Siemens HYB3164805J-50, HYB3164805J-60, HYB3164805T-50, HYB3164805T-60, HYB3164805TL-60 Datasheet

	8M x 8-Bit Dynamic RAM	HYB 3164805J/T(L) -50/-60
	(4k & 8k Refresh, EDO-version)
		HYB 3165805J/T(L) -50/-60

Preliminary Information

•8 388 608 words by 8-bit organization

•0 to 70 ˚C operating temperature

•Fast access and cycle time RAS access time:

50 ns (-50 version)

60 ns (-60 version) Cycle time:

84 ns (-50 version)

104 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version)

•Hyper page mode (EDO) cycle time 20 ns (-50 version)

25 ns (-60 version)

•Single + 3.3 V (± 0.3V) power supply

•Low power dissipation

max. 396 active mW ( HYB 3164805J/T(L)-50) max. 360 active mW ( HYB 3164805J/T(L)-60)

max. 504 active mW ( HYB 3165805J/T(L)-50) max. 432 active mW ( HYB 3165805J/T(L)-60) 7.2 mW standby (TTL)

720 W standby (MOS)

14.4 mW Self Refresh (L-version only)

•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes

•Hyper page mode (EDO) capability

•8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164805J/T(L))

•	4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165805J/T(L))
•	Plastic Package:
	P-SOJ-34-1	500 mil	HYB 3164(5)805J
	P-TSOPII-34-1	500 mil	HYB 3164(5)805T(L)

Semiconductor Group

149

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

This HYB3164(5)805 is a 64 MBit dynamic RAM organized 8 388 608 x 8 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)805 operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)805 to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)805TL parts have a very low power „sleep mode“ supported by Self Refresh.

Ordering Information

Type					Ordering	Package		Descriptions
					Code
HYB 3164805J-50					on request	P-SOJ-34-1	500 mil	DRAM (access time 50 ns)
HYB 3164805J-60					on request	P-SOJ-34-1	500 mil	DRAM (access time 60 ns)
HYB 3164805T-50					on request	P-TSOPII-34-1	500 mil	DRAM (access time 50 ns)
HYB 3164805T-60					on request	P-TSOPII-34-1	500 mil	DRAM (access time 60 ns)
HYB 3164805TL-50					on request	P-TSOPII-34-1	500 mil	DRAM (access time 50 ns)
HYB 3164805TL-60					on request	P-TSOPII-34-1	500 mil	DRAM (access time 60 ns)
HYB 3165805J-50					on request	P-SOJ-34-1	500 mil	DRAM (access time 50 ns)
HYB 3165805J-60					on request	P-SOJ-34-1	500 mil	DRAM (access time 60 ns)
HYB 3165805T-50					on request	P-TSOPII-34-1	500 mil	DRAM (access time 50 ns)
HYB 3165805T-60					on request	P-TSOPII-34-1	500 mil	DRAM (access time 60 ns)
HYB 3165805TL-50					on request	P-TSOPII-34-1	500 mil	DRAM (access time 50 ns)
HYB 3165805TL-60					on request	P-TSOPII-34-1	500 mil	DRAM (access time 60 ns)
Pin Names
A0-A12				Address Inputs for HYB 3164805J/T(L)
A0-A11				Address Inputs for HYB 3165805J/T(L)
				Row Address Strobe
RAS
				Output Enable
OE
I/O1-I/O8				Data Input/Output
				Column Address Strobe
CAS
				Read/Write Input
WRITE
Vcc				Power Supply ( + 3.3V)
Vss				Ground

Semiconductor Group

150

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

P-SOJ-34-1 (500 mil)

P-TSOPII-34-1 (500 mil)

Pin Configuration

Semiconductor Group

151

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

TRUTH TABLE

FUNCTION

RAS

CAS

WRITE

OE

ROW

COL

I/O1-

ADDR

ADDR

I/O4

Standby

H

H - X

X

X

X

X

High Impedance

Read

L

L

H

L

ROW

COL

Data Out

Early-Write

L

L

L

X

ROW

COL

Data In

Delayed-Write

L

L

H - L

H

ROW

COL

Data In

Read-Modify-Write

L

L

H - L

L - H

ROW

COL

Data Out, Data In

Hyper Page Mode Read

1st Cycle

L

H - L

H

L

ROW

COL

Data Out

2nd Cycle

L

H - L

H

L

n/a

COL

Data Out

Hyper Page Mode Write

1st Cycle

L

H - L

L

X

ROW

COL

Data In

2nd Cycle

L

H - L

L

X

n/a

COL

Data In

Hyper Page Mode RMW

1st Cycle

L

H - L

H - L

L - H

ROW

COL

Data Out, Data In

2st Cycle

L

H - L

H - L

L - H

n/a

COL

Data Out, Data In

only refresh

L

H

X

X

ROW

n/a

High Impedance

RAS

-before-

refresh

H - L

L

H

X

X

n/a

High Impedance

CAS

RAS

Test Mode Entry

H - L

L

L

X

X

n/a

High Impedance

Hidden Refresh

READ

L-H-L

L

H

L

ROW

COL

Data Out

WRITE

L-H-L

L

L

X

ROW

COL

Data In

Self Refresh

H - L

L

H

X

X

X

High Impedance

(L-version only)

Semiconductor Group

152

HYB3164(5)805J/T(L)-50/-60

8M x 8 EDO-DRAM

Block Diagram for HYB 3165805J/T(L)

Semiconductor Group

153

HYB3164(5)805J/T(L)-50/-60

8M x 8 EDO-DRAM

Block Diagram for HYB 3164805J/T(L)

Semiconductor Group

154

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

Absolute Maximum Ratings
Operating temperature range..............................................................................................	0 to 70 ˚C
Storage temperature range.........................................................................................	– 55 to 150 ˚C
Input/output voltage..................................................................................	-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................	-0.5V to 4.6 V
Power dissipation......................................................................................................................	1.0 W
Data out current (short circuit)..................................................................................................	50 mA

Note

Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

DC Characteristics

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165805J/T)

Parameter							Symbol	Limit Values		Unit	Note
								min.	max.
Input high voltage							VIH	2.0	Vcc+0.3	V	1)
Input low voltage							VIL	– 0.3	0.8	V	1)
Output high voltage (LVTTL)							VOH	2.4	–	V
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)							VOL	–	0.4	V
Output „L“level voltage (Iout = +2mA)
Output high voltage (LVCMOS)							VOH	Vcc-0.2	-	V
Output „H“ level voltage (Iout = -100uA)
Ouput low voltage (LVCMOS)							VOL	-	0.2	V
Output „L“ level voltage (Iout = +100uA)
Input leakage current,any input							II(L)	– 2	2	A
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current							IO(L)	– 2	2	A
(DO is disabled, 0 V < Vout < Vcc )
Average Vcc supply current:							ICC1
						-50 ns version		–	110 (140)	mA	2) 3) 4)
						-60 ns version		–	100 (120)	mA
						address cycling: tRC = tRC min.)
	(RAS,		CAS,
Standby Vcc supply current							ICC2	–	2	mA	–
	(RAS=CAS= Vih)

Semiconductor Group

155

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

DC Characteristics (cont’d)

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165805J/T)

Parameter

Symbol

Limit Values

Unit

Note

min.

max.

Average Vcc supply current, during RAS-only

ICC3

refresh cycles:

-50 ns version

–

110

(140)

mA

2) 4)

-60 ns version

–

100

(120)

mA

(RAS cycling: CAS = VIH: tRC = tRC min.)

Average Vcc supply current, during

ICC4

hyper page mode (EDO):

-50 ns version

–

115

(150)

mA

2) 3) 4)

-60 ns version

–

100

(120)

mA

address cycling: tHPC=tHPC min.)

(RAS

= VIL,

CAS,

Standby Vcc supply current

ICC5

–

200

A

–

(RAS=CAS= Vcc-0.2V)

Average Vcc supply current, during

-before-

ICC6

CAS

RAS

refresh mode:

-50 ns version

–

110

(140)

mA

2) 4)

-60 ns version

–

100

(120)

mA

cycling: tRC = tRC min.)

(RAS,

CAS

Self Refresh Current (L-version only)

ICC7

–

400

A

Average Power Supply Current during Self Refresh.

(CBR cycle with tRAS>TRASSmin, CAS held low,

WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

Capacitance

TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11,A12)

CI1

–

5

pF

Input capacitance

CI2

–

7

pF

(RAS,

CAS,

WRITE,

OE)

I/O capacitance (I/O1-I/O8)

CIO

–

7

pF

Semiconductor Group

156

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

AC Characteristics 5)6)

TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

common parameters

Random read or write cycle time

tRC

84

–

104

–

ns

precharge time

30

–

40

–

ns

RAS

tRP

pulse width

50

100k

60

100k

ns

RAS

tRAS

pulse width

8

10k

10

10k

ns

CAS

tCAS

Row address setup time

tASR

0

–

0

–

ns

Row address hold time

tRAH

8

–

10

–

ns

Column address setup time

tASC

0

–

0

–

ns

Column address hold time

tCAH

8

–

10

–

ns

to

delay time

12

37

14

45

ns

RAS

CAS

tRCD

to column address delay time

10

25

12

30

ns

RAS

tRAD

hold time

8

10

–

ns

RAS

tRSH

hold time

45

50

–

ns

CAS

tCSH

to

precharge time

5

–

5

–

ns

CAS

RAS

tCRP

Transition time (rise and fall)

tT

1

50

1

50

ns

7

Refresh period for HYB3164805

tREF

–

128

–

128

ms

Refresh period for HYB3165805

tREF

–

64

–

64

ms

Read Cycle

Access time from

RAS

tRAC

–

50

–

60

ns

8, 9

Access time from

–

13

–

15

ns

8, 9

CAS

tCAC

Access time from column address

tAA

–

25

–

30

ns

8,10

access time

–

13

–

15

ns

OE

tOEA

Column address to

lead time

25

–

30

–

ns

RAS

tRAL

Read command setup time

tRCS

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

ns

11

Read command hold time referenced to

tRRH

0

–

0

–

ns

11

RAS

Semiconductor Group

157

HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM

AC Characteristics (cont’d) 5)6)

TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

to output in low-Z

0

–

0

–

ns

8

CAS

tCLZ

Output buffer turn-off delay

tOFF

0

13

0

15

ns

12

Output buffer turn-off delay from

0

13

0

15

ns

12

OE

tOEZ

Data to

low delay

0

–

0

–

ns

13

CAS

tDZC

Data to

low delay

0

–

0

–

ns

13

OE

tDZO

high to data delay

13

–

15

–

ns

14

CAS

tCDD

high to data delay

13

–

15

–

ns

14

OE

tODD

Write Cycle

Write command hold time

tWCH

8

–

10

–

ns

Write command pulse width

tWP

7

–

10

–

ns

Write command setup time

tWCS

0

–

0

–

ns

15

Write command to

lead time

8

–

10

–

ns

RAS

tRWL

Write command to

lead time

8

–

10

–

ns

CAS

tCWL

Data setup time

tDS

0

–

0

–

ns

16

Data hold time

tDH

7

–

10

–

ns

16

Read-modify-Write Cycle

Read-write cycle time

tRWC

111

–

135

–

ns

to WE delay time

67

–

79

–

ns

15

RAS

tRWD

to

delay time

30

–

34

–

ns

15

CAS

WE

tCWD

Column address to

delay time

42

–

49

–

ns

15

WE

tAWD

command hold time

7

–

10

–

ns

OE

tOEH

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle time

tHPC

20

–

25

–

ns

precharge time

8

–

10

–

ns

CAS

tCP

Access time from

precharge

–

27

–

35

ns

7

CAS

tCPA

Output data hold time

tCOH

5

–

5

–

ns

pulse width in hyper page mode

50

200k

60

200k

ns

RAS

tRAS

Semiconductor Group

158