Siemens HYB3164405AJ-40, HYB3164405AJ-50, HYB3164405AJ-60, HYB3164405AT-40, HYB3164405AT-50 Datasheet

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16M x 4-Bit Dynamic RAM	HYB 3164405AJ/AT(L) -40/-50/-60

(4k & 8k Refresh, EDO-Version)	HYB 3165405AJ/AT(L) -40/-50/-60

Advanced Information

•16 777 216 words by 4-bit organization

•0 to 70 °C operating temperature

•Hyper Page Mode - EDO - operation

•Performance:

				-40	-50	-60

tRAC			access time	40	50	60	ns
tRAC		RAS	access time	40	50	60	ns
tCAC			access time	10	13	15	ns
tCAC	CAS		access time	10	13	15	ns
tAA	Access time from address			20	25	30	ns
tRC	Read/write cycle time			69	84	104	ns
tHPC	Hyper page mode (EDO)			16	20	25	ns
	cycle time

•Single + 3.3 V (± 0.3V) power supply

•Low power dissipation:

max. 450 active mW ( HYB 3164405AJ/AT(L)-40) max. 360 active mW ( HYB 3164405AJ/AT(L)-50) max. 324 active mW ( HYB 3164405AJ/AT(L)-60) max. 612 active mW ( HYB 3165405AJ/AT(L)-40) max. 405 active mW ( HYB 3165405AJ/AT(L)-50)

max. 432 active mW ( HYB 3165405AJ/AT(L)-60)

7.2mW standby (LVTTL)

3.24 mW standby (LVMOS)

720 μA standby for L-version

•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh

•Self refresh (L-version only)

•8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405AJ/AT)

4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405AJ/AT)

•256 msec refresh period for L-versions

•Plastic Package:

P-SOJ-32-1	400 mil	HYB 3164(5)400AJ
P-TSOPII-32-1	400 mil	HYB 3164(5)400AT(L)

Semiconductor Group

6.97

HYB3164(5)405AJ/AT(L)-40/-50/-60 16M x 4-DRAM

This HYB3164(5)405A is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated on an advanced second generation 64Mbit 0,35μm-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)405A operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)405A to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)405ATL parts have a very low power „sleep mode“ supported by Self Refresh.

Ordering Information

Type	Ordering	Package		Descriptions
	Code

8k-refresh versions:

HYB 3164405AJ-40		P-SOJ-32-1	400 mil	DRAM (access time 40 ns)
HYB 3164405AJ-50		P-SOJ-32-1	400 mil	DRAM (access time 50 ns)
HYB 3164405AJ-60		P-SOJ-32-1	400 mil	DRAM (access time 60 ns)
HYB 3164405AT-40		P-TSOPII-32-1	400 mil	DRAM (access time 40 ns)
HYB 3164405AT-50		P-TSOPII-32-1	400 mil	DRAM (access time 50 ns)
HYB 3164405AT-60		P-TSOPII-32-1	400 mil	DRAM (access time 60 ns)
HYB 3164405ATL-50		P-TSOPII-32-1	400 mil	DRAM (access time 50 ns)
HYB 3164405ATL-60		P-TSOPII-32-1	400 mil	DRAM (access time 60 ns)
4k-refresh versions:

HYB 3165405AJ-40		P-SOJ-32-1	400 mil	DRAM (access time 40 ns)
HYB 3165405AJ-50		P-SOJ-32-1	400 mil	DRAM (access time 50 ns)
HYB 3165405AJ-60		P-SOJ-32-1	400 mil	DRAM (access time 60 ns)
HYB 3165405AT-40		P-TSOPII-32-1	400 mil	DRAM (access time 40 ns)
HYB 3165405AT-50		P-TSOPII-32-1	400 mil	DRAM (access time 50 ns)
HYB 3165405AT-60		P-TSOPII-32-1	400 mil	DRAM (access time 60 ns)
HYB 3165405ATL-50		P-TSOPII-32-1	400 mil	DRAM (access time 50 ns)
HYB 3165405ATL-60		P-TSOPII-32-1	400 mil	DRAM (access time 60 ns)

Semiconductor Group

HYB3164(5)405AJ/AT(L)-40/-50/-60 16M x 4-DRAM

P-SOJ-32-1 (400 mil)

P-TSOPII-32-1 (400 mil)

VCC			1	32	VSS
	I/O1		2	31	I/O4
	I/O2		3	30	I/O3
	N.C.		4	29	N.C.
	N.C.		5	28	N.C.
	N.C.		6	27	N.C.
	N.C.			26
			7			CAS
			8	25
		WE					OE
	RAS		9	24		A12 / N.C. *
.
		A0	10	23			A11
		A1	11	22			A10
		A2	12	21			A9
		A3	13	20			A8
		A4	14	19			A7
		A5	15	18			A6
	VCC		16	17		VSS

* Pin 24 is A12 for HYB 3164405AJ/AT(L) and N.C. for HYB 3165405AJ/AT(L)

Pin Configuration

Pin Names

	A0-A12	Address Inputs for 8k-refresh version HYB 3164405AJ/AT(L)

	A0-A11	Address Inputs for 4k-refresh version HYB 3165405AJ/AT(L)

		Row Address Strobe
	RAS
		Output Enable
	OE
I/O1-I/O4		Data Input/Output

		Column Address Strobe
CAS

		Read/Write Input
WE

Vcc		Power Supply ( + 3.3V)

Vss		Ground

Semiconductor Group

HYB3164(5)405AJ/AT(L)-40/-50/-60 16M x 4-DRAM

TRUTH TABLE

FUNCTION

RAS

CAS

ROW

COL

I/O1-

ADDR

I/O4

Standby

H - X

High Impedance

Read

ROW

COL

Data Out

Early-Write

ROW

COL

Data In

Delayed-Write

H - L

ROW

COL

Data In

Read-Modify-Write

H - L

L - H

ROW

COL

Data Out, Data In

Hyper Page Mode Read

1st Cycle

H - L

ROW

COL

Data Out

2nd Cycle

H - L

n/a

COL

Data Out

Hyper Page Mode Write

1st Cycle

H - L

ROW

COL

Data In

2nd Cycle

H - L

n/a

COL

Data In

Hyper Page Mode RMW

1st Cycle

H - L

L - H

ROW

COL

Data Out, Data In

2st Cycle

H - L

L - H

n/a

COL

Data Out, Data In

only refresh

ROW

n/a

High Impedance

RAS

-before-

refresh

H - L

n/a

High Impedance

CAS

RAS

Test Mode Entry

H - L

n/a

High Impedance

Hidden Refresh

READ

L-H-L

ROW

COL

Data Out

WRITE

L-H-L

ROW

COL

Data In

Self Refresh

H - L

High Impedance

(L-version only)

Semiconductor Group

			HYB3164(5)405AJ/AT(L)-40/-50/-60
				16M x 4-DRAM
			I/O1 I/O2	I/O4
WE
CAS .	&		Data in	Data out
			Data in	Data out	OE
			Buffer	Buffer	OE
			Buffer	Buffer
	No. 2 Clock		4	4
	Generator		4	4
12	Column
12	Address		12	Column
A0	Buffer(12)		12	Decoder
A0	Buffer(12)
A1
A1
A2
A3	Refresh			Sense Amplifier	4
A4	Controller			Sense Amplifier	4
A4	Controller			I/O Gating
A5				I/O Gating
A5
A6
A7	Refresh			4096
A8	Counter (12)			4096
A8	Counter (12)			x4
A9				x4
A9	12
A10	12
A10
A11	Row		Row	Memory Array
12	Address	12	Decoder 4096	4096 x 4096 x 4
	Buffers(12)			4096 x 4096 x 4
	Buffers(12)
RAS	No. 1 Clock
RAS	Generator

Block Diagram for HYB 3165405AJ/AT(L)

Semiconductor Group

Siemens HYB3164405AJ-40, HYB3164405AJ-50, HYB3164405AJ-60, HYB3164405AT-40, HYB3164405AT-50 Datasheet

				HYB3164(5)405AJ/AT(L)-40/-50/-60
					16M x 4-DRAM
				I/O1 I/O2	I/O4
	WE
CAS .		&		Data in	Data out
				Data in	Data out	OE
				Buffer	Buffer	OE
				Buffer	Buffer
		No. 2 Clock			4
		Generator		4	4
	11	Column
	11	Address		11	Column
A0		Buffer(11)		11	Decoder
A0		Buffer(11)
A1
A1
A2
A3		Refresh			Sense Amplifier	4
A4		Controller			Sense Amplifier	4
A4		Controller			I/O Gating
A5					I/O Gating
A5
A6
A7		Refresh			2048
A8		Counter (13)			2048
A8		Counter (13)			x4
A9					x4
A9		13
A10		13
A10
A11		Row		Row	Memory Array
A12	13	Address	13	Decoder 8192	8192 x 2048 x 4
		Buffers(13)			8192 x 2048 x 4
		Buffers(13)
	RAS	No. 1 Clock
	RAS	Generator

Block Diagram for HYB 3164405AJ/AT(L)

Semiconductor Group

HYB3164(5)405AJ/AT(L)-40/-50/-60 16M x 4-DRAM

Absolute Maximum Ratings
Operating temperature range..............................................................................................	0 to 70 °C
Storage temperature range.........................................................................................	– 55 to 150 ° C
Input/output voltage..................................................................................	-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................	-0.5V to 4.6 V
Power dissipation......................................................................................................................	1.0 W
Data out current (short circuit)..................................................................................................	50 mA

Note

Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

DC Characteristics

TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V

Parameter	Symbol	Limit Values		Unit	Note

		min.	max.

Input high voltage	VIH	2.0	Vcc+0.3	V	1)
Input low voltage	VIL	– 0.3	0.8	V	1)
Output high voltage (LVTTL)	VOH	2.4	–	V
Output „H“ level voltage (Iout = -2mA)

Output low voltage (LVTTL)	VOL	–	0.4	V
Output „L“level voltage (Iout = +2mA)

Output high voltage (LVCMOS)	VOH	Vcc-0.2	-	V
Output „H“ level voltage (Iout = -100uA)

Ouput low voltage (LVCMOS)	VOL	-	0.2	V
Output „L“ level voltage (Iout = +100uA)

Input leakage current,any input	II(L)	– 2	2	μA
(0 V < Vin < Vcc , all other pins = 0 V

Output leakage current	IO(L)	– 2	2	μA
(DO is disabled, 0 V < Vout < Vcc )

Semiconductor Group

HYB3164(5)405AJ/AT(L)-40/-50/-60 16M x 4-DRAM

DC-Characteristics (cont’d)

TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V

Parameter

Symbol

refresh

version

Unit

Note

4k row

8k row

Operating Current

-40 ns version

ICC1

170

125

2) 3) 4)

-50 ns version

140

100

-60 ns version

115

address cycling: tRC = tRC min.)

(RAS,

CAS,

Standby Current

(RAS=CAS= Vih)

ICC2

–

RASOnlyRefreshCurrent:

ICC3

- 40 ns version

170

125

2) 4)

-50 ns version

140

100

-60 ns version

115

(RAS cycling: CAS = VIH: tRC = tRC min.)

Hyper Page Mode (EDO) Current:

ICC4

-40 ns version

140

2) 3) 4)

-50 ns version

105

-60 ns version

= VIL,

address cycling: tHPC=tHPC min.)

(RAS

CAS,

Standby Current

(RAS=CAS= Vcc-0.2V)

ICC5

900

μA

–

Standby Current

(L-Version)

ICC5

200

μA

–

(RAS=CAS= Vcc-0.2V)

Before

Refresh Current

ICC6

CAS

RAS

- 40 ns version

170

2) 4)

-50 ns version

140

-60 ns version

115

cycling: tRC = tRC min.)

(RAS,

CAS

Self Refresh Current (L-version only)

ICC7

400

μA

(CBR cycle with tRAS>TRASSmin,

held low,

CAS

= Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

Capacitance

TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11,A12)

CI1

–

Input capacitance

CI2

–

(RAS,

CAS,

WE,

OE)

I/O capacitance (I/O1-I/O4)

CIO

–

Semiconductor Group

HYB3164(5)405AJ/AT(L)-40/-50/-60 16M x 4-DRAM

AC Characteristics 5)6)

AC64-2E

TA = 0 to 70 °C, VCC = 3.3 V ± 0.3V , tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

- 50

- 60

min.

max.

min.

max.

min.

max.

Common Parameters

Random read or write cycle time

tRC

–

104

–

pulse width

tRAS

100k

RAS

pulse width

tCAS

100k

CAS

precharge time

tRP

–

RAS

precharge time

tCP

–

CAS

Row address setup time

tASR

–

Row address hold time

tRAH

–

Column address setup time

tASC

–

Column address hold time

tCAH

–

delay time

tRCD

RAS

CAS

to column address delay time

tRAD

RAS

hold time

tRSH

–

RAS

hold time

tCSH

–

CAS

precharge time

tCRP

–

CAS

RAS

Transition time (rise and fall)

Refresh period for 8k-refresh-version

tREF

–

128

–

128

–

128

Refresh period for 4k-refresh version

tREF

–

Refresh period for L-versions

tREF

–

256

–

256

–

256

Read Cycle

Access time from

tRAC

–

8, 9

RAS

Access time from

tCAC

–

8, 9

CAS

Access time from column address

tAA

–

8,10

access time

tOEA

–

Column address to

lead time

tRAL

–

RAS

Read command setup time

tRCS

–

Read command hold time

tRCH

–

Semiconductor Group

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