Siemens HYB3164165T-50, HYB3164165T-60, HYB3164165TL-50, HYB3164165TL-60, HYB3165165T-50 Datasheet

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	4M x 16-Bit Dynamic RAM	HYB 3164165T(L) -50/-60
	(4k & 8k Refresh, EDO-version)
		HYB 3165165T(L) -50/-60

Preliminary Information

•4 194 304 words by 16-bit organization

•0 to 70 ˚C operating temperature

•Fast access and cycle time RAS access time:

50 ns (-50 version)

60 ns (-60 version) Cycle time:

84 ns (-50 version)

104 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version)

•Hyper page mode (EDO) cycle time 20 ns (-50 version)

25 ns (-60 version)

•Single + 3.3 V (± 0.3V) power supply

•Low power dissipation

max. 396 active mW ( HYB 3164165T(L)-50) max. 360 active mW ( HYB 3164165T(L)-60)

max. 504 active mW ( HYB 3165165T(L)-50) max. 432 active mW ( HYB 3165165T(L)-60) 7.2 mW standby (TTL)

720 W standby (MOS)

14.4 mW Self Refresh (L-version only)

•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes

•Hyper page mode (EDO) capability

•2 CAS / 1 WE byte control

•	8192 refresh cycles/128 ms , 13	R/ 9C addresses (HYB 3164165T(L))
•	4096 refresh cycles/ 64 ms , 12	R/ 10C addresses (HYB 3165165T(L))
•	Plastic Package:
	P-TSOPII-54-1 500 mil		HYB 3164(5)165T(L)

Semiconductor Group

HYB3164(5)165T(L)-50/-60 4M x 16 EDO-DRAM

This HYB3164(5)165 is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)165 operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5)165 to be packaged in a 500mil wide TSOPII-54 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)165TL parts have a very low power „sleep mode“ supported by Self Refresh.

Ordering Information

Type

Ordering

Package

Descriptions

Code

HYB 3164165T-50

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 50 ns)

HYB 3164165T-60

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 60 ns)

HYB 3164165TL-50

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 50 ns)

HYB 3164165TL-60

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 60 ns)

HYB 3165165T-50

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 50 ns)

HYB 3165165T-60

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 60 ns)

HYB 3165165TL-50

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 50 ns)

HYB 3165165TL-60

on request

P-TSOPII-54-1

500 mil

EDO-DRAM (access time 60 ns)

Pin Names

A0-A12

Address Inputs for HYB 3164165T(L)

A0-A11

Address Inputs for HYB 3165165T(L)

Row Address Strobe

RAS

Output Enable

I/O1-I/O16

Data Input/Output

Column Address Strobe

UCAS,

LCAS

Read/Write Input

WRITE

Vcc

Power Supply ( + 3.3V)

Vss

Ground

Semiconductor Group

HYB3164(5)165T(L)-50/-60 4M x 16 EDO-DRAM

P-TSOPII-54-1 (500 mil)

* Pin 35 is A12 for HYB 3164165T(L) and N.C. for HYB 3165165T(L)

Pin Configuration

Semiconductor Group

HYB3164(5)165T(L)-50/-60 4M x 16 EDO-DRAM

TRUTH TABLE

FUNCTION		RAS	LCAS	UCA	WRIT	OE	ROW	COL	I/O1-
				S	E		ADD	ADD	I/O16
Standby		H	H - X	H - X	X	X	X	X	High Impedance

Read:Word		L	L	H	H	L	ROW	COL	Data Out

Read:Lower Byte		L	L	H	H	L	ROW	COL	Lower Byte:Data Out
									Upper-Byte:High-Z

Read:Upper Byte		L	H	L	H	L	ROW	COL	Lower Byte:High-Z
									Upper Byte:Data Out

Write:Word		L	L	L	L	X	ROW	COL	Data In
(Early-Write)

Write:Lower Byte		L	L	H	L	X	ROW	COL	Lower Byte:Data Out
(Early-Write)									Upper-Byte:High-Z

Write:Upper Byte		L	H	L	L	X	ROW	COL	Lower Byte:High-Z
(Early Write)									Upper Byte:Data Out

Read-Modify-		L	L	L	H - L	L - H	ROW	COL	Data Out, Data In
Write

Hyper Page Mode	1st	L	H - L	H - L	H	L	ROW	COL	Data Out
Read (Word)	Cycle

Hyper Page Mode	2nd	L	H - L	H - L	H	L	n/a	COL	Data Out
Read (Word)	Cycle

Hyper Page Mode	1st	L	H - L	H - L	L	X	ROW	COL	Data In
Early Write(Word)	Cycle

Hyper Page Mode	2nd	L	H - L	H - L	L	X	n/a	COL	Data In
Early Write(Word)	Cycle

Hyper Page Mode	1st	L	H - L	H - L	H - L	L - H	ROW	COL	Data Out, Data In
RMW	Cycle

Hyper Page Mode	2st	L	H - L	H - L	H - L	L - H	n/a	COL	Data Out, Data In
RMW	Cycle

RAS only refresh		L	H	H	X	X	ROW	n/a	High Impedance

CAS-before-RAS		H - L	L	L	H	X	X	n/a	High Impedance
refresh

Test Mode Entry		H - L	L	L	L	X	X	n/a	High Impedance

Hidden Refresh		L-H-	L	L	H	L	ROW	COL	Data Out
(Read)		L

Hidden Refresh		L-H-	L	L	L	X	ROW	COL	Data In
(Write)		L

Self Refresh		H-L	L	H	X	X	X	X	High Impedance
(L-version only)

Semiconductor Group

Siemens HYB3164165T-50, HYB3164165T-60, HYB3164165TL-50, HYB3164165TL-60, HYB3165165T-50 Datasheet

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

Block Diagram for HYB 3164165T(L)

Semiconductor Group

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

Block Diagram for HYB 3165165T(L)

Semiconductor Group

HYB3164(5)165T(L)-50/-60 4M x 16 EDO-DRAM

Absolute Maximum Ratings
Operating temperature range..............................................................................................	0 to 70 ˚C
Storage temperature range.........................................................................................	– 55 to 150 ˚C
Input/output voltage..................................................................................	-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................	-0.5V to 4.6 V
Power dissipation......................................................................................................................	1.0 W
Data out current (short circuit)..................................................................................................	50 mA

Note

Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

DC Characteristics

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165165J/T)

Parameter				Symbol	Limit Values		Unit	Note

					min.	max.

Input high voltage				VIH	2.0	Vcc+0.3	V	1)
Input low voltage				VIL	– 0.3	0.8	V	1)
Output high voltage (LVTTL)				VOH	2.4	–	V
Output „H“ level voltage (Iout = -2mA)

Output low voltage (LVTTL)				VOL	–	0.4	V
Output „L“level voltage (Iout = +2mA)

Output high voltage (LVCMOS)				VOH	Vcc-0.2	-	V
Output „H“ level voltage (Iout = -100uA)

Ouput low voltage (LVCMOS)				VOL	-	0.2	V
Output „L“ level voltage (Iout = +100uA)

Input leakage current,any input				II(L)	– 2	2	A
(0 V < Vin < Vcc , all other pins = 0 V

Output leakage current				IO(L)	– 2	2	A
(DO is disabled, 0 V < Vout < Vcc )

Average Vcc supply current:				ICC1
			-50 ns version		–	110 (140)	mA	2) 3) 4)
			-60 ns version		–	100 (120)	mA
			address cycling: tRC = tRC min.)
	(RAS,	CAS,	address cycling: tRC = tRC min.)

Standby Vcc supply current				ICC2	–	2	mA	–

	(RAS=CAS= Vih)

Semiconductor Group

HYB3164(5)165T(L)-50/-60 4M x 16 EDO-DRAM

DC Characteristics (cont’d)

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165165J/T)

Parameter

Symbol

Limit Values

Unit

Note

min.

max.

Average Vcc supply current, during RAS-only

ICC3

refresh cycles:

-50 ns version

–

110

(140)

2) 4)

-60 ns version

–

100

(120)

(RAS cycling: CAS = VIH: tRC = tRC min.)

Average Vcc supply current,

ICC4

Hyper page mode (EDO):

-50 ns version

–

115

(150)

2) 3) 4)

-60 ns version

–

100

(120)

address cycling: tHPC=tHPC min.)

(RAS

= VIL,

CAS,

Standby Vcc supply current

ICC5

–

200

–

(RAS=CAS= Vcc-0.2V)

Average Vcc supply current, during

-before-

ICC6

CAS

RAS

refresh mode:

-50 ns version

–

110

(140)

2) 4)

-60 ns version

–

100

(120)

cycling: tRC = tRC min.)

(RAS,

CAS

Self Refresh Current (L-version only)

ICC7

–

400

Average Power Supply Current during Self Refresh.

(CBR cycle with tRAS>TRASSmin, CAS held low,

WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

Capacitance

TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11,A12)

CI1

–

Input capacitance

CI2

–

(RAS,

CAS,

WRITE,

OE)

I/O capacitance (I/O1-I/O16)

CIO

–

Semiconductor Group

HYB3164(5)165T(L)-50/-60 4M x 16 EDO-DRAM

AC Characteristics 5)6)

TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

common parameters

Random read or write cycle time

tRC

–

104

–

precharge time

–

RAS

tRP

pulse width

100k

RAS

tRAS

pulse width

10k

CAS

tCAS

Row address setup time

tASR

–

Row address hold time

tRAH

–

Column address setup time

tASC

–

Column address hold time

tCAH

–

delay time

RAS

CAS

tRCD

to column address delay time

RAS

tRAD

hold time

–

RAS

tRSH

hold time

–

CAS

tCSH

precharge time

–

CAS

RAS

tCRP

Transition time (rise and fall)

Refresh period for HYB3164165

tREF

–

128

–

128

Refresh period for HYB3165165

tREF

–

Read Cycle

Access time from

RAS

tRAC

–

8, 9

Access time from

–

8, 9

CAS

tCAC

Access time from column address

tAA

–

8,10

access time

–

tOEA

Column address to

lead time

–

RAS

tRAL

Read command setup time

tRCS

–

Read command hold time

tRCH

–

Read command hold time referenced to

tRRH

–

RAS

to output in low-Z

–

CAS

tCLZ

Semiconductor Group

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