Siemens HYB514256BJL-50, HYB514256BJL-60, HYB514256BJL-70, HYB514256BL-50, HYB514256BL-60 Datasheet

256 K × 4-Bit Dynamic RAM	HYB 514256B/BJ-50/-60/-70
Low Power 256 K × 4-Bit Dynamic RAM	HYB 514256BL/BJL-50/-60/-70

Advanced Information

•262 144 words by 4-bit organization

•Fast access and cycle time 50 ns access time

95 ns cycle time (-50 version)

60 ns access time

110 ns cycle time (-60 version)

70 ns access time

130 ns cycle time (-70 version)

•Fast page mode cycle time 35 ns (-50 version)

40 ns (-60 version)

45 ns (-70 version)

•Low power dissipation

max. 495 mW active (-50 version) max. 440 mW active (-60 version) max. 385 mW active (-70 version) max. 5.5 mW standby

max. 1.1 mW standby for L-version

Ordering Information

• Single + 5 V (± 10 %) supply with a built-in VBB generator

• Output unlatched at cycle end allows twodimensional chip selection

• Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability

• All inputs, outputs and clocks TTL-compatible

• 512 refresh cycles/8 ms 512 refresh cycles/64 ms for L-version only

• Plastic Packages: P-DIP-20-2, P-SOJ-26/20-1

Type	Ordering Code	Package	Description
HYB 514256B-50	Q67100-Q1044	P-DIP-20-2	DRAM (access time 50ns)
HYB 514256B-60	Q67100-Q530	P-DIP-20-2	DRAM (access time 60 ns)
HYB 514256B-70	Q67100-Q433	P-DIP-20-2	DRAM (access time 70 ns)
HYB 514256BJ-50	Q67100-Q1054	P-SOJ-26/20-1	DRAM (access time 50 ns)
HYB 514256BJ-60	Q67100-Q536	P-SOJ-26/20-1	DRAM (access time 60 ns)
HYB 514256BJ-70	Q67100-Q537	P-SOJ-26/20-1	DRAM (access time 70 ns)
HYB 514256BL-50	on request	P-DIP-20-2	DRAM (access time 50 ns)
HYB 514256BL-60	Q67100-Q542	P-DIP-20-2	DRAM (access time 60 ns)
HYB 514256BL-70	Q67100-Q543	P-DIP-20-2	DRAM (access time 70 ns)
HYB 514256BJL-50	on request	P-SOJ-26/20-1	DRAM (access time 50 ns)
HYB 514256BJL-60	Q67100-Q608	P-SOJ-26/20-1	DRAM (access time 60 ns)
HYB 514256BJL-70	Q67100-Q607	P-SOJ-26/20-1	DRAM (access time 70 ns)

Semiconductor Group

55

01.95

HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM

The HYB 514256B/BJ/BL/BJL is the new generation dynamic RAM organized as 262 144 words by 4-bit. The HYB 514256B/BJ/BL/BJL utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514256B/BJ/BL/BJL to be packaged in a standard plastic P-DIP-20-2,or plastic P-SOJ-26/20-1. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. These HYB 514256BL/BJL are specially selected for battery backup applications.

Pin Definitions and Functions

Pin No.				Function
A0-A8				Address Inputs
				Row Address Strobe
RAS
				Output Enable
OE
I/O1-I/O4				Data Input/Output
				Column Address Strobe
CAS
				Read/Write Input
WE
VCC				Power Supply (+ 5 V)
VSS				Ground (0 V)
N.C.				No Connection

Semiconductor Group

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HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM

Pin Configuration

(top view)

P-SOJ-26/20-1

P-DIP-20-2

Semiconductor Group

57

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

Block Diagram

Semiconductor Group

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HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM

Absolute Maximum Ratings
Operating temperature range .........................................................................................	0 to + 70	˚C
Storage temperature range......................................................................................	– 55 to + 150	˚C
Soldering temperature ............................................................................................................	260	˚C
Soldering time.............................................................................................................................	10 s
Input/output voltage ........................................................................................................	– 1 to + 7 V
Power supply voltage......................................................................................................	– 1 to + 7 V
Power dissipation.....................................................................................................................	0.6 W
Data out current (short circuit) ................................................................................................	50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

TA = 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 %

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Input high voltage

VIH

2.4

6.5

V

1)

Input low voltage

VIL

– 1.0

0.8

V

1)

Output high voltage (IOUT = – 5 mA)

VOH

2.4

–

V

1)

Output low voltage (IOUT = 4.2 mA)

VOL

–

0.4

V

1)

Input leakage current, any input

II(L)

– 10

10

A

1)

(0 V ≤ VIN ≤ 6.5 V, all other pins = 0 V)

Output leakage current

IO(L)

– 10

10

A

1)

(DO is disabled, 0 V ≤ VOUT ≤ VCC)

Average VCC supply current:

ICC1

-50 version

–

90

mA

2) 3)

-60 version

–

80

mA

2) 3)

-70 version

–

70

mA

2) 3)

(RAS,

CAS,

address cycling: tRC = tRC min.)

Standby VCC supply current

=

= VIH)

ICC2

–

2

mA

–

(RAS

CAS

Average VCC supply current,

only mode:

ICC3

RAS

-50 version

–

90

mA

2)

-60 version

–

80

mA

2)

-70 version

–

70

mA

2)

(RAS

cycling:

CAS

= VIH : tRC = tRC min.)

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HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM

DC Characteristics (cont’d)

TA = 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 %

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Average VCC supply current, fast page mode:

ICC4

-60 version

–

70

mA

2) 3

-70 version

–

60

mA

2) 3)

-50 version

–

50

mA

2) 3)

= VIL ,

address cycling:

(RAS

CAS,

tPC = tPC min.)

Standby VCC supply current

ICC5

–

1

mA

1)

L-Version

–

200

A

1)

(RAS

=

CAS

= VCC – 0.2 V)

Average VCC supply current,

-before-RAS

ICC6

CAS

refresh mode:

–

90

mA

2)

-50 version

–

80

mA

2)

-60 version

–

70

mA

2)

-70 version

cycling: tRC = tRC min.)

(RAS,

CAS

For L-version only:

A

2)

Battery backup current:

ICC7

–

300

average power supply current,

battery backup mode:

(CAS

=

CAS

before

RAS

cycling or 0.2 V,

OE

= VCC – 0.2 V

WE

= VCC – 0.2 V or 0.2 V,

A0 to A8 = VCC – 0.2 V or 0.2 V,

I/O1 to I/O4 = VCC – 0.2 V or 0.2 V or open,

tRC = 125 s, tRAS = tRAS min. ~ 1 s)

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HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM

AC Characteristics 4) 13)

TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns

Parameter

Symbol

Limit Values

Unit

-50

-60

-70

min.

max.

min.

max.

min.

max.

Random read or write cycle

tRC

95

–

110

–

130

–

ns

time

Read-modify-write cycle time

tRWC

140

–

160

–

185

–

ns

Fast page mode cycle time

tPC

35

–

40

–

45

–

ns

Fast page mode read-modify-

tPRWC

80

–

90

–

100

–

ns

write cycle time

Access time from

tRAC

–

50

–

60

–

70

ns

RAS

6) 11)

Access time from

tCAC

–

15

–

15

–

20

ns

CAS

6) 11)

Access time from column

tAA

–

25

–

30

–

35

ns

address

6) 12)

Access time from

tCPA

–

30

–

35

–

40

ns

CAS

precharge

6) 12)

to output in low-Z

tCLZ

0

–

0

–

0

–

ns

CAS

4)

Output buffer

tOFF

0

15

0

20

0

20

ns

turn-off delay

7)

Transition time

tT

3

50

3

50

3

50

ns

(rise and fall)

5)

precharge time

tRP

35

–

40

–

50

–

ns

RAS

pulse width

tRAS

50

10.000

60

10.000

70

10.000

ns

RAS

pulse width

tRASP

50

100.000

60

100.000

70

100.000

ns

RAS

(fast page mode)

hold time

tRSH

15

–

15

–

20

–

ns

RAS

hold time

tCSH

50

–

60

–

70

–

ns

CAS

pulse width

tCAS

15

10.000

15

10.000

20

10.000

ns

CAS

hold time from

tRHCP

30

–

35

–

45

–

ns

RAS

CAS

precharge (Fast Page Mode)

precharge to

delay

tCPWD

55

–

60

–

65

–

ns

CAS

WE

time (FPM RMW)

to

delay time

tRCD

20

35

20

45

20

50

RAS

CAS

11)

to column address delay

tRAD

15

25

15

30

15

35

ns

RAS

time

12)

to

precharge time

tCRP

5

–

5

–

5

–

ns

CAS

RAS

precharge time

tCP

10

–

10

–

10

–

ns

CAS

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