8M x 8-Bit Dynamic RAM |
HYB 3164800AJ/AT(L) -40/-50/-60 |
( 4k & 8k Refresh) |
HYB 3165800AJ/AT(L) -40/-50/-60 |
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Advanced Information
•8 388 608 words by 8-bit organization
•0 to 70 °C operating temperature
•Fast Page Mode operation
•Performance:
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-40 |
-50 |
-60 |
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tRAC |
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access time |
40 |
50 |
60 |
ns |
RAS |
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tCAC |
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access time |
10 |
13 |
15 |
ns |
CAS |
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tAA |
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Access time from address |
20 |
25 |
30 |
ns |
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tRC |
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Read/write cycle time |
75 |
90 |
110 |
ns |
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tPC |
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Fast page mode cycle time |
30 |
35 |
40 |
ns |
•Single + 3.3 V (± 0.3V) power supply
•Low power dissipation:
max. 396 mW active ( HYB 3164800AJ/AT(L) -40) max. 324 mW active ( HYB 3164800AJ/AT(L) -50) max. 270 mW active ( HYB 3164800AJ/AT(L) -60)
max. 558 mW active ( HYB 3165800AJ/AT(L) -40) max. 468 mW active ( HYB 3165800AJ/AT(L) -50) max. 378 mW active ( HYB 3165800AJ/AT(L) -60)
7.2mW standby (LVTTL)
3.24 mW standby (LVCMOS)
720 μW standby for L-versions
•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only)
•8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800AJ/AT)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800AJ/AT)
•256 msec refresh period for L-versions
• Plastic Package: P-SOJ-32-1 |
400 mil |
HYB 3164(5)800AJ |
P-TSOPII-32-1 |
400 mil |
HYB 3164(5)800AT(L) |
Semiconductor Group |
1 |
6.97 |
HYB3164(5)800AJ/AT(L)-40/-50/-60 8M x 8-DRAM
This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in an advanced second generation 64Mbit 0,35 μm CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800AJ/AT to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5)800ATL parts (L-versions) have a very low power „sleep mode“ supported by Self Refresh
Ordering Information
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Type |
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Ordering |
Package |
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Descriptions |
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Code |
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HYB 3164800AJ-40 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 40 ns) |
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HYB 3164800AJ-50 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 50 ns) |
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HYB 3164800AJ-60 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 60 ns) |
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HYB 3164800AT-40 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 40 ns) |
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HYB 3164800AT-50 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 50 ns) |
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HYB 3164800AT-60 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 60 ns) |
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HYB 3165800AJ-40 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 40 ns) |
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HYB 3165800AJ-50 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 50 ns) |
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HYB 3165800AJ-60 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 60 ns) |
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HYB 3165800AT-40 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 40 ns) |
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HYB 3165800AT-50 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 50 ns) |
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HYB 3165800AT-60 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 60 ns) |
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HYB 3164(5)800ATL |
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P-TSOPII-32-1 |
400 mil |
Low Power DRAMs |
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Pin Names |
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A0-A12 |
Address Inputs for 8k-refresh versions HYB 3164800AJ/AT(L) |
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A0-A11 |
Address Inputs for 4k-refresh versions HYB 3165800AJ/AT(L) |
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Row Address Strobe |
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RAS |
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Output Enable |
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OE |
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I/O1-I/O8 |
Data Input/Output |
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Column Address Strobe |
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CAS |
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Read/Write Input |
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WE |
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Vcc |
Power Supply ( + 3.3V) |
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Vss |
Ground |
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Semiconductor Group |
2 |
HYB3164(5)800AJ/AT(L)-40/-50/-60 8M x 8-DRAM
P-SOJ-32-1 (400 mil)
P-TSOPII-32-1 (400 mil)
O
VCC |
1 |
32 |
VSS |
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I/O1 |
2 |
31 |
I/O8 |
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I/O2 |
3 |
30 |
I/O7 |
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I/O3 |
4 |
29 |
I/O6 |
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I/O4 |
5 |
28 |
I/O5 |
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N.C. |
6 |
27 |
VSS |
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26 |
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VCC |
7 |
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CAS |
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8 |
25 |
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WRITE |
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OE |
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RAS |
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9 |
24 |
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A12 / N.C. * |
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. |
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A0 |
10 |
23 |
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A11 |
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A1 |
11 |
22 |
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A10 |
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A2 |
12 |
21 |
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A9 |
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A3 |
13 |
20 |
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A8 |
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A4 |
14 |
19 |
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A7 |
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A5 |
15 |
18 |
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A6 |
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VCC |
16 |
17 |
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VSS |
* Pin 24 is A12 for HYB 3164800AJ/AT(L) and N.C. for HYB 3165800AJ/AT(L)
Pin Configuration
Semiconductor Group |
3 |
HYB3164(5)800AJ/AT(L)-40/-50/-60 8M x 8-DRAM
TRUTH TABLE
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FUNCTION |
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RAS |
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CAS |
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WE |
OE |
ROW |
COL |
I/O1- |
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ADDR |
ADDR |
I/O8 |
Standby |
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H |
H - X |
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X |
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X |
X |
X |
High Impedance |
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Read |
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L |
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L |
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H |
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L |
ROW |
COL |
Data Out |
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Early-Write |
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L |
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L |
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L |
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X |
ROW |
COL |
Data In |
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Delayed-Write |
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L |
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L |
H - L |
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H |
ROW |
COL |
Data In |
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Read-Modify-Write |
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L |
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L |
H - L |
L - H |
ROW |
COL |
Data Out, Data In |
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Fast Page Mode Read |
1st Cycle |
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L |
H - L |
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H |
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L |
ROW |
COL |
Data Out |
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2nd Cycle |
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L |
H - L |
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H |
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L |
n/a |
COL |
Data Out |
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Fast Page Mode Early |
1st Cycle |
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L |
H - L |
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L |
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X |
ROW |
COL |
Data In |
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Write |
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2nd Cycle |
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L |
H - L |
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L |
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X |
n/a |
COL |
Data In |
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Fast Page Mode RMW |
1st Cycle |
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L |
H - L |
H - L |
L - H |
ROW |
COL |
Data Out, Data In |
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2st Cycle |
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L |
H - L |
H - L |
L - H |
n/a |
COL |
Data Out, Data In |
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RAS only refresh |
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L |
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H |
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X |
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X |
ROW |
n/a |
High Impedance |
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CAS-before-RAS refresh |
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H - L |
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L |
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H |
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X |
X |
n/a |
High Impedance |
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Test Mode Entry |
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H - L |
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L |
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L |
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X |
X |
n/a |
High Impedance |
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Hidden Refresh |
READ |
L-H-L |
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L |
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H |
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L |
ROW |
COL |
Data Out |
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WRITE |
L-H-L |
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L |
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L |
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X |
ROW |
COL |
Data In |
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Semiconductor Group |
4 |
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HYB3164(5)800AJ/AT(L)-40/-50/-60 |
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8M x 8-DRAM |
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I/O1 I/O2 |
I/O8 |
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WE |
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CAS . |
& |
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Data in |
Data out |
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OE |
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Buffer |
Buffer |
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No. 2 Clock |
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8 |
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Generator |
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8 |
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11 |
Column |
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Address |
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11 |
Column |
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A0 |
Buffer(11) |
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Decoder |
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A1 |
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A2 |
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A3 |
Refresh |
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Sense Amplifier |
8 |
A4 |
Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
Refresh |
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2048 |
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A8 |
Counter (12) |
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x8 |
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A9 |
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12 |
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A10 |
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A11 |
Row |
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Row |
Memory Array |
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12 |
Address |
12 |
Decoder 4096 |
4096 x 2048 x 8 |
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Buffers(12) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3165800AJ/AT(L)
Semiconductor Group |
5 |
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HYB3164(5)800AJ/AT(L)-40/-50/-60 |
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8M x 8-DRAM |
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I/O1 I/O2 |
I/O8 |
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WE |
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CAS . |
& |
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Data in |
Data out |
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OE |
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Buffer |
Buffer |
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No. 2 Clock |
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8 |
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Generator |
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8 |
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10 |
Column |
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Address |
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10 |
Column |
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A0 |
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Buffer(10) |
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Decoder |
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A1 |
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A2 |
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A3 |
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Refresh |
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Sense Amplifier |
8 |
A4 |
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Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
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Refresh |
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1024 |
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A8 |
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Counter (13) |
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x8 |
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A9 |
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13 |
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A10 |
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A11 |
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Row |
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Row |
Memory Array |
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A12 |
13 |
Address |
13 |
Decoder 8192 |
8192 x 1024 x 8 |
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Buffers(13) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3164800AJ/AT(L)
Semiconductor Group |
6 |
HYB3164(5)800AJ/AT(L)-40/-50/-60 8M x 8-DRAM
Absolute Maximum Ratings |
|
Operating temperature range.............................................................................................. |
0 to 70 °C |
Storage temperature range......................................................................................... |
– 55 to 150 ° C |
Input/output voltage.................................................................................. |
-0.5 to min (Vcc+0.5,4.6) V |
Power supply voltage.................................................................................................... |
-0.5V to 4.6 V |
Power dissipation...................................................................................................................... |
1.0 W |
Data out current (short circuit).................................................................................................. |
50 mA |
Note |
|
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter |
Symbol |
Limit Values |
Unit |
Note |
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min. |
max. |
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Input high voltage |
VIH |
2.0 |
Vcc+0.3 |
V |
1) |
Input low voltage |
VIL |
– 0.3 |
0.8 |
V |
1) |
Output high voltage (LVTTL) |
VOH |
2.4 |
– |
V |
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Output „H“ level voltage (Iout = -2mA) |
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Output low voltage (LVTTL) |
VOL |
– |
0.4 |
V |
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Output „L“level voltage (Iout = +2mA) |
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Output high voltage (LVCMOS) |
VOH |
Vcc-0.2 |
- |
V |
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Output „H“ level voltage (Iout = -100uA) |
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Ouput low voltage (LVCMOS) |
VOL |
- |
0.2 |
V |
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Output „L“ level voltage (Iout = +100uA) |
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Input leakage current,any input |
II(L) |
– 2 |
2 |
μA |
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(0 V < Vin < Vcc , all other pins = 0 V |
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Output leakage current |
IO(L) |
– 2 |
2 |
μA |
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(DO is disabled, 0 V < Vout < Vcc ) |
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Semiconductor Group |
7 |
HYB3164(5)800AJ/AT(L)-40/-50/-60 8M x 8-DRAM
DC-Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter |
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Symbol |
refresh |
version |
Unit |
Note |
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4k |
8k |
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Operating Current |
-40 ns version |
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ICC1 |
155 |
110 |
mA |
2) 3) 4) |
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-50 ns version |
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130 |
90 |
mA |
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-60 ns version |
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105 |
75 |
mA |
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address cycling: tRC = tRC min.) |
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(RAS, |
CAS, |
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Standby Current |
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ICC2 |
2 |
2 |
mA |
– |
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(RAS=CAS= Vih) |
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RASOnlyRefreshCurrent: |
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ICC3 |
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110 |
mA |
2) 4) |
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- |
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-40 ns version |
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155 |
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-50ns version |
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130 |
90 |
mA |
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-60 ns version |
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105 |
75 |
mA |
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(RAS cycling: CAS = VIH: tRC = tRC min.) |
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Fast Page Mode Current: |
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ICC4 |
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-40 ns version |
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70 |
70 |
mA |
2) 3) 4) |
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-50 ns version |
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60 |
60 |
mA |
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-60 ns version |
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50 |
50 |
mA |
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= VIL, |
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address cycling: tPC=tPC min.) |
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(RAS |
CAS, |
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Standby Current |
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ICC5 |
900 |
900 |
μA |
– |
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(RAS=CAS= Vcc-0.2V) |
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Standby Current (L-Version) |
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ICC5 |
200 |
200 |
μA |
– |
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(RAS=CAS= Vcc-0.2V) |
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Before |
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Refresh Current |
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ICC6 |
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CAS |
RAS |
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-40 ns version |
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155 |
155 |
mA |
2) 4) |
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-50 ns version |
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130 |
130 |
mA |
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-60 ns version |
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105 |
105 |
mA |
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cycling: tRC = tRC min.) |
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(RAS, |
CAS |
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Self Refresh Current (L-version only) |
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ICC7 |
400 |
400 |
μA |
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(CBR cycle with tRAS>TRASSmin, |
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held low, |
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CAS |
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WE |
= Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) |
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Semiconductor Group |
8 |