Siemens HYB314100BJ-50, HYB314100BJ-60, HYB314100BJ-70, HYB314100BJL-50, HYB314100BJL-60 Datasheet

4M x 1-Bit Dynamic RAM	HYB 314100BJ/BJL -50/-60/-70
Low Power 4M x 1-Bit Dynamic RAM

Advanced Information

•4 194 304 words by 1-bit organization

•0 to 70 ˚C operating temperature

•Fast Page Mode Operation

•Performance:

				-50	-60	-70
tRAC			access time	50	60	70	ns
		RAS
tCAC			access time	13	15	20	ns
		CAS
tAA		Access time from address		25	30	35	ns
tRC		Read/Write cycle time		95	110	130	ns
tPC		Fast page mode cycle time		35	40	45	ns

•Single + 3.3 V (± 0.3 V ) supply with a built-in Vbb generator

•Low power dissipation

max. 252 mW active (-50 version) max. 216 mW active (-60 version) max. 198 mW active (-70 version)

•Standby power dissipation:

7.2mW max. standby (TTL)

3.6mW max. standby (CMOS)

720 μW max. standby (CMOS) for Low Power Version

•Output unlatched at cycle end allows two-dimensional chip selection

•Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability

•All inputs and outputs TTL-compatible

•1024 refresh cycles / 16 ms

•1024 refresh cycles / 128 ms Low Power Version

•Plastic Packages: P-SOJ-26/20-5 with 300 mil width

Semiconductor Group

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4.96

HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM

The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100BJ/BJL to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic device families.

Ordering Information

Type	Ordering Code	Package	Descriptions
HYB 314100BJ-50	Q67100-Q2035	P-SOJ-26/20-5	3.3 V DRAM
			(access time 50 ns)
HYB 314100BJ-60	Q67100-Q2037	P-SOJ-26/20-5	3.3 V DRAM
			(access time 60 ns)
HYB 314100BJ-70	Q67100-Q2039	P-SOJ-26/20-5	3.3 V DRAM
			(access time 70 ns)
HYB 314100BJL-50	on request	P-SOJ-26/20-5	3.3 V Low Power DRAM
			(access time 50 ns)
HYB 314100BJL-60	on request	P-SOJ-26/20-5	3.3 V Low Power DRAM
			(access time 60 ns)
HYB 314100BJL-70	on request	P-SOJ-26/20-5	3.3 V Low Power DRAM
			(access time 70 ns)

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HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM

Pin Configuration

(top view)

P-SOJ-26/20-5

Pin Names

A0-A10			Address Input
			Row Address Strobe
RAS
			Column Address Strobe
CAS
			Read/Write Input
WE
DI			Data In
DO			Data Out
VCC			Power Supply (+ 3.3 V)
VSS			Ground (0 V)
N.C.			No Connection

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Block Diagram

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HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM

Absolute Maximum Ratings
Operating temperature range ............................................................................................	0 to 70	˚C
Storage temperature range......................................................................................	– 55 to + 150	˚C
Input/output voltage ...........................................................................	– 1 to + min (VCC + 0.5, 4.6)		V
Power Supply voltage ..................................................................................................	– 1 to + 4.6		V
Data out current (short circuit) ................................................................................................	50 mA

Note: Stresses above those listed under damage of the device. Exposure periods may affect device reliability.

DC Characteristics

"Absolute Maximum Ratings" may cause permanent to absolute maximum rating conditions for extended

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Input high voltage

VIH

2.0

VCC + 0.5

V

1)

Input low voltage

VIL

– 1.0

0.8

V

1)

TTL Output high voltage (IOUT = – 2 mA)

VOH

2.4

–

V

1)

TTL Output low voltage (IOUT = 2 mA)

VOL

–

0.4

V

1)

CMOS Output high voltage (IOUT = – 100 μA)

VOH

VCC – 0.2

–

V

CMOS Output low voltage (IOUT = 100 μA)

VOL

–

0.2

V

Input leakage current, any input

II(L)

– 10

10

μA

1)

(0 V < Vin < VCC + 0.3 V, all other input = 0 V)

Output leakage current

IO(L)

– 10

10

μA

1)

(DO is disabled, 0 V < VOUT < VCC)

Average VCC supply current

ICC1

mA

2) 3)4)

-50 version

_

70

-60 version

–

60

-70 version

–

55

Standby VCC supply current

ICC2

–

2

mA

–

(RAS

=

CAS

=

WE

= VIH)

2)4)

Average VCC supply current during RAS-only

ICC3

mA

refresh cycles

-50 version

_

70

-60 version

–

60

-70 version

–

55

Average VCC supply current during fast page

ICC4

mA

2) 3)4)

mode operation

-50 version

–

50

-60 version

–

45

-70 version

40

Standby VCC supply current

ICC5

–

1

mA

1)

=

=

= VCC – 0.2 V)

200

μA

L-version

(RAS

CAS

WE

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HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM

DC Characteristics (cont’d)

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Average VCC supply current during

ICC6

mA

2)4)

CAS

before

RAS

refresh mode

-50 version

–

70

-60 version

–

60

-70 version

–

55

For Low Power Version only:

ICC7

–

250

μA

–

Battery backup current (average power supply

current in battery backup mode):

before

cycling or 0.2 V,

(CAS

=

CAS

RAS

WE

= VCC – 0.2 V or 0.2 V,

A0 to A10 = VCC – 0.2 V or 0.2 V;

DI = VCC – 0.2 V or 0.2 V or open,

tRC = 125 μs, tRAS = tRAS min = 1 μs)

Capacitance

TA = 0 to 70 ˚C; VCC = 3.3 V ± 0.3 V; f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A10, DI)

CI1

–

5

pF

Input capacitance

CI2

–

7

pF

(RAS,

CAS,

WE)

Output capacitance (DO)

CIO

–

7

pF

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HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM

AC Characteristics 5)6)

TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max.

min.

max.

min.

max.

Common Parameters

Random read or write cycle time

tRC

95

–

110

–

130

–

ns

precharge time

tRP

35

–

40

–

50

–

ns

RAS

pulse width

tRAS

50

10k

60

10k

70

10k

ns

RAS

pulse width

tCAS

13

10k

15

10k

20

10k

ns

CAS

Row address setup time

tASR

0

–

0

–

0

–

ns

Row address hold time

tRAH

8

–

10

–

10

–

ns

Column address setup time

tASC

0

–

0

–

0

–

ns

Column address hold time

tCAH

10

–

15

–

15

–

ns

to

delay time

tRCD

18

37

20

45

20

50

ns

RAS

CAS

to column address delay

tRAD

13

25

15

30

15

35

ns

RAS

time

hold time

tRSH

13

15

–

20

–

ns

RAS

hold time

tCSH

50

60

–

70

–

ns

CAS

to

precharge time

tCRP

5

–

5

–

5

–

ns

CAS

RAS

Transition time (rise and fall)

tT

3

50

3

50

3

50

ns

7

Refresh period

tREF

–

16

–

16

–

16

ms

Refresh period for L-version

tREF

–

128

–

128

–

128

ms

Read Cycle

Access time from

RAS

tRAC

–

50

–

60

–

70

ns

8, 9

Access time from

tCAC

–

13

–

15

–

20

ns

8, 9

CAS

Access time from column

tAA

–

25

–

30

–

35

ns

8,10

address

Column addr. to

lead time

tRAL

25

–

30

–

35

–

ns

RAS

Read command setup time

tRCS

0

–

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

0

–

ns

11

Read command hold time

tRRH

0

–

0

–

0

–

ns

11

referenced to

RAS

to output in low-Z

tCLZ

0

–

0

–

0

–

ns

8

CAS

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