Siemens HYB314265BJ-45, HYB314265BJ-50, HYB314265BJL-45, HYB314265BJL-50, HYB514265BJ-400 Datasheet

256K x 16-Bit EDO-Dynamic RAM	HYB 514265BJ-400/40/-45/-50
	HYB 314265BJ(L)-45/-50

Preliminary Information

•262 144 words by 16-bit organization

•0 to 70 °C operating temperature

•EDO - Hyper Page Mode

•Performance:

	-400	-40	-45	-50
trc	69	69	79	89	ns
trac	40	40	45	50	ns
tcac	10	10	12	13	ns
taa	20	20	22	25	ns
thpc	12,5	15	18	20	ns
thpc	80	66	55	50	MHz

•Low Power dissipation - Active(max.):

120mA / 120mA / 105mA / 95 mA

- Standby : TTL Inputs (max.)	2.0 mA
- Standby: CMOS Inputs (max.) 1.0 mA
- Standby (L-version)	200 μA

• Power Supply:

HYB 514265BJ-400	+5 V	±5%
HYB 514265BJ-40	+5 V	±10%
HYB 514265BJ-45	+5 V	±10%
HYB 514265BJ-50	+5 V	±10%
HYB 314265BJ(L)-45	+3.3 V	±0.3 V
HYB 314265BJ(L)-50	+3.3 V	±0.3 V

•Read, write, read-modify-write, CAS -before RAS refresh, RAS only refresh, hidden refresh mode

•Low Power Version (L) with Self Refresh and 250 μA self refresh current

•2 CAS / 1 WE control

•All inputs and outputs TTL-compatible

•512 refresh cycles / 16 ms

512 refresh cycles / 128 ms (L-version)

•Plastic Packages: P-SOJ-40-3 400 mil width

The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment.

The HYB314265BJL parts have a very low power “sleep mode“ supported by Self Refresh.

Semiconductor Group

1

6.96

HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Ordering Information

Type	Ordering	Package	Description
	Code
5 V versions:
HYB 514265BJ-400	Q67100-3033	P-SOJ-40-3	5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-40	Q67100-3039	P-SOJ-40-3	5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-45	Q67100-3035	P-SOJ-40-3	5 V 45 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-50	Q67100-3036	P-SOJ-40-3	5 V 50 ns 256 K x 16 EDO-DRAM
3.3 V versions:
HYB 314265BJ-45	on request	P-SOJ-40-3	3.3 V 45 ns 256 K x 16 EDODRAM
HYB 314265BJ-50	on request	P-SOJ-40-3	3.3 V 50 ns 256 K x 16 EDODRAM
HYB 314265BJL-45	on request	P-SOJ-40-3	3.3 V Low Power 45 ns 256 K x 16 EDODRAM
HYB 314265BJL-50	on request	P-SOJ-40-3	3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM

Truth Table

RAS

LCAS

UCAS

WE

OE

I/O1-I/O8

I/O9-I/O16

Operation

H

H

H

H

H

High-Z

High-Z

Standby

L

H

H

H

H

High-Z

High-Z

Refresh

L

L

H

H

L

Dout

High-Z

Lower byte read

L

H

L

H

L

High-Z

Dout

Upper byte read

L

L

L

H

L

Dout

Dout

Word read

L

L

H

L

H

Din

Don't care

Lower byte write

L

H

L

L

H

Don't care

Din

Upper byte write

L

L

L

L

H

Din

Din

Word write

L

L

L

H

H

High-Z

High-Z

Pin Names

A0-A8

Address Inputs

Row Address Strobe

RAS

Column Address Strobe

UCAS,

LCAS

Read/Write Input

WE

Output Enable

OE

I/O1 – I/O16

Data Input/Output

VCC

Power Supply:

+ 5 V for HYB 514265,

+ 3.3 V for HYB 314265

VSS

Ground (0 V)

N.C.

No Connection

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Pin Configuration

(top view)

P-SOJ-40-3

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Block Diagram

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Absolute Maximum Ratings
Operating temperature range ........................................................................................	0 to + 70	°C
Storage temperature range.....................................................................................	– 55 to + 150	°C
Input/output voltage for HYB 514265................................................	– 0.5 to min. (VCC + 0.5, 7.0)		V
Power supply voltage for HYB 514265 ...........................................................................	– 1 to + 7		V
Input/output voltage for HYB 314265................................................	– 0.5 to min. (VCC + 0.5, 4.6)		V
Power supply voltage for HYB 314265 .....................................................................	– 0.5 to + 4.6		V
Data out current (short circuit) ................................................................................................	50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics for HYB514265

TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 % (± 5 % for -400 version) , tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Input high voltage

VIH

2.4

VCC + 0.5

V

1

Input low voltage

VIL

– 0.5

0.8

V

1

Output high voltage (IOUT = – 5.0 mA)

VOH

2.4

–

V

1

Output low voltage (IOUT = 4.2 mA)

VOL

–

0.4

V

1

Input leakage current, any input

II(L)

– 10

10

μA

1

(0 V < VIN < 7 V, all other inputs = 0 V)

Output leakage current

IO(L)

– 10

10

μA

1

(DO is disabled, 0 V < VOUT < VCC)

Average VCC supply current:

ICC1

–

2, 3, 4

-400 version

120

mA

-40 version

120

-45 version

105

-50 version

95

Standby VCC supply current

ICC2

–

2

mA

–

(RAS

=

LCAS

=

UCAS

=

WE

= VIH)

Average VCC supply current during

-only

ICC3

–

RAS

refresh cycles:

-400 version

120

mA

2, 4

-40 version

120

-45 version

105

-50 version

95

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Average VCC supply current during

ICC4

–

2, 3, 4

hyper page mode (EDO) operation: -400 version

110

mA

-40 version

90

-45 version

75

-50 version

65

Standby VCC supply current

ICC5

–

1

mA

1

(RAS

=

LCAS

=

UCAS

=

WE

= VCC – 0.2 V)

Standby VCC supply current (L-version only)

ICC5

–

200

μA

1

(RAS

=

LCAS

=

UCAS

=

WE

= VCC – 0.2 V)

Average VCC supply current during

ICC6

–

2, 4

CAS

-before-

RAS

refresh mode:

-400 version

120

mA

-40 version

120

-45 version

105

-50 version

95

DC Characteristics for 314265

TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Input high voltage

VIH

2.0

VCC + 0.5

V

1

Input low voltage

VIL

– 0.5

0.8

V

1

TTL Output high voltage (IOUT = – 2.0 mA)

VOH

2.4

–

V

1

TTL Output low voltage (IOUT = 2 mA)

VOL

–

0.4

V

1

CMOS Output high voltage (IOUT = – 100 μA)

VOH

2.4

–

V

1

CMOS Output low voltage (IOUT = 100 μA)

VOL

–

0.4

V

1

Input leakage current, any input

II(L)

– 10

10

μA

1

(0 V < VIN < VCC + 0.3 V, all other inputs = 0 V)

Output leakage current

IO(L)

– 10

10

μA

1

(DO is disabled, 0 V < VOUT < VCC + 0.3 V)

Average VCC supply current:

ICC1

–

2, 3, 4

-45 version

105

mA

-50 version

95

Standby VCC supply current

ICC2

–

2

mA

–

(RAS

=

LCAS

=

UCAS

=

WE

= VIH)

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Average VCC supply current during

ICC3

–

2, 4

RAS

-only refresh cycles:

mA

-45 version

105

-50 version

95

Average VCC supply current during hyper page

ICC4

–

2, 3, 4

mode (EDO) operation:

mA

-45 version

75

-50 version

65

Standby VCC supply current

ICC5

–

1

mA

1

(RAS

=

LCAS

=

UCAS

=

WE

= VCC – 0.2 V)

Standby VCC supply current (L-version only)

ICC5

–

200

μA

1

(RAS

=

LCAS

=

UCAS

=

WE

= VCC – 0.2 V)

Average VCC supply current during

-

–

CAS

ICC6

2, 4

before-

RAS

refresh mode:

mA

-45 version

105

-50 version

95

Self Refresh Current (L-version only)

ICC7

–

250

μA

CBR cycle with

RAS

>trasss(min), CAS held low;

WE = VCC – 0.2 V,

Addresses and Din = VCC – 0.2 V or 0.2 V

Capacitance

TA = 0 to 70 °C; f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A8)

CI1

–

5

pF

Input capacitance

CI2

–

7

pF

(RAS,

UCAS,

LCAS,

WE,

OE)

Output capacitance (l/O1 to l/O16)

CIO

–

7

pF

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

AC Characteristics 5) 6)

TA = 0 to 70 °C, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-400

-40

min.

max.

min.

max.

Common Parameters

Random read or write cycle time

tRC

69

–

69

–

ns

precharge time

tRP

25

–

25

–

ns

RAS

pulse width

tRAS

40

10k

40

10k

ns

RAS

pulse width

tCAS

4.5

10k

6

10k

ns

CAS

precharge time

tCP

4

–

5

–

ns

CAS

Row address setup time

tASR

0

–

0

–

ns

Row address hold time

tRAH

5

–

5

–

ns

Column address setup time

tASC

0

–

0

–

ns

Column address hold time

tCAH

5

–

5

–

ns

to

delaytime

tRCD

9

30

9

30

ns

RAS

CAS

to column address delay time

tRAD

7

20

7

20

ns

RAS

hold time

tRSH

6

–

6

–

ns

RAS

hold time

tCSH

32

–

32

–

ns

CAS

to

precharge time

tCRP

5

–

5

–

ns

CAS

RAS

Transition time(rise and fall)

tT

1

50

1

50

ns

7

Refresh period

tREF

16

–

16

–

ms

Read Cycle

Access time from

tRAC

–

40

–

40

ns

8, 9

RAS

Access time from

tCAC

–

10

–

10

ns

8, 9

CAS

Access time from column address

tAA

–

17

–

20

ns

8,10

access time

tOEA

–

10

–

10

ns

OE

Column address to

lead time

tRAL

20

–

20

–

ns

RAS

Read command setup time

tRCS

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

ns

11

Read command hold time ref. to

tRRH

0

–

0

–

ns

11

RAS

to output inlow-Z

tCLZ

0

–

0

–

ns

8

CAS

Output buffer turn-off delay from

tOFF

0

–

0

10

ns

12

CAS

Semiconductor Group

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HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM

Parameter

Symbol

Limit Values

Unit

Note

-400

-40

min.

max.

min.

max.

Output buffer turn-off delay from

tOEZ

0

10

0

10

ns

12

OE

Data to

low delay

tDZO

0

–

0

ns

13

OE

high to data delay

tCDD

8

–

8

–

ns

14

CAS

high to data delay

tODD

8

–

8

–

ns

14

OE

Data to

low delay

tDZC

0

–

0

–

ns

13

CAS

Write Cycle

Write command hold time

tWCH

5

–

5

–

ns

Write command pulse width

tWP

5

–

5

–

ns

Write command setup time

tWCS

0

–

0

–

ns

15

Write command to

lead time

tRWL

10

–

10

–

ns

RAS

Write command to

lead time

tCWL

10

–

10

–

ns

CAS

Data setup time

tDS

0

–

0

–

ns

16

Data hold time

tDH

5

–

5

–

ns

16

Data to

low delay

tDZC

0

–

0

–

ns

13

CAS

Read-modify-Write Cycle

Read-write cycle time

tRWC

93

–

93

–

ns

to

delay time

tRWD

52

–

52

–

ns

15

RAS

WE

to

delay time

tCWD

22

–

22

–

ns

15

CAS

WE

Column address to

delay time

tAWD

32

–

32

–

ns

15

WE

command hold time

tOEH

5

–

5

–

ns

OE

Hyper Page Mode (EDO) Cycle

Hyper page mode cycle time

tHPC

12.5

–

15

–

ns

Access time from

precharge

tCPA

–

17

–

21

ns

7

CAS

Output data hold time

tCOH

3

–

3

–

ns

pulse width in hyper page mode

tRAS

40

200k

40

200k

ns

RAS

hold time from

precharge

tRHCP

17

–

21

–

ns

RAS

CAS

Semiconductor Group

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