16M x 4-Bit Dynamic RAM |
HYB 3164405BJ/BT(L) -40/-50/-60 |
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(4k & 8k Refresh, EDO-version) |
HYB 3165405BJ/BT(L) -40/-50/-60 |
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Preliminary Information
•16 777 216 words by 4-bit organization
•0 to 70 °C operating temperature
•Hyper Page Mode - EDO - operation
•Performance:
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-40 |
-50 |
-60 |
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tRAC |
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access time |
40 |
50 |
60 |
ns |
RAS |
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tCAC |
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access time |
10 |
13 |
15 |
ns |
CAS |
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tAA |
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Access time from address |
20 |
25 |
30 |
ns |
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tRC |
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Read/write cycle time |
69 |
84 |
104 |
ns |
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tHPC |
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Hyper page mode (EDO) |
16 |
20 |
25 |
ns |
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cycle time |
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•Single + 3.3 V (± 0.3V) power supply
•Low power dissipation:
max. 306 active mW ( HYB 3164405BJ/BT(L)-40) max. 252 active mW ( HYB 3164405BJ/BT(L)-50) max. 216 active mW ( HYB 3164405BJ/BT(L)-60) max. 486 active mW ( HYB 3165405BJ/BT(L)-40) max. 396 active mW ( HYB 3165405BJ/BT(L)-50) max. 324 active mW ( HYB 3165405BJ/BT(L)-60)
7.2mW standby (LVTTL)
3.6 mW standby (LVMOS)
720 A standby for L-version
•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh
•Self refresh (L-version only)
•8192 refresh cycles/128 ms, 13 R/ 11C addresses (HYB 3164405BJ/BT)
4096 refresh cycles / 64 ms, 12 R/ 12C addresses (HYB 3165405BJ/BT)
•128 msec refresh period for L-versions
•Plastic Package:
P-SOJ-32-1 |
400 mil HYB 3164(5)400BJ |
P-TSOPII-32-1 |
400 mil HYB 3164(5)400BT(L) |
Semiconductor Group |
1 |
12.97 |
HYB3164(5)405BJ/BT(L)-40/-50/-60 16M x 4-DRAM
This HYB3164(5)405B is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated in SIEMENS’most advanced 0,25 m-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)405B operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400B to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)405BTL parts have a very low power „sleep mode“supported by Self Refresh.
Ordering Information
Type |
Ordering |
Package |
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Descriptions |
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Code |
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8k-refresh versions: |
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HYB 3164405BJ-40 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 40 ns) |
HYB 3164405BJ-50 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 50 ns) |
HYB 3164405BJ-60 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 60 ns) |
HYB 3164405BT-40 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 40 ns) |
HYB 3164405BT-50 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 50 ns) |
HYB 3164405BT-60 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 60 ns) |
HYB 3164405BTL-50 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 50 ns) |
HYB 3164405BTL-60 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 60 ns) |
4k-refresh versions: |
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HYB 3165405BJ-40 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 40 ns) |
HYB 3165405BJ-50 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 50 ns) |
HYB 3165405BJ-60 |
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P-SOJ-32-1 |
400 mil |
DRAM (access time 60 ns) |
HYB 3165405BT-40 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 40 ns) |
HYB 3165405BT-50 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 50 ns) |
HYB 3165405BT-60 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 60 ns) |
HYB 3165405BTL-50 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 50 ns) |
HYB 3165405BTL-60 |
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P-TSOPII-32-1 |
400 mil |
DRAM (access time 60 ns) |
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Semiconductor Group |
2 |
HYB3164(5)405BJ/BT(L)-40/-50/-60 16M x 4-DRAM
P-SOJ-32-1 (400 mil)
P-TSOPII-32-1 (400 mil)
O
VCC |
1 |
32 |
VSS |
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I/O1 |
2 |
31 |
I/O4 |
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I/O2 |
3 |
30 |
I/O3 |
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N.C. |
4 |
29 |
N.C. |
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N.C. |
5 |
28 |
N.C. |
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N.C. |
6 |
27 |
N.C. |
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N.C. |
26 |
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7 |
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CAS |
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WE |
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8 |
25 |
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OE |
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RAS |
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9 |
24 |
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A12 / N.C. * |
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. |
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A0 |
10 |
23 |
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A11 |
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A1 |
11 |
22 |
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A10 |
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A2 |
12 |
21 |
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A9 |
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A3 |
13 |
20 |
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A8 |
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A4 |
14 |
19 |
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A7 |
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A5 |
15 |
18 |
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A6 |
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VCC |
16 |
17 |
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VSS |
* Pin 24 is A12 for HYB 3164405BJ/BT(L) and N.C. for HYB 3165405BJ/BT(L)
Pin Configuration
Pin Names
A0-A12 |
Address Inputs for 8k-refresh version HYB 3164405BJ/BT(L) |
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A0-A11 |
Address Inputs for 4k-refresh version HYB 3165405BJ/BT(L) |
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Row Address Strobe |
RAS |
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Output Enable |
OE |
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I/O1-I/O4 |
Data Input/Output |
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Column Address Strobe |
CAS |
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Read/Write Input |
WE |
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Vcc |
Power Supply ( + 3.3V) |
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Vss |
Ground |
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Semiconductor Group |
3 |
HYB3164(5)405BJ/BT(L)-40/-50/-60 16M x 4-DRAM
TRUTH TABLE
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FUNCTION |
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RAS |
CAS |
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WE |
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OE |
ROW |
COL |
I/O1- |
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ADDR |
ADDR |
I/O4 |
Standby |
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H |
H - X |
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X |
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X |
X |
X |
High Impedance |
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Read |
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L |
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L |
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H |
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L |
ROW |
COL |
Data Out |
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Early-Write |
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L |
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L |
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L |
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X |
ROW |
COL |
Data In |
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Delayed-Write |
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L |
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L |
H - L |
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H |
ROW |
COL |
Data In |
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Read-Modify-Write |
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L |
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L |
H - L |
L - H |
ROW |
COL |
Data Out, Data In |
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Hyper Page Mode Read |
1st Cycle |
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L |
H - L |
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H |
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L |
ROW |
COL |
Data Out |
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2nd Cycle |
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L |
H - L |
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H |
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L |
n/a |
COL |
Data Out |
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Hyper Page Mode Write |
1st Cycle |
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L |
H - L |
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L |
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X |
ROW |
COL |
Data In |
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2nd Cycle |
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L |
H - L |
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L |
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X |
n/a |
COL |
Data In |
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Hyper Page Mode RMW |
1st Cycle |
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L |
H - L |
H - L |
L - H |
ROW |
COL |
Data Out, Data In |
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2st Cycle |
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L |
H - L |
H - L |
L - H |
n/a |
COL |
Data Out, Data In |
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only refresh |
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L |
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H |
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X |
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X |
ROW |
n/a |
High Impedance |
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RAS |
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-before- |
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refresh |
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H - L |
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L |
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H |
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X |
X |
n/a |
High Impedance |
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CAS |
RAS |
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Test Mode Entry |
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H - L |
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L |
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L |
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X |
X |
n/a |
High Impedance |
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Hidden Refresh |
READ |
L-H-L |
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L |
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H |
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L |
ROW |
COL |
Data Out |
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WRITE |
L-H-L |
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L |
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L |
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X |
ROW |
COL |
Data In |
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Self Refresh |
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H - L |
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L |
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H |
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X |
X |
X |
High Impedance |
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(L-version only) |
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Semiconductor Group |
4 |
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HYB3164(5)405BJ/BT(L)-40/-50/-60 |
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16M x 4-DRAM |
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I/O1 I/O2 |
I/O4 |
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WE |
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CAS . |
& |
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Data in |
Data out |
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OE |
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Buffer |
Buffer |
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No. 2 Clock |
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4 |
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Generator |
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4 |
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12 |
Column |
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Address |
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12 |
Column |
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A0 |
Buffer(12) |
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Decoder |
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A1 |
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A2 |
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A3 |
Refresh |
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Sense Amplifier |
4 |
A4 |
Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
Refresh |
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4096 |
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A8 |
Counter (12) |
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x4 |
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A9 |
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12 |
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A10 |
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A11 |
Row |
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Row |
Memory Array |
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12 |
Address |
12 |
Decoder 4096 |
4096 x 4096 x 4 |
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Buffers(12) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3164405BJ/BT(L)
Semiconductor Group |
5 |
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HYB3164(5)405BJ/BT(L)-40/-50/-60 |
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16M x 4-DRAM |
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I/O1 I/O2 |
I/O4 |
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WE |
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CAS . |
& |
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Data in |
Data out |
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OE |
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Buffer |
Buffer |
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No. 2 Clock |
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4 |
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Generator |
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4 |
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11 |
Column |
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Address |
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11 |
Column |
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A0 |
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Buffer(11) |
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Decoder |
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A1 |
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A2 |
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A3 |
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Refresh |
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Sense Amplifier |
4 |
A4 |
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Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
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Refresh |
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2048 |
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A8 |
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Counter (13) |
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x4 |
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A9 |
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13 |
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A10 |
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A11 |
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Row |
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Row |
Memory Array |
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A12 |
13 |
Address |
13 |
Decoder 8192 |
8192 x 2048 x 4 |
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Buffers(13) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3165405BJ/BT(L)
Semiconductor Group |
6 |
HYB3164(5)405BJ/BT(L)-40/-50/-60 16M x 4-DRAM
Absolute Maximum Ratings |
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Operating temperature range.............................................................................................. |
0 to 70 °C |
Storage temperature range......................................................................................... |
– 55 to 150 °C |
Input/output voltage.................................................................................. |
-0.5 to min (Vcc+0.5,4.6) V |
Power supply voltage.................................................................................................... |
-0.5V to 4.6 V |
Power dissipation............................................................................................................... |
.....0.62 W |
Data out current (short circuit)................................................................................................ |
..50 mA |
Note
Stresses above those listed under „Absolute Maximum Ratings“may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter |
Symbol |
Limit Values |
Unit |
Note |
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min. |
max. |
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Input high voltage |
VIH |
2.0 |
Vcc+0.3 |
V |
1) |
Input low voltage |
VIL |
– 0.3 |
0.8 |
V |
1) |
Output high voltage (LVTTL) |
VOH |
2.4 |
– |
V |
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Output „H“level voltage (Iout = -2mA) |
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Output low voltage (LVTTL) |
VOL |
– |
0.4 |
V |
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Output „L“level voltage (Iout = +2mA) |
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Output high voltage (LVCMOS) |
VOH |
Vcc-0.2 |
- |
V |
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Output „H“level voltage (Iout = -100uA) |
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Ouput low voltage (LVCMOS) |
VOL |
- |
0.2 |
V |
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Output „L“level voltage (Iout = +100uA) |
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Input leakage current,any input |
II(L) |
– 2 |
2 |
A |
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(0 V < Vin < Vcc , all other pins = 0 V |
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Output leakage current |
IO(L) |
– 2 |
2 |
A |
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(DO is disabled, 0 V < Vout < Vcc ) |
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Semiconductor Group |
7 |
HYB3164(5)405BJ/BT(L)-40/-50/-60 16M x 4-DRAM
DC-Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter |
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Symbol |
refresh |
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version |
Unit |
Note |
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4k row |
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8k row |
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Operating Current |
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ICC1 |
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-40 ns version |
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135 |
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85 |
mA |
2) 3) 4) |
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-50 ns version |
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110 |
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70 |
mA |
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- |
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-60 ns version |
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90 |
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60 |
mA |
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address cycling: tRC = tRC min.) |
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(RAS, |
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CAS, |
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Standby Current |
(RAS=CAS= Vih) |
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ICC2 |
2 |
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2 |
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mA |
– |
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RASOnlyRefreshCurrent: |
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ICC3 |
135 |
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85 |
mA |
2) 4) |
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- |
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- 40 ns version |
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-50 ns version |
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110 |
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70 |
mA |
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-60 ns version |
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90 |
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60 |
mA |
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(RAS cycling: CAS = VIH: tRC = tRC min.) |
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Hyper Page Mode (EDO) Current: |
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ICC4 |
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-40 ns version |
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100 |
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100 |
mA |
2) 3) 4) |
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-50 ns version |
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65 |
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65 |
mA |
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-60 ns version |
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45 |
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45 |
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address cycling: tHPC=tHPC min.) |
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(RAS |
= VIL, |
CAS, |
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Standby Current |
(RAS=CAS= Vcc-0.2V) |
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ICC5 |
1 |
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1 |
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mA |
– |
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Standby Current |
(L-Version) |
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ICC5 |
200 |
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200 |
A |
– |
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(RAS=CAS= Vcc-0.2V) |
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Before |
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Refresh Current |
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ICC6 |
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CAS |
RAS |
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- 40 ns version |
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135 |
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85 |
mA |
2) 4) |
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-50 ns version |
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110 |
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70 |
mA |
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-60 ns version |
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90 |
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60 |
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(RAS, |
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CAS |
cycling: tRC = tRC min.) |
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Self Refresh Current (L-version only) |
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ICC7 |
400 |
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400 |
A |
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(CBR cycle with tRAS>TRASSmin, |
CAS |
held low, |
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WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) |
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Capacitance |
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TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V, f = 1 MHz |
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Parameter |
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Symbol |
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Limit Values |
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Unit |
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min. |
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max. |
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Input capacitance (A0 to A11,A12) |
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CI1 |
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– |
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5 |
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pF |
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Input capacitance |
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CI2 |
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– |
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7 |
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pF |
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(RAS, |
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CAS, |
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WE, |
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OE) |
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I/O capacitance (I/O1-I/O4) |
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CIO |
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– |
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7 |
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pF |
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Semiconductor Group |
8 |
HYB3164(5)405BJ/BT(L)-40/-50/-60 16M x 4-DRAM
AC Characteristics 5)6) |
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AC64-2E |
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TA = 0 to 70 °C, VCC = 3.3 V ± 0.3V , tT = 2 ns |
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Parameter |
Symbol |
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Limit Values |
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Unit |
Note |
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- |
40 |
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- 50 |
- 60 |
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min. |
max. |
min. |
max. |
min. |
max. |
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Common Parameters |
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Random read or write cycle time |
tRC |
69 |
– |
84 |
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– |
104 |
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– |
ns |
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pulse width |
tRAS |
40 |
100k |
50 |
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100k |
60 |
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100k |
ns |
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RAS |
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pulse width |
tCAS |
6 |
100k |
8 |
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100k |
10 |
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100k |
ns |
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CAS |
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precharge time |
tRP |
25 |
– |
30 |
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– |
40 |
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– |
ns |
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RAS |
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precharge time |
tCP |
6 |
– |
8 |
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– |
10 |
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– |
ns |
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CAS |
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Row address setup time |
tASR |
0 |
– |
0 |
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– |
0 |
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– |
ns |
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Row address hold time |
tRAH |
5 |
– |
7 |
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– |
10 |
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– |
ns |
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Column address setup time |
tASC |
0 |
– |
0 |
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– |
0 |
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– |
ns |
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Column address hold time |
tCAH |
5 |
– |
7 |
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– |
10 |
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– |
ns |
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to |
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delay time |
tRCD |
9 |
30 |
11 |
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37 |
14 |
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45 |
ns |
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RAS |
CAS |
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to column address delay time |
tRAD |
7 |
20 |
9 |
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25 |
12 |
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30 |
ns |
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RAS |
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hold time |
tRSH |
6 |
– |
8 |
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10 |
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– |
ns |
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RAS |
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hold time |
tCSH |
32 |
– |
40 |
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48 |
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– |
ns |
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CAS |
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to |
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precharge time |
tCRP |
5 |
– |
5 |
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– |
5 |
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– |
ns |
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CAS |
RAS |
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Transition time (rise and fall) |
tT |
1 |
50 |
1 |
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50 |
1 |
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50 |
ns |
7 |
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Refresh period for 8k-refresh-version |
tREF |
– |
128 |
– |
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128 |
– |
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128 |
ms |
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Refresh period for 4k-refresh version |
tREF |
– |
64 |
– |
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64 |
– |
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64 |
ms |
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Refresh period for L-versions |
tREF |
– |
128 |
– |
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128 |
– |
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128 |
ms |
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Read Cycle |
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Access time from |
RAS |
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tRAC |
– |
40 |
– |
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50 |
– |
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60 |
ns |
8, 9 |
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Access time from |
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tCAC |
– |
10 |
– |
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13 |
– |
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15 |
ns |
8, 9 |
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CAS |
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Access time from column address |
tAA |
– |
20 |
– |
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25 |
– |
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30 |
ns |
8,10 |
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access time |
tOEA |
– |
10 |
– |
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13 |
– |
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15 |
ns |
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OE |
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Column address to |
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lead time |
tRAL |
20 |
– |
25 |
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– |
30 |
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– |
ns |
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RAS |
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Read command setup time |
tRCS |
0 |
– |
0 |
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– |
0 |
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– |
ns |
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Read command hold time |
tRCH |
0 |
– |
0 |
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– |
0 |
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– |
ns |
11 |
Semiconductor Group |
9 |