4M x 16-Bit Dynamic RAM
( 8k, 4k & 2k Refresh)
Advanced Information
HYB 3164160AT(L) -40/-50/-60 HYB 3165160AT(L) -40/-50/-60 HYB 3166160AT(L) -40/-50/-60
•4 194 304 words by 16-bit organization
•0 to 70 °C operating temperature
•Fast Page Mode operation
•Performance:
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-40 |
-50 |
-60 |
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tRAC |
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access time |
40 |
50 |
60 |
ns |
RAS |
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tCAC |
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access time |
10 |
13 |
15 |
ns |
CAS |
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tAA |
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Access time from address |
20 |
25 |
30 |
ns |
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tRC |
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Read/write cycle time |
75 |
90 |
110 |
ns |
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tPC |
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Fast page mode cycle time |
30 |
35 |
40 |
ns |
•Single + 3.3 V (± 0.3V) power supply
•Low power dissipation:
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-40 |
-50 |
-60 |
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HYB3166160AT(L) |
900 |
558 |
396 |
mW |
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HYB3165160AT(L) |
756 |
468 |
324 |
mW |
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HYB3164160AT(L) |
612 |
378 |
270 |
mW |
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7.2 mW standby (TTL)
3.24 mW standby (MOS)
720 μW standby for L-version
•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only)
•2 CAS / 1 WE byte control
• 8192 refresh cycles /128 ms , 13 |
R/ 9C addresses (HYB 3164160AT) |
4096 refresh cycles / 64 ms , 12 |
R/ 10C addresses (HYB 3165160AT) |
2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT)
•256 msec refresh period for L-versions
• Plastic Package: P-TSOPII-50 400 mil
Semiconductor Group |
1 |
6.97 |
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated on an advanced second generation 64Mbit 0,35μm-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160AT to be packaged in a 400 mil wide TSOP-50 package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts (L-version) have a very low power „sleep mode“ supported by Self Refresh.
Ordering Information
Type |
Ordering |
Package |
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Descriptions |
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Code |
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8k-refresh versions: |
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HYB 3164160AT-40 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 40 ns) |
HYB 3164160AT-50 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 50 ns) |
HYB 3164160AT-60 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 60 ns) |
HYB 3164160ATL-50 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 50 ns) |
HYB 3164160ATL-60 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 60 ns) |
4k-refresh versions: |
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HYB 3165160AT-40 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 40 ns) |
HYB 3165160AT-50 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 50 ns) |
HYB 3165160AT-60 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 60 ns) |
HYB 3165160ATL-50 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 50 ns) |
HYB 3165160ATL-60 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 60 ns) |
2k-refresh versions: |
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HYB 3166160AT-40 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 40 ns) |
HYB 3166160AT-50 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 50 ns) |
HYB 3166160AT-60 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 60 ns) |
HYB 3166160ATL-50 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 50 ns) |
HYB 3166160ATL-60 |
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P-TSOPII-50 |
400 mil |
DRAM (access time 60 ns) |
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Semiconductor Group |
2 |
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
Pin Configuration
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.
A0
A1
A2
A3
A4
A5
VCC
P-TSOPII-50 (400 mil)
O |
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1 |
50 |
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VSS |
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2 |
49 |
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I/O16 |
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3 |
48 |
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I/O15 |
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4 |
47 |
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I/O14 |
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5 |
46 |
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I/O13 |
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6 |
45 |
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VSS |
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7 |
44 |
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I/O12 |
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8 |
43 |
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I/O11 |
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9 |
42 |
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I/O10 |
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10 |
41 |
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I/O9 |
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11 |
40 |
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N.C. |
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12 |
39 |
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VSS |
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13 |
38 |
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LCAS. |
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. |
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14 |
37 |
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UCAS |
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15 |
36 |
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OE |
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16 |
35 |
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N.C. |
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17 |
34 |
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N.C. |
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18 |
33 |
A12/N.C. * |
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19 |
32 |
A11/N.C.** |
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20 |
31 |
A10 |
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21 |
30 |
A9 |
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22 |
29 |
A8 |
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23 |
28 |
A7 |
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24 |
27 |
A6 |
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25 |
26 |
VSS |
*Pin 33 is A12 for HYB 3164160AT(L) and N.C. for HYB 3165(6)160AT(L)
**Pin 32 is A11 for HYB 3164(5)160AT(L) and N.C. for HYB 3166160AT(L)
Pin Names
A0-A12 |
Address Inputs for 8k-refresh version HYB 3164160AT(L) |
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A0-A11 |
Address Inputs for 4k-refresh version HYB 3165160AT(L) |
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A0-A10 |
Address Inputs for 2k-refresh version HYB 3166160AT(L) |
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Row Address Strobe |
RAS |
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Output Enable |
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OE |
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I/O1-I/O16 |
Data Input/Output |
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Column Address Strobe |
UCAS,LCAS |
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Read/Write Input |
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WE |
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Vcc |
Power Supply ( + 3.3V) |
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Vss |
Ground |
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Semiconductor Group |
3 |
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
TRUTH TABLE
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FUNCTION |
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RAS |
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LCAS |
UCAS |
WE |
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OE |
ROW |
COL |
I/O1- |
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ADD |
ADD |
I/O16 |
Standby |
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H |
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H - X |
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H - X |
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X |
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X |
X |
X |
High Impedance |
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Read:Word |
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L |
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L |
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H |
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H |
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L |
ROW |
COL |
Data Out |
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Read:Lower Byte |
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L |
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L |
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H |
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H |
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L |
ROW |
COL |
Lower Byte:Data Out |
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Upper-Byte:High-Z |
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Read:Upper Byte |
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L |
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H |
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L |
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H |
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L |
ROW |
COL |
Lower Byte:High-Z |
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Upper Byte:Data Out |
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Write:Word |
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L |
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L |
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L |
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L |
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X |
ROW |
COL |
Data In |
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(Early-Write) |
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Write:Lower Byte |
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L |
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L |
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H |
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L |
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X |
ROW |
COL |
Lower Byte:Data Out |
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(Early-Write) |
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Upper-Byte:High-Z |
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Write:Upper Byte |
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L |
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H |
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L |
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L |
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X |
ROW |
COL |
Lower Byte:High-Z |
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(Early Write) |
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Upper Byte:Data Out |
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Read-Modify- |
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L |
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L |
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L |
H - L |
L - H |
ROW |
COL |
Data Out, Data In |
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Write |
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Fast Page Mode |
1st |
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L |
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H - L |
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H - L |
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H |
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L |
ROW |
COL |
Data Out |
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Read (Word) |
Cycle |
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Fast Page Mode |
2nd |
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L |
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H - L |
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H - L |
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H |
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L |
n/a |
COL |
Data Out |
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Read (Word) |
Cycle |
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Fast Page Mode |
1st |
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L |
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H - L |
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H - L |
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L |
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X |
ROW |
COL |
Data In |
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Early Write(Word) |
Cycle |
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Fast Page Mode |
2nd |
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L |
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H - L |
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H - L |
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L |
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X |
n/a |
COL |
Data In |
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Early Write(Word) |
Cycle |
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Fast Page Mode |
1st |
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L |
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H - L |
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H - L |
H - L |
L - H |
ROW |
COL |
Data Out, Data In |
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RMW |
Cycle |
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Fast Page Mode |
2st |
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L |
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H - L |
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H - L |
H - L |
L - H |
n/a |
COL |
Data Out, Data In |
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RMW |
Cycle |
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RAS only refresh |
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L |
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H |
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H |
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X |
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X |
ROW |
n/a |
High Impedance |
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CAS-before-RAS |
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H - L |
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L |
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L |
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H |
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X |
X |
n/a |
High Impedance |
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refresh |
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Test Mode Entry |
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H - L |
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L |
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L |
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L |
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X |
X |
n/a |
High Impedance |
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Hidden Refresh |
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L-H- |
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L |
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L |
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H |
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L |
ROW |
COL |
Data Out |
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(Read) |
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L |
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Hidden Refresh |
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L-H- |
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L |
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L |
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L |
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X |
ROW |
COL |
Data In |
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(Write) |
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L |
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Semiconductor Group |
4 |
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HYB3164(5/6)160AT(L)-40/-50/-60 |
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4M x 16-DRAM |
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I/O1 I/O2 |
I/O16 |
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WE |
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LCASUCAS .. |
& |
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Data in |
Data out |
OE |
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Buffer |
Buffer |
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No. 2 Clock |
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16 |
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Generator |
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16 |
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9 |
Column |
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Address |
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9 |
Column |
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A0 |
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Buffer(9) |
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Decoder |
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A1 |
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A2 |
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A3 |
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Refresh |
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Sense Amplifier |
16 |
A4 |
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Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
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Refresh |
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512 |
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A8 |
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Counter (13) |
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x16 |
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A9 |
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13 |
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A10 |
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A11 |
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Row |
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Row |
Memory Array |
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A12 |
13 |
Address |
13 |
Decoder 8192 |
8192x512x16 |
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Buffers(13) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3164160AT(L)
Semiconductor Group |
5 |
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HYB3164(5/6)160AT(L)-40/-50/-60 |
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4M x 16-DRAM |
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I/O1 I/O2 |
I/O16 |
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WE |
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LCASUCAS .. |
& |
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Data in |
Data out |
OE |
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Buffer |
Buffer |
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No. 2 Clock |
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16 |
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Generator |
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16 |
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10 |
Column |
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Address |
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10 |
Column |
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A0 |
Buffer(10) |
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Decoder |
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A1 |
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A2 |
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A3 |
Refresh |
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Sense Amplifier |
16 |
A4 |
Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
Refresh |
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1024 |
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A8 |
Counter (12) |
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x16 |
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A9 |
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12 |
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A10 |
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A11 |
Row |
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Row |
Memory Array |
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12 |
Address |
12 |
Decoder 4096 |
4096x1024x16 |
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Buffers(12) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3165160AT(L)
Semiconductor Group |
6 |
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HYB3164(5/6)160AT(L)-40/-50/-60 |
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4M x 16-DRAM |
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I/O1 I/O2 |
I/O16 |
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LCASUCAS .. |
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Data in |
Data out |
OE |
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Buffer |
Buffer |
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No. 2 Clock |
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16 |
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Generator |
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16 |
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11 |
Column |
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Address |
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11 |
Column |
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A0 |
Buffer(11) |
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Decoder |
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A1 |
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A2 |
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A3 |
Refresh |
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Sense Amplifier |
16 |
A4 |
Controller |
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I/O Gating |
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A5 |
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A6 |
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A7 |
Refresh |
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2048 |
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A8 |
Counter (11) |
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x16 |
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A9 |
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11 |
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A10 |
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Row |
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Row |
Memory Array |
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11 |
Address |
11 |
Decoder 2048 |
2048x2048x16 |
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Buffers(11) |
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RAS |
No. 1 Clock |
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Generator |
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Block Diagram for HYB 3166160AT(L)
Semiconductor Group |
7 |
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
Absolute Maximum Ratings |
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Operating temperature range.............................................................................................. |
0 to 70 °C |
Storage temperature range......................................................................................... |
– 55 to 150 ° C |
Input/output voltage.................................................................................. |
-0.5 to min (Vcc+0.5,4.6) V |
Power supply voltage.................................................................................................... |
-0.5V to 4.6 V |
Power dissipation...................................................................................................................... |
1.3 W |
Data out current (short circuit).................................................................................................. |
50 mA |
Note |
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Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter |
Symbol |
Limit Values |
Unit |
Note |
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min. |
max. |
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Input high voltage |
VIH |
2.0 |
Vcc+0.3 |
V |
1) |
Input low voltage |
VIL |
– 0.3 |
0.8 |
V |
1) |
Output high voltage (LVTTL) |
VOH |
2.4 |
– |
V |
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Output „H“ level voltage (Iout = -2mA) |
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Output low voltage (LVTTL) |
VOL |
– |
0.4 |
V |
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Output „L“level voltage (Iout = +2mA) |
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Output high voltage (LVCMOS) |
VOH |
Vcc-0.2 |
- |
V |
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Output „H“ level voltage (Iout = -100uA) |
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Ouput low voltage (LVCMOS) |
VOL |
- |
0.2 |
V |
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Output „L“ level voltage (Iout = +100uA) |
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Input leakage current,any input |
II(L) |
– 2 |
2 |
μA |
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(0 V < Vin < Vcc , all other pins = 0 V |
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Output leakage current |
IO(L) |
– 2 |
2 |
μA |
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(DO is disabled, 0 V < Vout < Vcc ) |
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Semiconductor Group |
8 |