Siemens HYB3116405BJ-50, HYB3116405BT-50, HYB3116405BT-60, HYB3116405BTL-50, HYB3116405BTL-60 Datasheet

4M × 4-Bit Dynamic RAM	HYB 5116405BJ-50/-60
2k & 4k Refresh	HYB 5117405BJ-50/-60
(Hyper Page Mode - EDO)	HYB 3116405BJ/BT(L)-50/-60
	HYB 3117405BJ/BT-50/-60
Advanced Information

•4 194 304 words by 4-bit organization

•0 to 70 °C operating temperature

•Hyper Page Mode - EDO - operation

•Performance:

											-50			-60
	tRAC			access time							50			60			ns
			RAS
	tCAC			access time							13			15			ns
			CAS
	tAA		Access time from address								25			30			ns
	tRC		Read/Write cycle time								84			104			ns
	tHPC		Hyper page mode (EDO) cycle time								20			25			ns
• Power dissipation, refresh & addressing:
					HYB 5116405			HYB 3116405					HYB 5117405							HYB 3117405
					-50		-60	-50		-60			-50				-60			-50		-60
	Power supply				5 V ±		10%	3.3 V ± 0.3 V						5 V ± 10%						3.3 V ± 0.3 V
	Addressing				12/10			12/10					11/11							11/11
	Refresh					4096 cylces / 64 ms								2048 cycles / 32 ms
	L-version				4096 cycles / 128 ms														–
	Active				275		220	180		144			440				385			288		252	mW
	TTL Standby					11		7.2					11							7.2			mW
	CMOS Standby					5.5		3.6					5.5							3.6			mW
	CMOS Standby					–		0.72						–						–			mW
	(L-version)

•Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, test mode and Self Refresh (on L-versions only)

•All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible

• Plastic Package:	P-SOJ-26/24-1	300 mil
	P-TSOPII-26/24-1 300 mil

Semiconductor Group

1

1998-10-01

HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M × 4 EDO-DRAM

The HYB 5(3)116(7)405 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized as 4 194 304 words by 4-bits. The HYB 5(3)116(7)405BJ/BT(L) utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)405 to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB 3116(7)405BTL have a very low power “sleep mode” supported by Self Refresh.

Ordering Information

Type	Ordering Code	Package	Descriptions
2k-Refresh Versions:
HYB 5117405BJ-50	Q67100-Q1101	P-SOJ-26/24-1 300 mil	5 V 50 ns EDO-DRAM
HYB 5117405BJ-60	Q67100-Q1102	P-SOJ-26/24-1 300 mil	5 V 60 ns EDO-DRAM
HYB 3117405BJ-50	on request	P-SOJ-26/24-1 300 mil	3.3	V 50 ns EDO-DRAM
HYB 3117405BJ-60	on request	P-SOJ-26/24-1 300 mil	3.3	V 60 ns EDO-DRAM
HYB 3117405BT-50	on request	P-TSOPII-26/24-1 300 mil	3.3	V 50 ns EDO-DRAM
HYB 3117405BT-60	on request	P-TSOPII-26/24-1 300 mil	3.3	V 60 ns EDO-DRAM
4k-Refresh Versions:
HYB 5116405BJ-50	Q67100-Q1098	P-SOJ-26/24-1 300 mil	5 V 50 ns EDO-DRAM
HYB 5116405BJ-60	Q67100-Q1099	P-SOJ-26/24-1 300 mil	5 V 60 ns EDO-DRAM
HYB 3116405BJ-50	on request	P-SOJ-26/24-1 300 mil	3.3	V 50 ns EDO-DRAM
HYB 3116405BJ-60	on request	P-SOJ-26/24-1 300 mil	3.3	V 60 ns EDO-DRAM
HYB 3116405BT-50	on request	P-TSOPII-26/24-1 300 mil	3.3	V 50 ns EDO-DRAM
HYB 3116405BT-60	on request	P-TSOPII-26/24-1 300 mil	3.3	V 60 ns EDO-DRAM
HYB 3116405BTL-50	on request	P-TSOPII-26/24-1 300 mil	3.3	V 50 ns LP-EDO-DRAM
HYB 3116405BTL-60	on request	P-TSOPII-26/24-1 300 mil	3.3	V 60 ns LP-EDO-DRAM

Semiconductor Group

2

1998-10-01

								HYB 5116(7)405BJ-50/-60
								HYB 3116(7)405BJ/BT(L)-50/-60
									4M × 4 EDO-DRAM
Pin Names
		HYB 5(3)16405			HYB 5(3)17405
		4k-Refresh			2k-Refresh
Row Address Inputs		A0 - A11			A0 - A10
Column Address Inputs		A0 - A9			A0 - A10
Row Address Strobe
			RAS
Column Address Strobe
			CAS
Output Enable
				OE
Data Input/Output		I/O1 - I/O4
Read/Write Input
				WE
Power Supply			VCC
Ground (0 V)				VSS
Not Connected		–			N.C.

P-SOJ-26/24-1 300 mil

P-TSOPII-26/24-1 300 mil

	VCC								VSS
					1		26
	I/O1				2		25		I/O4
	I/O2				3		24		I/O3
					4		23
		WE								CAS
					5		22
	RAS										OE
A11 / N.C.					6		21		A9
	A10				8		19		A8
		A0			9		18		A7
		A1			10		17		A6
		A2			11		16		A5
		A3			12		15			A4
	VCC				13		14		VSS
							SPP03454

Pin Configuration

(top view)

Semiconductor Group

3

1998-10-01

							HYB 5116(7)405BJ-50/-60
					HYB 3116(7)405BJ/BT(L)-50/-60
							4M × 4 EDO-DRAM
				I/O1	I/O2	I/O3	I/O4
				Data IN			Data OUT	OE
				Buffer			Buffer
WE		&
CAS							4
					4
		No.2 Clock
		Generator
	10	Column		10
A0		Address					Column
		Buffers (10)
							Decoder
A1
A2
A3		Refresh
A4		Controller					Sense Amplifier		4
A5							I/O Gating
A6
A7		Refresh					1024
A8		Counter (12)					x 4
A9		12
A10
A11	12	Row	12	Row	4096		Memory Array
		Address		Decoder			4096 x 1024 x 4
		Buffers (12)
RAS		No.1 Clock
		Generator							VCC
							Voltage Down
							Generator		VCC
									(internal)
							SPB03455

Block Diagram for HYB 5(3)116405 (4k-refresh)

Semiconductor Group

4

1998-10-01

					HYB 5116(7)405BJ-50/-60
				HYB 3116(7)405BJ/BT(L)-50/-60
						4M × 4 EDO-DRAM
				I/O1	I/O2 I/O3	I/O4
				Data In		Data Out		OE
				Buffer		Buffer
WE		&		4			4
CAS
		No.2 Clock
		Generator
	11	Column
		Address			11
A0		Buffers (11)				Column
						Decoder
A1
A2		Refresh
A3
		Controller				Sense Amplifier			4
A4
						I/O Gating
A5
A6		Refresh				2048
A7		Counter (11)
						. . .	x 4	. ..
A8		11
A9
					.
A10					.
	11	Row	11	Row	.	Memory Array
					2048
		Address
				Decoder		2048 x 2048 x 4
		Buffers (11)			.
					.
					.
RAS		No.1 Clock
		Generator
					Voltage Down		V CC
					Generator		V CC (internal)
									SPB02823

Block Diagram for HYB 5(3)117405 (2k-refresh)

Semiconductor Group

5

1998-10-01

		HYB 5116(7)405BJ-50/-60
		HYB 3116(7)405BJ/BT(L)-50/-60
		4M × 4 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ...........................................................................................		0 to 70 ˚C
Storage temperature range........................................................................................		– 55 to 150 ˚C
Input/output voltage (5 V versions) ...................................................		– 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions) ................................................		– 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) .......................................................................		– 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) ....................................................................		– 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................		1.0 W
Power dissipation (3.3 V versions) .........................................................................................		0.5 W
Data out current (short circuit) ...............................................................................................		50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns

Parameter	Symbol	Limit Values		Unit	Test
					Condition
		min.	max.
5 V Versions
Power supply voltage	VCC	4.5	5.5	V
Input high voltage	VIH	2.4	VCC + 0.5	V	1
Input low voltage	VIL	– 0.5	0.8	V	1
Output high voltage (IOUT = – 5 mA)	VOH	2.4	–	V	1
Output low voltage (IOUT = 4.2 mA)	VOL	–	0.4	V	1
3.3 V Versions
Power supply voltage	VCC	3.0	3.6	V
Input high voltage	VIH	2.0	VCC + 0.5	V	1
Input low voltage	VIL	– 0.5	0.8	V	1
TTL Output high voltage (IOUT = – 2 mA)	VOH	2.4	–	V	1
TTL Output low voltage (IOUT = 2 mA)	VOL	–	0.4	V	1
CMOS Output high voltage (IOUT = – 100 A)	VOH	VCC – 0.2	–	V
CMOS Output low voltage (IOUT = 100 A)	VOL	–	0.2	V

Semiconductor Group

6

1998-10-01

HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M × 4 EDO-DRAM

DC Characteristics (cont’d)

TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

2k

4k

Common Parameters

Input leakage current

II(L)

– 10

10

A

1

(0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V)

Output leakage current

IO(L)

– 10

10

A

1

(DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V)

Average VCC supply current

-50 version

ICC1

–

80

50

mA

2, 3, 4

2, 3, 4

-60 version

–

70

40

mA

address cycling: tRC = tRC MIN.)

(RAS,

CAS,

Standby VCC supply current

ICC2

–

2

mA

–

(RAS

=

CAS

= VIH)

Average VCC supply current, during

RAS

-only

ICC3

2, 4

refresh cycles

-50 version

–

80

50

mA

2, 4

-60 version

–

70

40

mA

cycling,

= VIH, tRC = tRC MIN.)

(RAS

CAS

Average VCC supply current,during hyper page

ICC4

2, 3, 4

mode (EDO)

-50 version

–

35

mA

2, 3, 4

-60 version

–

30

mA

= VIL,

address cycling:

(RAS

CAS,

tPC = tPC MIN.)

Standby VCC supply current

ICC5

–

1

mA

1

=

= VCC – 0.2 V)

200

A

L-version

(RAS

CAS

Average VCC supply current, during

CAS

-

ICC6

2, 4

before-RAS refresh mode

-50 version

–

80

50

mA

2, 4

-60 version

–

70

40

mA

cycling: tRC = tRC MIN.)

(RAS,

CAS

Average Self Refresh current

ICC7

–

250

A

L-

(CBR cycle with tRAS > tRASS MIN.,

CAS

held

version

low,

= VCC – 0.2 V, Address and

only

WE

Din = VCC – 0.2 V or 0.2 V)

Semiconductor Group

7

1998-10-01

HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M × 4 EDO-DRAM

Capacitance

TA = 0 to 70 °C, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11)

CI1

–

5

pF

Input capacitance

CI2

–

7

pF

(RAS,

CAS,

WE,

OE)

I/O capacitance (I/O1 to I/O4)

CIO

–

7

pF

AC Characteristics 5, 6

TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

Common Parameters

Random read or write cycle time

tRC

84

–

104

–

ns

precharge time

tRP

30

–

40

–

ns

RAS

pulse width

tRAS

50

10k

60

10k

ns

RAS

pulse width

tCAS

8

10k

10

10k

ns

CAS

Row address setup time

tASR

0

–

0

–

ns

Row address hold time

tRAH

8

–

10

–

ns

Column address setup time

tASC

0

–

0

–

ns

Column address hold time

tCAH

8

–

10

–

ns

to

delay time

tRCD

12

37

14

45

ns

RAS

CAS

to column address delay

tRAD

10

25

12

30

ns

RAS

hold time

tRSH

13

–

15

–

ns

RAS

hold time

tCSH

40

–

50

–

ns

CAS

to

precharge time

tCRP

5

–

5

–

ns

CAS

RAS

Transition time (rise and fall)

tT

1

50

1

50

ns

7

Refresh period for 2k-refresh version

tREF

–

32

–

32

ms

Refresh period for 4k-refresh version

tREF

–

64

–

64

ms

Refresh period for Low Power Version

tREF

–

128

–

128

ms

Read Cycle

Access time from RAS

tRAC

–

50

–

60

ns

8, 9

tCAC

8, 9

Access time from CAS

–

13

–

15

ns

Semiconductor Group

8

1998-10-01

HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M × 4 EDO-DRAM

AC Characteristics (cont’d) 5, 6

TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

Access time from column address

tAA

–

25

–

30

ns

8, 10

access time

tOEA

–

13

–

15

ns

OE

Column address to

lead time

tRAL

25

–

30

–

ns

RAS

Read command setup time

tRCS

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

ns

11

tRRH

11

Read command hold time referenced to RAS

0

–

0

–

ns

tCLZ

8

CAS to output in low-Z

0

–

0

–

ns

Output buffer turn-off delay

tOFF

0

13

0

15

ns

12

tOEZ

12

Output turn-off delay from OE

0

13

0

15

ns

tDZC

13

Data to CAS low delay

0

–

0

–

ns

tDZO

13

Data to OE low delay

0

–

0

–

ns

tCDD

14

CAS high to data delay

10

–

13

–

ns

tODD

14

OE high to data delay

10

–

13

–

ns

Write Cycle

Write command hold time

tWCH

8

–

10

–

ns

Write command pulse width

tWP

8

–

10

–

ns

Write command setup time

tWCS

0

–

0

–

ns

15

Write command to

lead time

tRWL

8

–

10

–

ns

RAS

Write command to

lead time

tCWL

8

–

10

–

ns

CAS

Data setup time

tDS

0

–

0

–

ns

16

Data hold time

tDH

8

–

10

–

ns

16

Read-Modify-Write Cycle

Read-write cycle time

tRWC

113

–

138

–

ns

tRWD

15

RAS to WE delay time

64

–

77

–

ns

tCWD

15

CAS to WE delay time

27

–

32

–

ns

tAWD

15

Column address to WE delay time

39

–

47

–

ns

command hold time

tOEH

10

–

13

–

ns

OE

Semiconductor Group

9

1998-10-01