Siemens HYB3118165BSJ-50, HYB3118165BSJ-60, HYB3118165BST-50, HYB3118165BST-60, HYB5118165BSJ-50 Datasheet

1M × 16-Bit Dynamic RAM	HYB 5118165BSJ/BST-50/-60
1k Refresh	HYB 3118165BSJ/BST-50/-60
(Hyper Page Mode-EDO)

Advanced Information

•1 048 576 words by 16-bit organization

•0 to 70 °C operating temperature

•Hyper Page Mode-EDO-operation

•Performance:

										-50		-60
	tRAC			access time						50		60			ns
			RAS
	tCAC			access time						13		15			ns
			CAS
	tAA		Access time from address							25		30			ns
	tRC		Read/Write cycle time							84		104			ns
	tHPC		Hyper page mode (EDO) cycle time							20		25			ns
• Power Dissipation, Refresh & Addressing:
						HYB5118165				HYB3118165
						-50		-60		-50				-60
	Power Supply					5 V ±		10 %		3.3 V			± 0.3 V
	Addressing					10/10					10/10
	Refresh						1024 cycles / 16 ms
	Active					715		632		468				414		mW
	TTL Standby						11				7.2					mW
	CMOS Standby						5.5				3.6					mW

•Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh and hidden refresh

•All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible

• Plastic Package: P-SOJ-42-1

400 mil

P-TSOPII-50/44-1 400 mil

Semiconductor Group

1

1998-10-01

HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM

The HYB 5(3)118165 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized as 1 048 576 words by 16-bits. The HYB 5(3)118165 utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)18165 to be packaged in a standard SOJ-42 and TSOPII-50/44 plastic package with 400 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.

Ordering Information

Type	Ordering Code	Package	Descriptions
HYB 5118165BSJ-50	Q67100-Q1107	P-SOJ-42-1 400 mil	5 V 50 ns EDO-DRAM
HYB 5118165BSJ-60	Q67100-Q1108	P-SOJ-42-1 400 mil	5 V 60 ns EDO-DRAM
HYB 3118165BSJ-50	on request	P-SOJ-42-1 400 mil	3.3 V 50 ns EDO-DRAM
HYB 3118165BSJ-60	on request	P-SOJ-42-1 400 mil	3.3 V 60 ns EDO-DRAM
HYB 5118165BST-50	on request	P-TSOPII-50/44-1 400 mil	5 V 50 ns EDO-DRAM
HYB 5118165BST-60	on request	P-TSOPII-50/44-1 400 mil	5 V 60 ns EDO-DRAM
HYB 3118165BST-50	on request	P-TSOPII-50/44-1 400 mil	3.3 V 50 ns EDO-DRAM
HYB 3118165BST-60	on request	P-TSOPII-50/44-1 400 mil	3.3 V 60 ns EDO-DRAM

Semiconductor Group

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1998-10-01

HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM

Pin Names and Configuration

		HYB 5(3)118165
Row Address Inputs		A0 - A9
Column Address Inputs	A0 - A9
Row Address Strobe
		RAS
Upper Column Address Strobe	UCAS
Lower Column Address Strobe	LCAS
Output Enable
		OE
Data Input/Output		I/O1 - I/O16
Read/Write Input
		WE
Power Supply		VCC
Ground (0 V)		VSS
Not Connected		N.C.

P-SOJ-42-1 (400 mil)

V CC					V SS
		1	42
I/O1		2	41		I/O16
I/O2		3	40		I/O15
I/O3		4	39		I/O14
I/O4		5	38		I/O13
V CC		6	37		V SS
I/O5		7	36		I/O12
I/O6		8	35		I/O11
I/O7		9	34		I/O10
I/O8		10	33		I/O9
N.C.		11	32		N.C.
N.C.		12	31		LCAS
WE		13	30		UCAS
RAS		14	29		OE
N.C.		15	28		A9
N.C.		16	27		A8
A0		17	26		A7
A1		18	25		A6
A2		19	24		A5
A3		20	23		A4
V CC		21	22		V SS
				SPP02812

P-TSOPII-50/44-1 (400 mil)

VCC		1	50		VSS
I/O1		2	49		I/O16
I/O2		3	48		I/O15
I/O3		4	47		I/O14
I/O4		5	46		I/O13
VCC		6	45		VSS
I/O5		7	44		I/O12
I/O6		8	43		I/O11
I/O7		9	42		I/O10
I/O8		10	41		I/O9
N.C.		11	40		N.C.

	N.C.					15	36				N.C.
	N.C.					16	35
												LCAS
							34
		WE				17					UCAS
						18	33
	RAS										OE
A11 / N.C.						19	32				A9
A10 / N.C.						20	31				A8
		A0				21	30				A7
		A1				22	29				A6
		A2				23	28				A5
		A3				24	27				A4
	VCC					25	26			VSS
							SPP03457

Semiconductor Group

3

1998-10-01

					HYB 5118165BSJ/BST-50/-60
					HYB 3118165BSJ/BST-50/-60
						1M × 16 EDO-DRAM
			I/O1		I/O2 . . .	I/O16
					. . .
			Data In			Data Out		OE
			Buffer			Buffer
WE	&			16			16
UCAS
LCAS
	No.2 Clock
	Generator
10	Column
	Address
	Buffers (10)				10	Column
A0						Decoder
A1
A2	Refresh
A3	Controller					Sense Amplifier			16
A4						I/O Gating
A5	Refresh
A6						1024
	Counter (10)
A7						. . .	x 16	. ..
A8	10
A9					.
10	Row	10			.
			Row		.	Memory Array
	Address				1024
			Decoder			1024 x 1024		x 16
	Buffers (10)				.
					.
					.
RAS	No.1 Clock
	Generator
					Voltage Down		V CC
					Generator		V CC (internal)
									SPB02826

Block Diagram for HYB 5118165BSJ

Semiconductor Group

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1998-10-01

	HYB 5118165BSJ/BST-50/-60
	HYB 3118165BSJ/BST-50/-60
	1M × 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ...........................................................................................	0 to 70 °C
Storage temperature range........................................................................................	– 55 to 150 °C
Input/output voltage (5 V versions) ....................................................	– 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions) .................................................	– 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) .......................................................................	– 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) ....................................................................	– 1.0 V to 4.6 V
Power dissipation (5 V versions) .............................................................................................	1.0 W
Power dissipation (3.3 V versions) ..........................................................................................	0.5 W
Data out current (short circuit) ................................................................................................	50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns

Parameter	Symbol	Limit Values		Unit	Test
					Condition
		min.	max.
5 V Versions
Power supply voltage	VCC	4.5	5.5	V
Input high voltage	VIH	2.4	VCC + 0.5	V	1
Input low voltage	VIL	– 0.5	0.8	V	1
Output high voltage (IOUT = – 5 mA)	VOH	2.4	–	V	1
Output low voltage (IOUT = 4.2 mA)	VOL	–	0.4	V	1
3.3 V Versions
Power supply voltage	VCC	3.0	3.6	V
Input high voltage	VIH	2.0	VCC + 0.5	V	1
Input low voltage	VIL	– 0.5	0.8	V	1
TTL Output high voltage (IOUT = – 2 mA)	VOH	2.4	–	V	1
TTL Output low voltage (IOUT = 2 mA)	VOL	–	0.4	V	1
CMOS Output high voltage (IOUT = – 100 A)	VOH	VCC – 0.2	–	V
CMOS Output low voltage (IOUT = 100 A)	VOL	–	0.2	V

Semiconductor Group

5

1998-10-01

HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM

DC Characteristics (cont’d)

TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Common Parameters

Input leakage current

II(L)

– 10

10

A

1

(0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V)

Output leakage current

IO(L)

– 10

10

A

1

(DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V)

Average VCC supply current

-50 ns version

ICC1

–

130

mA

2, 3, 4

2, 3, 4

-60 ns version

–

115

mA

address cycling: tRC = tRC MIN.)

(RAS,

CAS,

Standby VCC supply current

=

= VIH)

ICC2

–

2

mA

–

(RAS

CAS

Average VCC supply current, during

-only refresh

ICC3

RAS

2, 4

cycles

-50 ns version

–

130

mA

2, 4

-60 ns version

–

115

mA

cycling,

= VIH, tRC = tRC MIN.)

(RAS

CAS

Average VCC supply current, during hyper page mode

ICC4

2, 3, 4

(EDO)

-50 ns version

–

50

mA

2, 3, 4

-60 ns version

–

40

mA

= VIL,

address cycling: tPC = tPC MIN.)

(RAS

CAS,

Standby VCC supply current

ICC5

–

1

mA

1

(RAS

=

CAS

= VCC – 0.2 V)

Average VCC supply current, during

-before-

ICC6

CAS

RAS

2, 4

refresh mode

-50 ns version

–

130

mA

2, 4

-60 ns version

–

115

mA

cycling: tRC = tRC MIN.)

(RAS,

CAS

Semiconductor Group

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1998-10-01

HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM

Capacitance

TA = 0 to 70 °C, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11)

CI1

–

5

pF

Input capacitance

CI2

–

7

pF

(RAS,

UCAS,

LCAS,

WE,

OE)

I/O capacitance (I/O1 - I/O16)

CIO

–

7

pF

AC Characteristics 5, 6

TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

Common Parameters

Random read or write cycle time

tRC

84

–

104

–

ns

precharge time

tRP

30

–

40

–

ns

RAS

pulse width

tRAS

50

10k

60

10k

ns

RAS

pulse width

tCAS

8

10k

10

10k

ns

CAS

Row address setup time

tASR

0

–

0

–

ns

Row address hold time

tRAH

8

–

10

–

ns

Column address setup time

tASC

0

–

0

–

ns

Column address hold time

tCAH

8

–

10

–

ns

to

delay time

tRCD

12

37

14

45

ns

RAS

CAS

to column address delay

tRAD

10

25

12

30

ns

RAS

hold time

tRSH

13

–

15

–

ns

RAS

hold time

tCSH

40

–

50

–

ns

CAS

to

precharge time

tCRP

5

–

5

–

ns

CAS

RAS

Transition time (rise and fall)

tT

1

50

1

50

ns

7

Refresh period for 1k-refresh version

tREF

–

16

–

16

ms

Read Cycle

Access time from RAS

tRAC

–

50

–

60

ns

8, 9

tCAC

8, 9

Access time from CAS

–

13

–

15

ns

Access time from column address

tAA

–

25

–

30

ns

8, 10

access time

tOEA

–

13

–

15

ns

OE

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HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM

AC Characteristics (cont’d) 5, 6

TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

Column address to

lead time

tRAL

25

–

30

–

ns

RAS

Read command setup time

tRCS

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

ns

11

tRRH

11

Read command hold time referenced to RAS

0

–

0

–

ns

tCLZ

8

CAS to output in low-Z

0

–

0

–

ns

Output buffer turn-off delay

tOFF

0

13

0

15

ns

12

tOEZ

12

Output turn-off delay from OE

0

13

0

15

ns

tDZC

13

Data to CAS low delay

0

–

0

–

ns

tDZO

13

Data to OE low delay

0

–

0

–

ns

tCDD

14

CAS high to data delay

10

–

13

–

ns

tODD

14

OE high to data delay

10

–

13

–

ns

Write Cycle

Write command hold time

tWCH

8

–

10

–

ns

Write command pulse width

tWP

8

–

10

–

ns

Write command setup time

tWCS

0

–

0

–

ns

15

Write command to

lead time

tRWL

8

–

10

–

ns

RAS

Write command to

lead time

tCWL

8

–

10

–

ns

CAS

Data setup time

tDS

0

–

0

–

ns

16

Data hold time

tDH

8

–

10

–

ns

16

Read-Modify-Write Cycle

Read-write cycle time

tRWC

113

–

138

–

ns

tRWD

15

RAS to WE delay time

64

–

77

–

ns

tCWD

15

CAS to WE delay time

27

–

32

–

ns

tAWD

15

Column address to WE delay time

39

–

47

–

ns

command hold time

tOEH

10

–

13

–

ns

OE

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle time

tHPC

20

–

25

–

ns

precharge time

tCP

8

–

10

–

ns

CAS

Semiconductor Group

8

1998-10-01