Siemens HYB3116405BJ-70, HYB3116405BT-70, HYB3116405BTL-70, HYB3117405BJ-70, HYB3117405BT-70 Datasheet

3.3V 4M x 4-Bit EDO-Dynamic RAM	HYB3116405BJ/BT(L)	-50/-60/-70
	HYB3117405BJ/BT(L)	-50/-60/-70

Advanced Information

•4 194 304 words by 4-bit organization

•0 to 70 °C operating temperature

•Performance

						-50	-60	-70
tRAC					access time	50	60	70	ns
			RAS
tCAC					access time	13	15	20	ns
		CAS
tAA		Access time from address				25	30	35	ns
tRC		Read/Write cycle time				84	104	124	ns
tHPC		Hyper page mode (EDO)				20	25	30	ns
		cycle time

•Single + 3.3 V (± 0.3V ) supply

•Low power dissipation

max. 396 active mW (HYB3117405BJ/BT-50) max. 363 active mW (HYB3117405BJ/BT-60) max. 330 active mW (HYB3117405BJ/BT-70) max. 360 active mW (HYB3116405BJ/BT-50) max. 324 active mW (HYB3116405BJ/BT-60) max. 288 active mW (HYB3116405BJ/BT-70)

7.2 mW standby (LV-TTL)

3.6 mW standby (LV-CMOS)

720 W standby for L-version

•Output unlatched at cycle end allows two-dimensional chip selection

•Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, Self Refresh and test mode

•Hyper page mode (EDO) capability

•All inputs, outputs and clocks fully TTL-compatible

•2048 refresh cycles / 32 ms for HYB3117405

4096 refresh cycles / 64 ms for HYB3116405

• Plastic Package:	P-SOJ-26/24-1 (300 mil)
	P-TSOPII-26/24-1 (300mil)

Semiconductor Group

1

3.96

HYB 3116(7)405BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM

The HYB 3116(7)405BJ/BT(L) is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 3116(7)405BJ/BT(L) utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(7)405BJ/BT(L) to be packaged in a standard SOJ 26/24 300 mil or TSOPII-26/24 300 mil wide plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families.The HYB3116405BTL parts have a very low power „sleep mode“ supported by Self Refresh.

Ordering Information

Type	Ordering Code	Package	Descriptions
HYB 3117405BJ-50	Q67100-Q1119	P-SOJ-26/24-1 300 mil	DRAM (access time 50 ns)
HYB 3117405BJ-60	Q67100-Q1120	P-SOJ-26/24-1 300 mil	DRAM (access time 60 ns)
HYB 3117405BJ-70		P-SOJ-26/24-1 300 mil	DRAM (access time 70 ns)
HYB 3117405BT-50	Q67100-Q1135	P-TSOPII-26/24-1 300 mil	DRAM (access time 50 ns)
HYB 3117405BT-60	Q67100-Q1136	P-TSOPII-26/24-1 300 mil	DRAM (access time 60 ns)
HYB 3117405BT-70	Q67100-Q1184	P-TSOPII-26/24-1 300 mil	DRAM (access time 70 ns)
HYB 3116405BJ-50	Q67100-Q1127	P-SOJ-26/24-1 300 mil	DRAM (access time 50 ns)
HYB 3116405BJ-60	Q67100-Q1128	P-SOJ-26/24-1 300 mil	DRAM (access time 60 ns)
HYB 3116405BJ-70		P-SOJ-26/24-1 300 mil	DRAM (access time 70 ns)
HYB 3116405BT-50	Q67100-Q1143	P-TSOPII-26/24-1 300 mil	DRAM (access time 50 ns)
HYB 3116405BT-60	Q67100-Q1144	P-TSOPII-26/24-1 300 mil	DRAM (access time 60 ns)
HYB 3116405BT-70	Q67100-Q1186	P-TSOPII-26/24-1 300 mil	DRAM (access time 70 ns)
HYB 3116405BTL-50	on request	P-TSOPII-26/24-1 300 mil	LP-DRAM (access time 50 ns)
HYB 3116405BTL-60	on request	P-TSOPII-26/24-1 300 mil	LP-DRAM (access time 60 ns)
HYB 3116405BTL-70	on request	P-TSOPII-26/24-1 300 mil	LP-DRAM (access time 70 ns)

Semiconductor Group

2

HYB 3116(7)405BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM

Vcc

1

26

Vss

Vcc

1

26

Vss

I/O1

2

25

I/O4

I/O1

2

25

I/O4

I/O2

3

24

I/O3

I/O2

3

24

I/O3

WE

4

23

CAS

WE

4

23

CAS

5

22

OE

5

22

OE

RAS

RAS

N.C.

6

21

A9

A11

6

21

A9

A10

8

19

A8

A10

8

19

A8

A0

9

18

A7

A0

9

18

A7

A1

10

17

A6

A1

10

17

A6

A2

11

16

A5

A2

11

16

A5

A3

12

15

A4

A3

12

15

A4

VCC

13

14

Vss

VCC

13

14

Vss

HYB3117405BJ/BT

HYB3116405BJ/BT

P-SOJ-26/24-1 (300mil)

P-TSOPII-26/24-1 (300mil)

Pin Configuration

Pin Names

A0 to A10

Row & Column Address Inputs for HYB3117405

A0 to A11

Row Address Inputs for HYB3116405

A0 to A9

Column Address Inputs for HYB3116405

Row Address Strobe

RAS

Output Enable

OE

I/O1 -I/O4

Data Input/Output

Column Address Strobe

CAS

Read/Write Input

WE

VCC

Power Supply (+ 3.3 V)

VSS

Ground (0 V)

N.C.

not connected

Semiconductor Group

3

			HYB 3116(7)405BJ/BT(L) -50/-60/-70
				3.3V 4Mx4-DRAM
			I/O1 I/O2 I/O3 I/O4
WE
CAS .	&		Data in	Data out
					OE
			Buffer	Buffer
	No. 2 Clock		4	4
	Generator
11	Column
	Address		11	Column
A0	Buffer(11)			Decoder
A1
A2
A3	Refresh			Sense Amplifier
A4	Controller				4
				I/O Gating
A5
A6
A7	Refresh			2048
A8	Counter (11)
				x4
A9
	11
A10
	Row		Row	Memory Array
11	Address	11	Decoder 2048	2048x2048x4
	Buffers(11)
RAS	No. 1 Clock
	Generator

Block Diagram for HYB3117405

Semiconductor Group

4

			HYB 3116(7)405BJ/BT(L) -50/-60/-70
				3.3V 4Mx4-DRAM
			I/O1 I/O2 I/O3 I/O4
WE
CAS .	&		Data in	Data out
					OE
			Buffer	Buffer
	No. 2 Clock		4	4
	Generator
10	Column
	Address		10	Column
A0	Buffer(10)			Decoder
A1
A2
A3	Refresh			Sense Amplifier
A4	Controller				4
				I/O Gating
A5
A6
A7	Refresh			1024
A8	Counter (12)
				x4
A9
	12
A10
A11	Row		Row	Memory Array
12	Address	12	Decoder 4096	4096x1024x4
	Buffers(12)
RAS	No. 1 Clock
	Generator

Block Diagram for HYB3116405

Semiconductor Group

5

TA = 0 to 70 °C,

HYB 3116(7)405BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM

Absolute Maximum Ratings
Operating temperature range ............................................................................................	0 to 70	°C
Storage temperature range.........................................................................................	– 55 to 150	°C
Input/output voltage ................................................................................	-0.5 to min(Vcc+0.5, 4.6)		V
Power supply voltage.................................................................................................	- 0.5 V to 4.6		V
Power dissipation....................................................................................................................	0.5		W
Data out current (short circuit) ................................................................................................	50 mA

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics (values in brackets for HYB3117405)

VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Input high voltage

VIH

2.0

Vcc+0.5

V

1)

Input low voltage

VIL

– 0.5

0.8

V

1)

TTL Output high voltage (IOUT = – 2 mA)

VOH

2.4

–

V

1)

TTL Output low voltage (IOUT = 2 mA)

VOL

–

0.4

V

1)

CMOS Output high voltage (IOUT = –100 uA)

VOH

VCC-0.2

–

V

CMOS Output low voltage (IOUT = 100 uA)

VOL

–

0.2

V

Input leakage current

II(L)

– 10

10

A

1)

(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)

Output leakage current

IO(L)

– 10

10

A

1)

(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)

Average VCC supply current:

ICC1

2) 3) 4)

-50 ns version

–

100(120)

mA

-60 ns version

–

90 (110)

mA

2) 3) 4)

-70 ns version

–

80 (100)

mA

2) 3) 4)

address cycling, tRC = tRC min.)

(RAS,

CAS,

Standby VCC supply current

=

= VIH)

ICC2

–

2

mA

–

(RAS

CAS

Semiconductor Group

6

TA = 0 to 70 °C,

HYB 3116(7)405BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM

DC Characteristics (values in brackets for HYB3117405)

VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Test

Condition

min.

max.

Average VCC supply current, during

-only

ICC3

RAS

2)

4)

refresh cycles:

-50 ns version

–

100(120)

mA

-60 ns version

–

90 (110)

mA

2)

4)

-70 ns version

–

80 (100)

mA

2)

4)

cycling:

= VIH, tRC = tRC min.)

(RAS

CAS

Average VCC supply current, during hyper page

ICC4

2)

3) 4)

mode EDO):

-50 ns version

–

70 (70)

mA

-60 ns version

–

55 (55)

mA

2)

3) 4)

-70 ns version

–

45 (45)

mA

2)

3) 4)

= VIL,

address cycling, tPC = tPC min.)

(RAS

CAS,

Standby VCC supply current

ICC5

–

1

mA

1)

=

= VCC – 0.2 V)

200

A

L-version

(RAS

CAS

Average VCC supply current, during

-

ICC6

CAS

2)

4)

before-RAS refresh mode:

-50 ns version

–

100(120)

mA

-60 ns version

–

90 (110)

mA

2)

4)

-70 ns version

–

80 (100)

mA

2)

4)

cycling, tRC = tRC min.)

(RAS,

CAS

Average Self Refresh Current

ICC7

_

1

mA

250

A

L-version

(CBR cylce with tRAS>TRASSmin.,

CAS

held low,

WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

Capacitance

TA = 0 to 70 °C, VCC = 3.3 V ± 0.3V, f = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A10, A11)

CI1

–

5

pF

Input capacitance

CI2

–

7

pF

(RAS,

CAS,

WE,

OE)

I/O capacitance (I/O1 - I/O4)

CIO

–

7

pF

Semiconductor Group

7

HYB 3116(7)405BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM

AC Characteristics 5)6)

16E

TA = 0 to 70 °C, VCC = 5 V ± 10 %, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max.

min.

max.

min.

max.

common parameters

Random read or write cycle time

tRC

84

–

104

–

124

–

ns

precharge time

tRP

30

–

40

–

50

–

ns

RAS

pulse width

tRAS

50

10k

60

10k

70

10k

ns

RAS

pulse width

tCAS

8

10k

10

10k

12

10k

ns

CAS

Row address setup time

tASR

0

–

0

–

0

–

ns

Row address hold time

tRAH

8

–

10

–

10

–

ns

Column address setup time

tASC

0

–

0

–

0

–

ns

Column address hold time

tCAH

8

–

10

–

12

–

ns

to

delay time

tRCD

12

37

14

45

14

53

ns

RAS

CAS

to column address delay

tRAD

10

25

12

30

12

35

ns

RAS

hold time

tRSH

13

15

–

17

–

ns

RAS

hold time

tCSH

40

50

–

60

–

ns

CAS

to

precharge time

tCRP

5

–

5

–

5

–

ns

CAS

RAS

Transition time (rise and fall)

tT

1

50

1

50

1

50

ns

7

Refresh period for HYB5116405

tREF

–

64

–

64

–

64

ms

Refresh period for HYB5117405

tREF

–

32

–

32

–

32

ms

Refresh period for L-version

tREF

–

256

–

256

–

256

ms

Read Cycle

Access time from

RAS

tRAC

–

50

–

60

–

70

ns

8, 9

Access time from

tCAC

–

13

–

15

–

17

ns

8, 9

CAS

Access time from column address

tAA

–

25

–

30

–

35

ns

8,10

access time

tOEA

–

13

–

15

–

17

ns

OE

Column address to

lead time

tRAL

25

–

30

–

35

–

ns

RAS

Read command setup time

tRCS

0

–

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

0

–

ns

11

Read command hold time

tRRH

0

–

0

–

0

–

ns

11

referenced to

RAS

to output in low-Z

tCLZ

0

–

0

–

0

–

ns

8

CAS

Semiconductor Group

8