MOTOROLA MC74ACT109N, MC74ACT109ML1, MC74ACT109ML2, MC74ACT109MR2, MC74ACT109DR2 Datasheet
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Dual JK Positive Edge Triggered Flip Flop
The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
•Outputs Source/Sink 24 mA
•′ACT109 Has TTL Compatible Inputs
VCC |
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CD2 |
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J2 |
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K2 |
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CP2 |
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SD2 |
Q2 |
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Q2 |
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9 |
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CD |
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J |
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K |
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CP |
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SD |
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Q |
Q |
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PIN NAMES |
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CD1 |
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K1 |
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CP1 |
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SD1 |
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Q1 |
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Q1 |
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J1, J2, K1, K2 |
Data Inputs |
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J1 |
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CP1, |
CP2 |
Clock Pulse Inputs |
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C |
D1, |
C |
D2 |
Direct Clear Inputs |
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2 |
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3 |
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4 |
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5 |
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6 |
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7 |
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8 |
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SD1, SD2 |
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Direct Set Inputs |
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CD1 |
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J1 |
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K1 |
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CP1 |
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SD1 |
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Q1 |
Q1 |
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GND |
Q1, Q2, Q1, Q2 |
Outputs |
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TRUTH TABLE
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Inputs |
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Outputs |
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SD |
CD |
CP |
J |
K |
Q |
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Q |
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L |
H |
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X |
X |
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H |
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L |
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H |
L |
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X |
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L |
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H |
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L |
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X |
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H |
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H |
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H |
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L |
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H |
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H |
H |
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H |
L |
Toggle |
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H |
H |
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L |
H |
Q0 |
Q0- |
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H |
H |
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H |
H |
H |
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L |
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H |
H |
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L |
X |
X |
Q0 |
Q0- |
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H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Clock Transition
X = Immaterial
Q0(Q0) = Previous Q0(Q0) before
LOW-to-HIGH Transition of Clock
MC74AC109
MC74ACT109
DUAL JK POSITIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
Q Q
SD CD 
J CP K
Q |
Q |
SD |
CD |
J CP |
K |
FACT DATA
5-1
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MC74AC109 MC74ACT109 |
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LOGIC DIAGRAM (one half shown) |
SD |
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K |
Q |
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CP |
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J |
Q |
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CD |
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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
±0.5 to +7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
±0.5 to VCC +0.5 |
V |
Iin |
DC Input Current, per Pin |
±20 |
mA |
Iout |
DC Output Sink/Source Current, per Pin |
±50 |
mA |
ICC |
DC VCC or GND Current per Output Pin |
±50 |
mA |
Tstg |
Storage Temperature |
±65 to +150 |
°C |
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
′AC |
2.0 |
5.0 |
6.0 |
V |
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′ACT |
4.5 |
5.0 |
5.5 |
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Vin, Vout |
DC Input Voltage, Output Voltage (Ref. to GND) |
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0 |
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VCC |
V |
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Input Rise and Fall Time (Note 1) |
VCC @ 3.0 V |
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150 |
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tr, tf |
VCC @ 4.5 V |
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40 |
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ns/V |
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′AC Devices except Schmitt Inputs |
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VCC @ 5.5 V |
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25 |
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tr, tf |
Input Rise and Fall Time (Note 2) |
VCC @ 4.5 V |
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10 |
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ns/V |
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′ACT Devices except Schmitt Inputs |
VCC @ 5.5 V |
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8.0 |
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TJ |
Junction Temperature (PDIP) |
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140 |
°C |
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TA |
Operating Ambient Temperature Range |
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±40 |
25 |
85 |
°C |
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IOH |
Output Current Ð High |
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±24 |
mA |
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IOL |
Output Current Ð Low |
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24 |
mA |
1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA
5-2
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