February 1991
Revised February 2000
DM74ALS137
3 to 8 Line Decoder/Demultiplexer with Address Latches
General Description
The ALS137 is a three line to eight line decoder/demultiplexer with latches on the three address inputs. When the latch-enable input (GL) is LOW, the ALS137 acts as a decoder/demultiplexer. When GL goes from LOW-to-HIGH, the address present at the select inputs (A, B, and C) is stored in the latches. Further address changes are ignored as long as GL remains HIGH. The output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are HIGH unless G1 is HIGH and G2 is LOW. The ALS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.
Features
■Combines decoder and 3-bit address latch
■Incorporates 3 enable inputs to simplify cascading
■Low power dissipation: 28 mW typ
■Switching specifications guaranteed over full temperature and VCC range
■Advanced oxide-isolated, ion-implanted Schottky TTL process
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74ALS137M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74ALS137N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Function Table |
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Inputs |
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Outputs |
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Enable |
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Select |
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GL G1 G2 |
C |
B |
A |
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 |
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X X H |
X X X |
H H H H H H H H |
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X L X |
X X X |
H |
H H H H H H H |
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L H L |
L L L |
L H H H H H H H |
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L H L |
L L H |
H L H H H H H H |
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L H L |
L H L |
H H L H H H H H |
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L H L |
L H H |
H H H L H H H H |
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L H L |
H L L |
H H H H L H H H |
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L H L |
H L H |
H H H H H L H H |
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L H L |
H H L |
H H H H H H L H |
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L |
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H L |
H H H |
H H H H H H H L |
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H |
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H L |
X |
X |
X |
Output corresponding to stored |
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address, L; all others, H |
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L = LOW State |
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H = HIGH State |
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X = Don't Care |
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Latches Address with Decoder/Demultiplexer Line 8 to 3 DM74ALS137
© 2000 Fairchild Semiconductor Corporation |
DS006202 |
www.fairchildsemi.com |
DM74ALS137
Logic Diagram
www.fairchildsemi.com |
2 |
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