SGS Thomson Microelectronics M48Z35-70MH1, M48Z35, M48Z35Y-70PC1, M48Z35Y-70MH1, M48Z35Y Datasheet

M48Z35

M48Z35Y

256Kbit (32Kb x8) ZEROPOWER®SRAM

■INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and	SNAPHAT (SH)
BATTERY	Battery

■READ CYCLE TIME EQUALS WRITE CYCLE TIME

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

	■ WRITE PROTECT VOLTAGES	28
	(VPFD = Power-fail Deselect Voltage):	28	1
	– M48Z35: 4.50V ≤ VPFD ≤ 4.75V
		1	PCDIP28 (PC)
	– M48Z35Y: 4.20V ≤ VPFD ≤ 4.50V		Battery CAPHAT
	■ SELF-CONTAINED BATTERY in the CAPHAT	SOH28 (MH)
	DIP PACKAGE
	■ PACKAGING INCLUDES a 28-LEAD SOIC and
	SNAPHAT® TOP (to be Ordered Separately)	Figure 1. Logic Diagram

■SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL

■PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x8 SRAMs

DESCRIPTION

VCC

The M48Z35/35Y ZEROPOWER® RAM is a 32

15

8

Kbit x8 non-volatile

static RAM

that integrates

power-fail deselect circuitry and

battery control

A0-A14

DQ0-DQ7

logic on a single die. The monolithic chip is avail-

able in two special packages to provide a highly in-

tegrated battery backed-up memory solution.

W

M48Z35

M48Z35Y

E

Table 1. Signal Names

G

A0-A14

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

Chip Enable

E

VSS

Output Enable

AI01616D

G

Write Enable

W

VCC

Supply Voltage

VSS

Ground

August 1999

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M48Z35, M48Z35Y

Figure 2A. DIP Pin Connections

Figure 2B. SOIC Pin Connections

A14	1		28	VCC
									A14	1		28	VCC
A12	2		27	W					A12	2		27		W
A7	3		26	A13					A7	3		26	A13
A6	4		25	A8					A6	4		25	A8
A5	5		24	A9					A5	5		24	A9
A4	6		23	A11					A4	6		23	A11
A3	7		22						A3	7		22
		M48Z35		G							M48Z35Y				G
A2	8	M48Z35Y	21	A10					A2	8		21	A10
A1	9		20						A1	9		20
				E												E
A0	10		19	DQ7					A0	10		19	DQ7
DQ0	11		18	DQ6					DQ0	11		18	DQ6
DQ1	12		17	DQ5					DQ1	12		17	DQ5
DQ2	13		16	DQ4					DQ2	13		16	DQ4
VSS	14		15	DQ3					VSS	14		15	DQ3
		AI01617D									AI02303C

Table 2. Absolute Maximum Ratings (1)

Symbol	Parameter		Value	Unit
TA	Ambient Operating Temperature	Grade 1	0 to 70	°C
		Grade 6	–40 to 85
TSTG	Storage Temperature (VCC Off)	SNAPHAT	–40 to 85	°C
		SOIC	–55 to 125
TSLD (2)	Lead Solder Temperature for 10 seconds		260	°C
VIO	Input or Output Voltages		–0.3 to 7	V
VCC	Supply Voltage		–0.3 to 7	V
IO	Output Current		20	mA
PD	Power Dissipation		1	W

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

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M48Z35, M48Z35Y

Table 3. Operating Modes (1)

Mode

VCC

E

G

W

DQ0-DQ7

Power

Deselect

VIH

X

X

High Z

Standby

Write

4.75V to 5.5V

VIL

X

VIL

DIN

Active

or

Read

VIL

VIL

VIH

DOUT

Active

4.5V to 5.5V

Read

VIL

VIH

VIH

High Z

Active

Deselect

VSO to VPFD (min) (2)

X

X

X

High Z

CMOS Standby

Deselect

≤ VSO

X

X

X

High Z

Battery Back-up Mode

Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.

Figure 3. Block Diagram

				A0-A14
	LITHIUM			DQ0-DQ7
	CELL	POWER	32K x 8
	VOLTAGE SENSE		SRAM ARRAY
	AND			E
	SWITCHING	VPFD
	CIRCUITRY			W
				G
	VCC		VSS	AI01619B

The M48Z35/35Y is a non-volatile pin and function equivalent to any JEDEC standard 32K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28 pin 600mil DIP CAPHAT™ houses the M48Z35/35Y silicon with a long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.

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M48Z35, M48Z35Y

Table 4. AC Measurement Conditions

Input Rise and Fall Times	≤ 5ns
Input Pulse Voltages	0 to 3V
Input and Output Timing Ref. Voltages	1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form.

For the 28 lead SOIC, the battery package (i.e. SNAPHAT) part number is "M4Z28-BR00SH1".

The M48Z35/35Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns.

READ MODE

The M48Z35/35Y is in the Read Mode whenever W (Write Enable) is high, E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 264,144 locations in the static storage array. Thus, the unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins

within Address Access time (tAVQV) after the last address input signal is stable, providing that the E

and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access

time (tELQV) or Output Enable Access time (tGLQV).

The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activat-

Figure 4. AC Testing Load Circuit

DEVICE 645Ω

UNDER

TEST

CL = 100pF or				1.75V
5pF

CL includes JIG capacitance

AI03211

ed before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active, output data will remain valid for Output Data Hold

time (tAXQX) but will go indeterminate until the next Address Access.

WRITE MODE

The M48Z35/35Y is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum

of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write

cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G

should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.

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M48Z35, M48Z35Y

Table 5. Capacitance (1, 2)

(TA = 25 °C)

Symbol	Parameter	Test Condition	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		10	pF
CIO (3)	Input / Output Capacitance	VOUT = 0V		10	pF

Note: 1. Effective capacitance measured with power supply at 5V.

2.Sampled only, not 100% tested.

3.Outputs deselected.

Table 6. DC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; V CC = 4.75V to 5.5V or 4.5V to 5.5V)

Symbol	Parameter	Test Condition					Min	Max	Unit
ILI (1)	Input Leakage Current		0V ≤ VIN ≤ VCC					±1	µA
ILO (1)	Output Leakage Current	0V ≤ VOUT ≤ VCC						±5	µA
ICC	Supply Current		Outputs open					50	mA
ICC1	Supply Current (Standby) TTL					= VIH		3	mA
					E
ICC2	Supply Current (Standby) CMOS			= VCC – 0.2V				3	mA
			E
VIL (2)	Input Low Voltage						–0.3	0.8	V
VIH	Input High Voltage						2.2	VCC + 0.3	V
VOL	Output Low Voltage			IOL = 2.1mA				0.4	V
VOH	Output High Voltage			IOH = –1mA			2.4		V

Note: 1. Outputs deselected.

2. Negative spikes of –1V allowed for up to 10ns once per cycle.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C)

Symbol		Parameter	Min	Typ	Max	Unit
VPFD		Power-fail Deselect Voltage (M48Z35)	4.5	4.6	4.75	V
VPFD		Power-fail Deselect Voltage (M48Z35Y)	4.2	4.35	4.5	V
VSO		Battery Back-up Switchover Voltage (M48Z35/35Y)		3.0		V
tDR (2)		Expected Data Retention Time	10			YEARS
Note: 1.	All voltages referenced to VSS.
2.	At 25 °C.

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M48Z35, M48Z35Y

Table 8. Power Down/Up AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C)

Symbol					Parameter	Min	Max	Unit
tPD			or		at VIH before Power Down	0		µs
		E		W
tF (1)	VPFD (max) to VPFD (min) VCC Fall Time					300		µs
tFB (2)	VPFD (min) to VSS VCC Fall Time					10		µs
tR	VPFD (min) to VPFD (max) VCC Rise Time					10		µs
tRB	VSS to VPFD (min) VCC Rise Time					1		µs
tREC (3)	VPFD (max) to Inputs Recognized					40	200	ms

Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).

2.VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

3.tREC (min) = 20ms for industrial temperature grade (6) device.

Figure 5. Power Down/Up Mode AC Waveforms

VCC

VPFD (max)

VPFD (min)
VSO	tF				tR
		tFB	tRB
INPUTS	tPD		tDR				tREC
	RECOGNIZED		DON'T CARE				RECOGNIZED
OUTPUTS	VALID		HIGH-Z				VALID
	(PER CONTROL INPUT)					(PER CONTROL INPUT)
							AI01168C

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