SGS Thomson Microelectronics ST62T18CM6, ST62T18CM3, ST62T18CB6, ST62T18CB3, ST62P18CM6 Datasheet

ST62T18C/E18C

8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE

■3.0 to 6.0V Supply Operating Range

■8 MHz Maximum Clock Frequency

■-40 to +125°C Operating Temperature Range

■Run, Wait and Stop Modes

■5 Interrupt Vectors

■Look-up Table capability in Program Memory

■Data Storage in Program Memory: User selectable size

■Data RAM: 192 bytes

■User Programmable Options

■12 I/O pins, fully programmable as:

±Input with pull-up resistor

±Input without pull-up resistor

±Input with interrupt generation

±Open-drain or push-pull output

±Analog Input

■5 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly

■8-bit Timer/Counter with 7-bit programmable prescaler

PDIP20

PSO20

■8-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer)

■Digital Watchdog

■8-bit A/D Converter with 7 analog inputs

■8-bit Asynchronous Peripheral Interface (UART)

■On-chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator

■Oscillator Safe Guard

■Low Voltage Detector for safe Reset

■One external Non-Maskable Interrupt

■ST623x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port).

DEVICE SUMMARY

	DEVICE	OTP	EPROM	I/O Pins
		(Bytes)	(Bytes)
	ST62T18C	7948	-	12
	ST62E18C		7948	12

CDIP20W

(See end of Datasheet for Ordering Information)

Rev. 2.5

November 1999

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Table of Contents

Document

Page

ST62T18C/E18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 5
1.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
1.2	PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
1.3	MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	1.3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	1.3.2	Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	1.3.3	Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	1.3.4	Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	1.3.5	Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.3.6	Data RAM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
1.4	PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	1.4.1	Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			14
2.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
2.2	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . .			16
3.1	CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.1.1	Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	3.1.3	Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
3.2	RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	3.2.1	RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.2.2	Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.2.3	Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	3.2.4	LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	3.2.5	Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	3.2.6	MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
3.3	DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
	3.3.1	Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	3.3.2	Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
3.4	IINTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	3.4.1	Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	3.4.2	Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	3.4.3	Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	3.4.4	Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
3.5	POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		33

3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.4 UART alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.5 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.6 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.7 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 53

4.5.1 Ports Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.5.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.5.3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.5.4 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.5.5 Interrupt Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.5.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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ST62P18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			76
1.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		76
1.2	ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		76
	1.2.1	Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
	1.2.2	Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76

ST6218C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			80
1.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		80
7.3	ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		80
7.4	ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		82
	7.4.1	Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
	7.4.2	Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST62T18C and ST62E18C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which are targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a

Figure 1. Block Diagram

TEST/VPP

NMI

TEST

INTERRUPT

PROGRAM

Memory

7948 bytes

PC

STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6

8-BIT

A/D CONVERTER

DATA ROM

USER

SELECTABLE

DATA RAM

192 Bytes

8 BIT CORE

POWER OSCILLATOR RESET SUPPLY

VDD VSS OSCin OSCout RESET

(VPP on EPROM/OTP versions only)

ST62T18C/E18C

common core is surrounded by a number of onchip peripherals.

The ST62E18C is the erasable EPROM version of the ST62T18C device, which may be used to emulate the ST62T18C device, as well as the respective ST6218C ROM devices.

		PA1 / 20 mA Sink
	PORT A	PA2/ARTIMout / 20 mA Sink
		PA3/ARTIMin/ 20 mA Sink
		PA4..PA 5/20 mA Sink
	PORT B	PB4..PB6/Ain
		PD4/Ain/RXD1
	PORT D	PD5/Ain/TXD1
		PD6,PD7/Ain
	UART
	AUTORELOAD
	TIMER
	TIMER	TIMER
	DIGITAL
	WATCHD OG

VR01823F

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INTRODUCTION (Cont'd)

OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options defined in the programmable option byte of the OTP/ EPROM versions.OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required.

Figure 2. ST62T18C/E18C Pin Configuration

These compact low-cost devices feature a Timer

VDD	1	20	VSS
TIMER	2	19	PA1*
OSCin	3	18	PA2/ARTIMout*
OSCout	4	17	PA3/ARTIMin*
NMI	5	16	PA4*
(1)	6	15	PA5*
TEST/VPP
RESET	7	14	PD4/Ain/RXD1
Ain/PB6	8	13	PD5/Ain/TXD1
Ain/PB5	9	12	PD6/Ain
Ain/PB4	10	11	PD7/Ain

(1)V on EPROM/OTP only

PP

(*) 20 mA Sink

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1.2 PIN DESCRIPTIONS

VDD and VSS. Power is supplied to the MCU via these two pins. VDD is the power connection and VSS is the ground connection.

OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active-low RESET pin is used to restart the microcontroller.

TEST/VPP. The TEST must be held at VSS for normal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/ OTP programming Mode is entered.

NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. The NMI input is falling edge sensitive with Schmitt trigger characteristics. The user can select as option the availability of an on-chip pull-up at this pin.

PA1-PA5. These 5 lines are organised as one I/O port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, input with interrupt generation and pull-up resistor, open-drain or push-pull outputs.

PA3/ARTIMout and PA4/ARTIMin can be used respectively as output and input pins for the embedded 8-bit Auto-Reload Timer.

In addition, PA1-PA5 can sink 20mA for direct LED or TRIAC drive.

PB4...PB6. These 3 lines are organised as one I/O port (B). Each line may be configured under software control as inputs with or without internal pullup resistors, input with interrupt generation and pull-up resistor, open-drain or push-pull outputs, analog inputs for the A/D converter.

PD4...PD7. These 4 lines are organised as one I/O port (portD). Each line may be configured under software control as input with or without internal pull-up resistor, input with interrupt generation and pull-up resistor, analog input open-drain or pushpull output. In addition, the pins PD5/TXD1 and PD4/RXD1 can be used as UART output (PD5/ TXD1) or UART input (PD4/RXD1).

TIMER. This is the TIMER 1 I/O pin. In input mode, it is connected to the prescaler and acts as external timer clock or as control gate for the internal timer clock. In output mode, the TIMER pin outputs the data bit when a time-out occurs.The user can select as option the availability of an on-chip pullup at this pin.

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1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.

Briefly, Program space contains user program code in Program memory and user vectors; Data space contains user data in RAM and in Program memory, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.

1.3.2 Program Space

Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register).

Program Space is organised in 4K pages. 4 of them are addressed in the 000h-7FFh locations of the Program Space by the Program Counter and by writing the appropriate code in the Program ROM Page Register (PRPR register). A common

Figure 4. Memory Addressing Diagram

PROGRAM SPACE

0000h

0-63

PROGRAM

MEMORY

0FF0h

INTERRUPT &

RESET VECTORS

0FFFh

(STATIC) 2K page is available all the time for interrupt vectors and common subroutines, independently of the PRPR register content. This ªSTATICº page is directly addressed in the 0800h-0FFFh by the MSB of the Program Counter register PC 11. Note this page can also be addressed in the 0007FFh range. It is two different ways of addressing the same physical memory.

Jump from a dynamic page to another dynamic page is achieved by jumping back to the static page, changing contents of PRPR and then jumping to the new dynamic page.

Figure 3. 8Kbytes Program Space Addressing

		ROM SPACE
PC
SPACE	0000h		1FFFh
000h		Page 1
	Page 0		Page 2 Page 3
7FFh		Static
		Page
800h	Page 1
FFFh	Static
	Page

	DATA SPACE
000h
	RAM / EEPROM
	BANKING AREA
03Fh
040h
	DATA READ-ONLY
	MEMORY WINDOW
07Fh
080h	X REGISTER
081h	Y REGISTER
082h	V REGISTER
083h	W REGISTER
084h	RAM
0C0h	DATA READ-ONLY
	MEMORY
	WINDOW SELECT
	DATA RAM
	BANK SELECT
0FFh	ACCUMULATOR

VR01568

8/82

MEMORY MAP (Cont'd)

Table 1. ST62E18C/T18C Program Memory Map

	ROM Page	Device Address	Description
	Page 0	0000h-007Fh	Reserved
		0080h-07FFh	User ROM
		0800h-0F9Fh	User ROM
		0FA0h-0FEFh	Reserved
	Page 1	0FF0h-0FF7h	Interrupt Vectors
	ªSTATICº	0FF8h-0FFBh	Reserved
		0FFCh-0FFDh	NMI Vector
		0FFEh-0FFFh	Reset Vector
	Page 2	0000h-000Fh	Reserved
		0010h-07FFh	User ROM
	Page 3	0000h-000Fh	Reserved
		0010h-07FFh	User ROM

Note: OTP/EPROM devices can be programmed with the development tools available from STMicroelectronics (ST62E2XC-EPB or ST622XC-KIT).

1.3.2.1 Program ROM Page Register (PRPR)

The PRPR register can be addressed like a RAM location in the Data Space at the address CAh; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the 2-Kbyte ROM bank of the Program Space that will be addressed. The number of the page has to be loaded in the PRPR register. Refer to the Program Space description for additional information concerning the use of this register. The PRPR register is not modified when an interrupt or a subroutine occurs.

Care is required when handling the PRPR register as it is write only. For this reason, it is not allowed to change the PRPR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. This operation may be necessary if common routines and interrupt service routines take more than 2K bytes; in this case it could be necessary to divide the interrupt service routine into a (minor) part in the static page (start and end) and to a second (major) part in one of the dynamic pages. If it is impossible to avoid the writing of this register in interrupt service routines, an image of this register must be saved in a RAM location, and each time the program writes to the PRPR it must write also to the image register. The image register must be written before PRPR, so if an interrupt occurs between the two instructions the PRPR is not affected.

ST62T18C/E18C

Program ROM Page Register (PRPR)

Address: CAh Ð Write Only

7					0
-	-	-	-	-	- PRPR1 PRPR0

Bits 2-7= Not used.

Bit 5-0 = PRPR1-PRPR0: Program ROM Select.

These two bits select the corresponding page to be addressed in the lower part of the 4K program address space as specified in Table 2.

This register is undefined on Reset. Neither read nor single bit instructions may be used to address this register.

Table 2. 6Kbytes Program ROM Page Register

Coding

PRPR1	PRPR0	PC bit 11	Memory Page
X	X	1	Static Page (Page 1)
0	0	0	Page 0
0	1	0	Page 1 (Static Page)
1	0	0	Page 2
1	1	0	Page 3

1.3.2.2 Program Memory Protection

The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.

In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.

Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted.

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ST62T18C/E18C

MEMORY MAP (Cont'd)

1.3.3 Data Space

Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in Program memory.

1.3.3.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in Program memory.

1.3.3.2 Data RAM

In ST62T18C and ST62E18C devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register).

Additional RAM pages can also be addressed using banks of 64 bytes located between addresses 00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents.

Table 3. Additional RAM Banks

Device	RAM
ST62T18C/E18C	2 x 64 bytes

Table 4. ST62T18C/E18C Data Memory Space

	DATA RAM BANKS	000h
		03Fh
	DATA ROM WINDOW AREA	040h
		07Fh
	X REGISTER	080h
	Y REGISTER	081h
	V REGISTER	082h
	W REGISTER	083h
	DATA RAM	084h
		0BFh
	PORT A DATA REGISTER	0C0h
	PORT B DATA REGISTER	0C1h
	RESERVED	0C2h
	PORT D DATA REGISTE R	0C3h
	PORT A DIRECTION REGISTE R	0C4h
	PORT B DIRECTION REGISTE R	0C5h
	RESERVED	0C6h
	PORT D DIRECT ION REGISTE R	0C7h
	INTERRUPT OPTION REGISTER	0C8h*
	DATA ROM WINDOW REGISTE R	0C9h*
	ROM BANK SELECT REGISTE R	0CAh*
	RAM BANK SELECT REGISTE R	0CBh*
	PORT A OPTION REGISTER	0CCh
	PORT B OPTION REGISTER	0CDh
	RESERVED	0CEh
	PORT D OPTION REGISTER	0CFh
	A/D DATA REGISTER	0D0h
	A/D CONTROL REGISTER	0D1h
	TIMER 1 PRESCALE R REGISTER	0D2h
	TIMER 1 COUNTER REGISTER	0D3h
	TIMER 1 STATUS/CONTROL REGISTER	0D4h
	RESERVED	0D5h
	UART DATA SHIFT REGISTER	0D6h
	UART STATUS CONTROL REGISTER	0D7h
	WATCHDOG REGISTER	0D8h
	RESERVED	0D9h
	I/O INTER RUPT POLARITY REGISTER	0DAh
	RESERVED	0DCh*
	RESERVED	0DDh
	RESERVED	0DEh
		0E4h
	ARTIMER MODE/CONTROL REGISTER	0E5h
	ARTIME R STATUS/CONTROL REGISTER ARSC0	0E6h
	ARTIME R STATUS/CONTROL REGISTER ARSC1	0E7h
	RESERVED	0E8h
	ARTIMER RELOAD/CAPTURE REGIST ER	0E9h
	ARTIMER COMPARE REGISTER	0EAh
	. ARTIMER LOAD REGISTER	0EBh
	RESERVED	0ECh
	ACCUMULATOR	OFFh

* WRIT E ONLY REGISTER

10/82

ST62T18C/E18C

MEMORY MAP (Cont'd)

1.3.5 Data Window Register (DWR)

The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 1FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data Window Register (DWR).

The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the 64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 00h loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data read-only memory window area.

Data Window Register (DWR)

Address: 0C9h Ð Write Only

7

0

-DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

Bits 7 = Not used.

Bit 6-0 = DWR6-DWR0: Data read-only memory Window Register Bits. These are the Data readonly memory Window bits that correspond to the upper bits of the data read-only memory space.

Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to address this register.

Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DWR is not affected.

Figure 5. Data read-only memory Window Memory Addressing

DATA ROM	13	12	11	10	9	8	7	6	5	4	3	2	1	0	PROGRAM SPACE ADDRESS
															READ
WINDOW REGISTER 7		6	5	4	3	2	1	0
CONTENTS									5	4	3	2	1	0	DATA SPACE ADDRESS
(DWR)
							0	1							40h-7Fh
															IN INSTRUCTION

Example:

DWR=28h	0	1	0	1	0	0	0
						0	1	0	1	1	0	0	1	DATA SPACE ADDRESS
														59h
ROM	0	1	0	1	0	0	0	0	1	1	0	0	1
ADDRESS:A19h

VR01573A

11/82

ST62T18C/E18C

MEMORY MAP (Cont'd)

1.3.6 Data RAM Bank Register (DRBR)

Address: CBh Ð Write only

7				0
-	-	- DRBR4 DRBR3 -	-	-

Bit 7-5 = These bits are not used

Bit 4 - DRBR4. This bit, when set, selects RAM Page 2.

Bit 3 - DRBR3. This bit, when set, selects RAM Page 1.

Bit 2.0 These bits are not used.

The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR register) located at address CBh of the Data Space according to Table 1. No more than one bank should be set at a time.

The DRBR register can be addressed like a RAM Data Space location at the address CBh; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address).

This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to

the Data Space description for additional information. The DRBR register is not modified when an interrupt or a subroutine occurs.

Notes:

Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors.

Table 5. Data RAM Bank Register Set-up

DRBR	ST62T18C/E18C
00h	None
01h	Reserved
02h	Reserved
08h	RAM Page 1
10h	RAM Page 2
other	Reserved

12/82

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capability to the MCUs. Option byte's content is automatically read, and the selected options enabled, when the chip reset is activated.

It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING mode of the programmer.

The option bytes are located in a non-user map. No address has to be specified.

EPROM Code Option Byte (LSB)

7							0
PRO-	OSCIL	PORT	-	NMI	TIM	WDACT	OS-
TECT		PULL		PULL	PULL		GEN

EPROM Code Option Byte (MSB)

	15							8
	-	-	-	ADC	UART	-	EXTC-	LVD
				SYNCHRO	FRAME		NTL

D15-D13. Reserved. Must be cleared.

ADC SYNCHRO. When set, an A/D conversion is started upon WAIT instruction execution, in order to reduce supply noise. When this bit is low, an A/ D conversion is started as soon as the STA bit of the A/D Converter Control Register is set.

D11. UART Frame. When set, UART transmission and reception are based on a 11-bit frame. When cleared, a 10-bit frame is used.

D10. Reserved. This bit must be cleared

EXTCNTL. External STOP MODE control.. When EXTCNTL is high, STOP mode is available with watchdog active by setting NMI pin to one. When

ST62T18C/E18C

EXTCNTL is low, STOP mode is not available with the watchdog active.

LVD. LVD RESET enable.When this bit is set, safe RESET is performed by MCU when the supply voltage is too low. When this bit is cleared, only power-on reset or external RESET are active.

PROTECT. Readout Protection. This bit allows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware.. When this bit is low, the user program can be read.

OSCIL. Oscillator selection. When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided.

D5. Port Pull. This bit must be set high to have pull-up input state at reset on the I/O port. When this bit is low, I/O ports are in input without pull-up (high impedance state at reset).

D4. Reserved. Must be set to 1.

NMI PULL. NMI Pull-Up. This bit must be set high to configure the NMI pin with a pull-up resistor. When it is low, no pull-up is provided.

TIM PULL.TIM Pull-Up. This bit must be set high to configure the TIMER pin with a pull-up resistor. When it is low, no pull-up is provided.

WDACT. This bit controls the watchdog activation. When it is high, hardware activation is selected. The software activation is selected when WDACT is low.

OSGEN. Oscillator Safe Guard. This bit must be set high to enable the Oscillator Safe Guard. When this bit is low, the OSG is disabled.

The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode).

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ST62T18C/E18C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU corefeatures six registers and three pairs of flags available to the programmer. These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space.

Figure 6. ST6 Core Block Diagram

Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space.

Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space.

Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

		0,01 TO 8MHz
	RESET	OSCin	OSCout
			INTERRUPTS
		CONTROLLER
					DATA SPACE
		FLAG	CONTROL
	OPCODE		SIGNALS		DATA
		VALUES	ADDRESS /READ LINE
		2			RAM/EEPR OM
PROGRAM					DATA
ROM/EPROM			ADDRESS
				256	ROM/EPROM
			DECODER
		A-DATA B-DATA			DEDICAT IONS
					ACCUMULATOR
12	Program Counter
	and	FLAGS
	6 LAYER STACK		ALU

RESULTS TO DATA SPACE (WRITE LINE)

VR01811

14/82

CPU REGISTERS (Cont'd)

However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:

-JP (Jump) instructionPC=Jump address

-CALL instructionPC= Call address

-Relative Branch Instruction.PC= PC +/- offset

- Interrupt	PC=Interrupt vector
- Reset	PC= Reset vector

-RET & RETI instructionsPC= Pop (stack)

-Normal instructionPC= PC + 1

Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI).

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status.

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction.

The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.

Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is

ST62T18C/E18C

automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its ªdeepestº position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.

Figurel 7. ST6 CPU Programming Mode

	INDEX	b7	X REG. POINTER		b0	SHORT
	REGISTER
		b7	Y REG. POINTER		b0	DIRECT
						ADDRESSING
		b7	V REGISTER		b0	MODE
		b7	W REGISTER		b0
		b7	ACCUM ULATO R		b0
	b11	PROGRAM COUNTER			b0
		SIX LEVELS
		STACK REGISTER
	NORMAL FLAGS			C	Z
	INTERRUPT FLAGS			C	Z
	NMI FLAGS			C	Z
						VA000423

15/82

ST62T18C/E18C

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor

(RNET). In addition, a Low Frequency Auxiliary Oscillator (LFAO) can be switched in for security rea-

sons, to reduce power consumption, or to offer the benefits of a back-up clock system.

Figure 8. Oscillator Configurations

CRYSTAL/RES ONATOR CLOCK

CRYSTAL/RESON ATOR option

ST6xxx

The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automatically limits the internal clock frequency (fINT) as a function of VDD, in order to guarantee correct operation. These functions are illustrated in Figure 2, Figure 3, Figure 4 and Figure 5.

OSCin OSCout

CL1n

CL2

Figure 1 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor (RNET), or the lowest cost solution using only the LFAO. CL1 an CL2 should have a capacitance in the range 12 tST6_CLK1o 22 pF for an oscillator frequency in the 4-8 MHz range.

The internal MCU clock frequency (fINT) is divided by 12 to drive the Timer, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 4.

With an 8MHz oscillator frequency, the fastest machine cycle is therefore 1.625μs.

A machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five machine cycles for execution.

EXTERNAL CLOCK CRYSTAL/RESON ATOR option

ST6xxx

OSCin OSCout

NC

RC NETW ORK

RC NETW ORK option

ST6xxx

OSCin OSCout

3.1.1 Main Oscillator

The oscillator configuration may be specified by selecting theappropriate option.When the CRYSTAL/ RESONATORoption isselected, itmustbeusedwith a quartz crystal, a ceramic resonator or an external signal providedonthe OSCinpin.When theRCNETWORK option is selected, the system clock is generated by an external resistor.

The main oscillator can be turned off (when the OSG ENABLED option is selected) by setting the OSCOFF bit of the ADC Control Register. The Low Frequency Auxiliary Oscillator is automatically started.

NC

RNET

INTEGRA TED CLOCK CRYSTAL/RESON ATOR option

OSG ENABLED option

ST6xxx

OSCin OSCout

NC

16/82

CLOCK SYSTEM (Cont'd)

Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at fLFAO clock frequency.

3.1.2Low Frequency Auxiliary Oscillator (LFAO)

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a safety oscillator in case of main oscillator failure.

This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillator defective, no clock circuitry provided, main oscillator switched off...).

User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced fLFAO frequency. The A/D converter accuracy is decreased, since the internal frequency is below 1MHz.

At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay until the Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.

ADCR

Address: 0D1h Ð			Read/Write
7							0
ADCR	ADCR	ADCR	ADCR	ADCR	OSC	ADCR	ADCR
7	6	5	4	3	OFF	1	0

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:

ADC Control Register. These bits are not used.

Bit 2 = OSCOFF. When low, this bit enables main oscillator to run. The main oscillator is switched off when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic func-

ST62T18C/E18C

tions: it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct operation even if the power supply should drop.

The OSG is enabled or disabled by choosing the relevant OSG option. It may be viewed as a filter whose cross-over frequency is device dependent.

Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustrated in Figure 2). In all cases, when the OSG is active, the maximum internal clock frequency, fINT, is limited to fOSG, which is supply voltage dependent. This relationship is illustrated in Figure 5.

When the OSG is enabled, the Low Frequency Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of the main oscillator (see Figure 3).

Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on VDD), and below fOSG: the maximum authorised frequency with OSG enabled.

Note. The OSG should be used wherever possible as it provides maximum safety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency to fOSG.

Warning: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and a maximum value and is not accurate.

For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.

It should also be noted that power consumption in Stop mode is higher when the OSG is enabled (around 50μA at nominal conditions and room temperature).

17/82

ST62T18C/E18C

CLOCK SYSTEM (Cont'd)

Figure 9. OSG Filtering Principle

(1)

(2)

(3)

(4)

(1)Maximum Frequency for the device to work correctly

(2)Actual Quartz Crystal Frequency at OSCin pin

(3)Noise from OSCin

(4)Resulting Internal Frequency

Figure 10. OSG Emergency Oscillator Principle

Main

Oscillator

Emergency

Oscillator

Internal

Frequency

VR001932

VR001933

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			ST62T18C/E18C
CLOCK SYSTEM (Cont'd)
Figure 11. Clock Circuit Block Diagram
			POR
		: 13	Core
OSG
			TIMER 1
MAIN	M	fINT	Watchdog
	U	: 12

OSCILLATOR

X

LFAO

: 1

Main Oscillator off

Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)

Maximum FREQUENCY (MHz)
8
7	NOT	4
6					3
	FUNCTIONALITYIS GUARANTEED THISIN AREA					fOSG Min (at 125°C)
						fOSG
5
4					2	fOSG Min (at 85°C)
3
2
					1
1	3
2.5		3.6	4	4.5	5	5.5	6

SUPPLY VOLTAGE (VDD)

VR01807J

Notes:

1.In this area, operation is guaranteed at the quartz crystal frequency.

2.When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guar-

anteed at a frequency of at least fOSG Min.

3. When the OSG is disabled, operation in this

area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept a fOSG.

4. When the OSG is disabled, operation in this area is not guaranteed

When the OSG is enabled, access to this area is prevented. The internal frequency is kept at fOSG.

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ST62T18C/E18C

3.2 RESETS

The MCU can be reset in four ways:

±by the external Reset input being pulled low;

±by Power-on Reset;

±by the digital Watchdog peripheral timing out.

±by Low Voltage Detection (LVD)

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low.

If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking up the MCU by detecting around 2V a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence

is executed immediately following the internal delay.

To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from 0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (presenting oscillation) VDD supplies.

An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performances.

Figure 13. Reset and Interrupt Processing

RESET

NMI MASK SET

INT LATCH CLEARED ( IF PRESENT )

SELECT

NMI MODE FLAGS

PUT FFEH

ON ADDRESS BUS

YES

IS RESET STILL

PRESENT?

NO

LOAD PC

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

VA000427

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ST62T18C/E18C

RESETS (Cont'd)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter.

The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as user option, features static Reset when supply voltage is below a reference value. Thanks to this feature, external reset circuit can be removed while keeping the application safety. This SAFE RESET is effective as well in Power-on phase as in power supply drop with different reference val-

ues, allowing hysteresis effect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start's running and sinking current on the supply.

As long as the supply voltage is below the reference value, there is a internal and static RESET command. The MCU can start only when the supply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU: RESET active below the voltage reference, and running mode over the voltage reference as shown on the Figure 14, that represents a powerup, power-down sequence.

Note: When the RESET state is controlled by one of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET pin is tied to low logic level.

Figure 14. LVD Reset on Power-on and Power-down (Brown-out)

VDD

VUp

Vdn

RESET	RESET
	time

VR02106A

3.2.5 Application Notes

No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to VDD must be avoided in order to ensure safe behaviour of the internal reset sources (AND.Wired structure).

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ST62T18C/E18C

RESETS (Cont'd)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced.

Figure 15. Reset and Interrupt Processing

RESET

JP	JP:2 BYTES/4 CYCLES

RESET

VECTOR

INITIALIZATION

ROUTINE	RETI: 1 BYTE/2 CYCLES
	RETI

VA00181

Figure 16. Reset Block Diagram

VDD			ST6
fOSC		CK	INTERNA L
			RESET
RPU		COUNTER
	AND. Wired
1)
RESD
RESET	RESET	RESET
POWER ON RESET
WATCHD OG RESET
LVD RESET
			VR02107A

1) Resistive ESD protection. Value not guaranteed.

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ST62T18C/E18C

RESETS (Cont'd)

Table 6. Register Reset Status

Register

Address(es)

Status

Comment

Port Data Registers	0C0h, 0C1h, 0C3h
Port Direction Register	0C4h, 0C5h, 0C7h
Port Option Register	0CCh, 0CDh, 0CFh
Interrupt Option Register	0C8h
TIMER Status/Control	0D4h	00h
AR TIMER Mode/Control Register	0E5h
AR TIMER Status/Control Register 0	0E6h
AR TIMER Status/Control Register 1	0E7h
X, Y, V, W, Register	080H TO 083H
Accumulator	0FFh
Data RAM	084h to 0BFh
Data RAM Page Register	0CBh
Data ROM Window Register	0C9h	Undefined
A/D Result Register	0D0h
ARTIMER Reload/Capture Register	0E9h
ARTIMER Compare Registers	0EAh
ARTIMER Load Registers	0EBh
TIMER Counter Register	0D3h	FFh
TIMER Prescaler Register	0D2h	7Fh
Watchdog Counter Register	0D8h	FEh
A/D Control Register	0D1h	40h
UART Status Control	0D7h

I/O are Input with or without pull-up depending on PORT PULL option

Interrupt disabled

TIMER disabled

AR TIMER disabled

Max count loaded

A/D in Stand-by

UART disabled

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ST62T18C/E18C

3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets.

The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. In the event of a software mishap (usually caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind.

Watchdog behaviour is governed by two options, known as ªWATCHDOG ACTIVATIONº (i.e. HARDWARE or SOFTWARE) and ªEXTERNAL STOP MODE CONTROLº (see Table 7).

In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set.

When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU.

In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown.

However, when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode.

Execution of the STOP instruction is then governed by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode.

When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.

Table 7. Recommended Option Choices

Functions Required	Recommended Options
Stop Mode & Watchdog	ªEXTERNAL STOP MODEº & ªHARDWARE WATCHDOGº
Stop Mode	ªSOFTWARE WATCHDOGº
Watchdog	ªHARDWARE WATCHDOGº

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ST62T18C/E18C

DIGITAL WATCHDOG (Cont'd)

The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR). This register is set to 0FEh on Reset: bit C is cleared to ª0º, which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are all set to ª1º, thus selecting the longest Watchdog timer period. This time period can be set to the user's requirements by setting the appropriate value for bits T0 to T5 in the DWDR register. The SR bit must be set to ª1º, since it is this bit which generates the Reset signal when it changes to ª0º; clearing this bit would generate an immediate Reset.

It should be noted that the order of the bits in the DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the DWDR register corresponds, in fact, to T0 and bit 2 to T5. The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timer downcounter is illustrated in Figure 17.

Only the 6 most significant bits may be used to define the time period, since it is bit 6 which triggers the Reset when it changes to ª0º. This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8MHz, this is equivalent to timer periods ranging from 384μs to 24.576ms).

Figure 17. Watchdog Counter Control

	D0		C
REGISTERCONTROLWATCHDOG	D1		SR
		COUNTERWATCHDOG
	D2			RESET
			T5
	D3		T4
	D4		T3
	D5		T2
	D6		T1
	D7		T0
			28	OSC 12

VR02068A

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