M29F800AT
M29F800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory
PRELIMINARY DATA
■SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
■ACCESS TIME: 70ns
■PROGRAMMING TIME
±8μs per Byte/Word typical
■19 MEMORY BLOCKS
±1 Boot Block (Top or Bottom Location)
±2 Parameter and 16 Main Blocks
■PROGRAM/ERASE CONTROLLER
±Embedded Byte/Word Program algorithm
±Embedded Multi-Block/Chip Erase algorithm
±Status Register Polling and Toggle Bits
±Ready/Busy Output Pin
■ERASE SUSPEND and RESUME MODES
±Read and Program another Block during Erase Suspend
■TEMPORARY BLOCK UNPROTECTION MODE
■LOW POWER CONSUMPTION
±Standby and Automatic Standby
■100,000 PROGRAM/ERASE CYCLES per BLOCK
■20 YEARS DATA RETENTION
±Defectivity below 1 ppm/year
■ELECTRONIC SIGNATURE
±Manufacturer Code: 0020h
±M29F800AT Device Code: 00ECh
±M29F800AB Device Code: 0058h
44
|
1 |
TSOP48 (N) |
SO44 (M) |
12 x 20mm |
|
Figure 1. Logic Diagram
|
VCC |
|
|
19 |
|
15 |
|
A0-A18 |
|
DQ0-DQ14 |
|
W |
|
DQ15A±1 |
|
E |
M29F800AT |
BYTE |
|
M29F800AB |
|||
|
|
||
G |
|
RB |
|
RP |
|
|
VSS
AI02198B
January 2000 |
1/21 |
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M29F800AT, M29F800AB
Figure 2A. TSOP Connections
A15 |
1 |
|
48 |
A16 |
A14 |
|
|
|
BYTE |
A13 |
|
|
|
VSS |
A12 |
|
|
|
DQ15A±1 |
A11 |
|
|
|
DQ7 |
A10 |
|
|
|
DQ14 |
A9 |
|
|
|
DQ6 |
A8 |
|
|
|
DQ13 |
NC |
|
|
|
DQ5 |
NC |
|
|
|
DQ12 |
W |
|
|
|
DQ4 |
RP |
12 |
M29F800AT |
37 |
VCC |
NC |
13 |
M29F800AB |
36 |
DQ11 |
NC |
|
|
|
DQ3 |
RB |
|
|
|
DQ10 |
A18 |
|
|
|
DQ2 |
A17 |
|
|
|
DQ9 |
A7 |
|
|
|
DQ1 |
A6 |
|
|
|
DQ8 |
A5 |
|
|
|
DQ0 |
A4 |
|
|
|
G |
A3 |
|
|
|
VSS |
A2 |
|
|
|
E |
A1 |
24 |
|
25 |
A0 |
|
|
|
AI02199 |
|
Table 1. Signal Names
A0-A18 |
Address Inputs |
DQ0-DQ7 |
Data Inputs/Outputs |
DQ8-DQ14 |
Data Inputs/Outputs |
DQ15A±1 |
Data Input/Output or Address Input |
E |
Chip Enable |
G |
Output Enable |
W |
Write Enable |
RP |
Reset/Block Temporary Unprotect |
RB |
Ready/Busy Output |
BYTE |
Byte/Word Organization Select |
VCC |
Supply Voltage |
VSS |
Ground |
NC |
Not Connected Internally |
Figure 2B. SO Connections
RB |
1 |
44 |
RP |
A18 |
2 |
43 |
W |
A17 |
3 |
42 |
A8 |
A7 |
4 |
41 |
A9 |
A6 |
5 |
40 |
A10 |
A5 |
6 |
39 |
A11 |
A4 |
7 |
38 |
A12 |
A3 |
8 |
37 |
A13 |
A2 |
9 |
36 |
A14 |
A1 |
10 |
35 |
A15 |
A0 |
11 |
M29F800AT 34 |
A16 |
E |
12 M29F800AB 33 |
BYTE |
|
VSS |
13 |
32 |
VSS |
G |
14 |
31 |
DQ15A±1 |
DQ0 |
15 |
30 |
DQ7 |
DQ8 |
16 |
29 |
DQ14 |
DQ1 |
17 |
28 |
DQ6 |
DQ9 |
18 |
27 |
DQ13 |
DQ2 |
19 |
26 |
DQ5 |
DQ10 |
20 |
25 |
DQ12 |
DQ3 |
21 |
24 |
DQ4 |
DQ11 |
22 |
23 |
VCC |
|
|
AI02101B |
|
SUMMARY DESCRIPTION
The M29F800A is an 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
2/21
M29F800AT, M29F800AB
Table 2. Absolute Maximum Ratings (1)
Symbol |
Parameter |
Value |
Unit |
|
Ambient Operating Temperature (Temperature Range Option 1) |
0 to 70 |
°C |
T |
Ambient Operating Temperature (Temperature Range Option 6) |
±40 to 85 |
° |
A |
C |
||
|
Ambient Operating Temperature (Temperature Range Option 3) |
±40 to 125 |
°C |
T |
Temperature Under Bias |
±50 to 125 |
° |
BIAS |
C |
||
T |
Storage Temperature |
±65 to 150 |
° |
STG |
C |
||
VIO (2) |
Input or Output Voltage |
±0.6 to 6 |
V |
VCC |
Supply Voltage |
±0.6 to 6 |
V |
VID |
Identification Voltage |
±0.6 to 13.5 |
V |
Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to ±2V during transition and for less than 20ns during transitions.
The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm) and SO44 packages. Access times of 70ns and 90ns are available. The memory is supplied with all the bits erased (set to '1').
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A±1 Low will select the LSB of the Word on the other addresses, DQ15A±1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.
3/21
M29F800AT, M29F800AB
Table 3A. M29F800AT Block Addresses |
Table 3B. M29F800AB Block Addresses |
||||
Size |
Address Range |
Address Range |
Size |
Address Range |
Address Range |
(Kbytes) |
(x8) |
(x16) |
(Kbytes) |
(x8) |
(x16) |
16 |
FC000h-FFFFFh |
7E000h-7FFFFh |
64 |
F0000h-FFFFFh |
78000h-7FFFFh |
8 |
FA000h-FBFFFh |
7D000h-7DFFFh |
64 |
E0000h-EFFFFh |
70000h-77FFFh |
8 |
F8000h-F9FFFh |
7C000h-7CFFFh |
64 |
D0000h-DFFFF h |
68000h-6FFFFh |
32 |
F0000h-F7FFFh |
78000h-7BFFFh |
64 |
C0000h-CFFFF h |
60000h-67FFFh |
64 |
E0000h-EFFFF h |
70000h-77FFFh |
64 |
B0000h-BFFFFh |
58000h-5FFFFh |
64 |
D0000h-DFFFFh |
68000h-6FFFFh |
64 |
A0000h-AFFFFh |
50000h-57FFFh |
64 |
C0000h-CFFFFh |
60000h-67FFFh |
64 |
90000h-9FFFFh |
48000h-4FFFFh |
64 |
B0000h-BFFFF h |
58000h-5FFFFh |
64 |
80000h-8FFFFh |
40000h-47FFFh |
64 |
A0000h-AFFFF h |
50000h-57FFFh |
64 |
70000h-7FFFFh |
38000h-3FFFFh |
64 |
90000h-9FFFFh |
48000h-4FFFFh |
64 |
60000h-6FFFFh |
30000h-37FFFh |
64 |
80000h-8FFFFh |
40000h-47FFFh |
64 |
50000h-5FFFFh |
28000h-2FFFFh |
64 |
70000h-7FFFFh |
38000h-3FFFFh |
64 |
40000h-4FFFFh |
20000h-27FFFh |
64 |
60000h-6FFFFh |
30000h-37FFFh |
64 |
30000h-3FFFFh |
18000h-1FFFFh |
64 |
50000h-5FFFFh |
28000h-2FFFFh |
64 |
20000h-2FFFFh |
10000h-17FFFh |
64 |
40000h-4FFFFh |
20000h-27FFFh |
64 |
10000h-1FFFFh |
08000h-0FFFFh |
64 |
30000h-3FFFFh |
18000h-1FFFFh |
32 |
08000h-0FFFFh |
04000h-07FFFh |
64 |
20000h-2FFFFh |
10000h-17FFFh |
8 |
06000h-07FFFh |
03000h-03FFFh |
64 |
10000h-1FFFFh |
08000h-0FFFFh |
8 |
04000h-05FFFh |
02000h-02FFFh |
64 |
00000h-0FFFFh |
00000h-07FFFh |
16 |
00000h-03FFFh |
00000h-01FFFh |
Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.
Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.
A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details.
Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 14 and Figure 10, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode.
4/21
Table 4A. Bus Operations, BYTE = VIL
Operation |
E |
G |
W |
|
Bus Read |
VIL |
VIL |
VIH |
|
Bus Write |
VIL |
VIH |
VIL |
|
Output Disable |
X |
VIH |
VIH |
|
Standby |
VIH |
X |
X |
|
Read Manufacturer |
VIL |
VIL |
VIH |
|
Code |
||||
|
|
|
||
Read Device Code |
VIL |
VIL |
VIH |
|
Note: X = VIL or VIH. |
|
|
|
M29F800AT, M29F800AB
Address Inputs
DQ15A±1, A0-A18
Cell Address
Command Address
X
X
A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH
A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH
Data Inputs/Outpu ts
DQ14-DQ8 |
DQ7-DQ0 |
|
Hi-Z |
Data Output |
|
Hi-Z |
Data Input |
|
Hi-Z |
Hi-Z |
|
Hi-Z |
Hi-Z |
|
Hi-Z |
20h |
|
Hi-Z |
ECh (M29F800AT) |
|
58h (M29F800AB) |
||
|
Table 4B. Bus Operations, BYTE = VIH
Operation |
E |
G |
W |
|
Bus Read |
VIL |
VIL |
VIH |
|
Bus Write |
VIL |
VIH |
VIL |
|
Output Disable |
X |
VIH |
VIH |
|
Standby |
VIH |
X |
X |
|
Read Manufacturer |
VIL |
VIL |
VIH |
|
Code |
||||
|
|
|
||
Read Device Code |
VIL |
VIL |
VIH |
|
Note: X = VIL or VIH. |
|
|
|
Address Inputs |
Data Inputs/Outpu ts |
|
A0-A18 |
DQ15A±1, DQ14-DQ0 |
|
Cell Address |
Data Output |
|
Command Address |
Data Input |
|
X |
Hi-Z |
|
X |
Hi-Z |
|
A0 = VIL, A1 = VIL, A9 = VID, |
0020h |
|
Others VIL or VIH |
||
|
||
A0 = VIH, A1 = VIL, A9 = VID, |
00ECh (M29F800AT) |
|
Others VIL or VIH |
0058h (M29F800AB) |
VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1μF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4.
VSS Ground. The VSS Ground is the reference for all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 4A and 4B, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad-
5/21
M29F800AT, M29F800AB
dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current, ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.
Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4A and 4B, Bus Operations.
Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Block Unprotection operations must only be performed on programming equipment.
For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. In this case, after at least 50ns, an address transition or Chip Enable going Low is required before reading correct data. The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8- bit mode. See either Table 5A, or 5B, depending on the configuration that is being used, for a summary of the commands.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.
If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10μs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F800AT is 00ECh and for the M29F800AB is 0058h.
The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re-
6/21
M29F800AT, M29F800AB
Table 5A. Commands, 16-bit mode, BYTE = VIH
Command
Length
|
|
Bus Write Operations |
|
|
|
1st |
2nd |
3rd |
4th |
5th |
6th |
Addr Data |
Addr Data |
Addr Data |
Addr Data |
Addr Data |
Addr Data |
Read/Reset |
1 |
X |
F0 |
|
|
|
|
|
|
|
|
|
|
3 |
555 |
AA |
2AA |
55 |
X |
F0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
Auto Select |
3 |
555 |
AA |
2AA |
55 |
555 |
90 |
|
|
|
|
|
|
Program |
4 |
555 |
AA |
2AA |
55 |
555 |
A0 |
PA |
PD |
|
|
|
|
Chip Erase |
6 |
555 |
AA |
2AA |
55 |
555 |
80 |
555 |
AA |
2AA |
55 |
555 |
10 |
Block Erase |
6+ |
555 |
AA |
2AA |
55 |
555 |
80 |
555 |
AA |
2AA |
55 |
BA |
30 |
Erase Suspend |
1 |
X |
B0 |
|
|
|
|
|
|
|
|
|
|
Erase Resume |
1 |
X |
30 |
|
|
|
|
|
|
|
|
|
|
Table 5B. Commands, 8-bit mode, BYTE = VIL
Command
Length
|
|
Bus Write Operations |
|
|
|
1st |
2nd |
3rd |
4th |
5th |
6th |
Addr Data |
Addr Data |
Addr Data |
Addr Data |
Addr Data |
Addr Data |
Read/Reset |
1 |
X |
F0 |
|
|
|
|
|
|
|
|
|
|
3 |
AAA |
AA |
555 |
55 |
X |
F0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
Auto Select |
3 |
AAA |
AA |
555 |
55 |
AAA |
90 |
|
|
|
|
|
|
Program |
4 |
AAA |
AA |
555 |
55 |
AAA |
A0 |
PA |
PD |
|
|
|
|
Chip Erase |
6 |
AAA |
AA |
555 |
55 |
AAA |
80 |
AAA |
AA |
555 |
55 |
AAA |
10 |
Block Erase |
6+ |
AAA |
AA |
555 |
55 |
AAA |
80 |
AAA |
AA |
555 |
55 |
BA |
30 |
Erase Suspend |
1 |
X |
B0 |
|
|
|
|
|
|
|
|
|
|
Erase Resume |
1 |
X |
30 |
|
|
|
|
|
|
|
|
|
|
Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A±1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don't Care. DQ15A±1 is A±1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until the Timeout Bit is set.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode.
quires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a bit set at '0' back to '1' and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
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