SGS Thomson Microelectronics M29F010B70K1, M29F010B45N1, M29F010B45K1, M29F010B, M29F010B70P1 Datasheet

M29F010B

1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory

PRELIMINARY DATA

■SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 45ns

■PROGRAMMING TIME

±8μs per Byte typical

■8 UNIFORM 16 Kbytes MEMORY BLOCKS

■PROGRAM/ERASE CONTROLLER

±Embedded Byte Program algorithm

±Embedded Multi-Block/Chip Erase algorithm

±Status Register Polling and Toggle Bits

■ERASE SUSPEND and RESUME MODES

±Read and Program another Block during Erase Suspend

■UNLOCK BYPASS PROGRAM COMMAND

±Faster Production/Batch Programming

■LOW POWER CONSUMPTION

±Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■20 YEARS DATA RETENTION

±Defectivity below 1 ppm/year

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: 20h

PLCC32 (K)	TSOP32 (N)
	8 x 20mm

32

1

PDIP32 (P)

Figure 1. Logic Diagram

	VCC
17	8
A0-A16	DQ0-DQ7
W	M29F010B
E
G

VSS

AI02735

July 1999

1/20

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F010B

Figure 2A. PLCC Connections

	A12	A15	A16	NC	CC	W	NC
					V
A7				1	32			A14
A6								A13
A5								A8
A4								A9
A3	9		M29F010B				25	A11
A2								G
A1								A10
A0								E
DQ0				17				DQ7
	DQ1	DQ2			DQ4	DQ5	DQ6
			V	DQ3
			SS
								AI02737

Figure 2B. TSOP Connections

A11	1	32	G
A9			A10
A8			E
A13			DQ7
A14			DQ6
NC			DQ5
W			DQ4
VCC	8	M29F010B 25	DQ3
NC	9	24	VSS
A16			DQ2
A15			DQ1
A12			DQ0
A7			A0
A6			A1
A5			A2
A4	16	17	A3
		AI02738

Figure 2C. PDIP Connections

NC	1		32	VCC
A16	2		31	W
A15	3		30	NC
A12	4		29	A14
A7	5		28	A13
A6	6		27	A8
A5	7		26	A9
A4	8	M29F010B	25	A11
A3	9		24	G
A2	10		23	A10
A1	11		22	E
A0	12		21	DQ7
DQ0	13		20	DQ6
DQ1	14		19	DQ5
DQ2	15		18	DQ4
VSS	16		17	DQ3
		AI02736

Table 1. Signal Names

A0-A16	Address Inputs
DQ0-DQ7	Data Inputs/Outputs
E	Chip Enable
G	Output Enable
W	Write Enable
VCC	Supply Voltage
VSS	Ground
NC	Not Connected Internally

SUMMARY DESCRIPTION

The M29F010B is a 1 Mbit (128Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve

2/20

			M29F010B
Table 2. Absolute Maximum Ratings (1)
Symbol	Parameter	Value	Unit
	Ambient Operating Temperature (Temperature Range Option 1)	0 to 70	°C
T	Ambient Operating Temperature (Temperature Range Option 6)	±40 to 85	°
A			C
	Ambient Operating Temperature (Temperature Range Option 3)	±40 to 125	°C
T	Temperature Under Bias	±50 to 125	°
BIAS			C
T	Storage Temperature	±65 to 150	°
STG			C
VIO (2)	Input or Output Voltage	±0.6 to 6	V
VCC	Supply Voltage	±0.6 to 6	V
VID	Identification Voltage	±0.6 to 13.5	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to ±2V during transition and for less than 20ns during transitions.

valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in PLCC32, TSOP32 (8 x 20mm) and PDIP32 packages. Access times of 45ns, 70ns, 90ns and 120ns are available. The memory is supplied with all the bits erased (set to '1').

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A16). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.

VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1μF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4.

Vss Ground. The VSS Ground is the reference for all voltage measurements.

3/20

M29F010B

Table 3. Block Addresses

Size (Kbytes)	Address Range
16	1C000h-1FFFFh
16	18000h-1BFFFh
16	14000h-17FFFh
16	10000h-13FFFh
16	0C000h-0FFFFh
16	08000h-0BFFFh
16	04000h-07FFFh
16	00000h-03FFFh

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4, for Program or Erase operations until the operation completes.

4/20

Table 4. Bus Operations

	Operation	E	G	W
	Bus Read	VIL	VIL	VIH
	Bus Write	VIL	VIH	VIL
	Output Disable	X	VIH	VIH
	Standby	VIH	X	X
	Read Manufacturer	VIL	VIL	VIH
	Code
	Read Device Code	VIL	VIL	VIH
	Note: X = VIL or VIH.

Address Inpu ts

Cell Address

Command Address

X

X

A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH

M29F010B

Data Inputs/Outpu ts

Data Output

Data Input

Hi-Z

Hi-Z

20h

20h

Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Blocks Unprotection operations must only be performed on programming equipment. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

5/20

M29F010B

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10μs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 20h.

The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F010B is 20h.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A14-A16 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on the Data Inputs/Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal

state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at '0' back to '1' and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.

6/20