SGS Thomson Microelectronics M27C256B-15F1, M27C256B-12C1TR, M27C256B-12C1, M27C256B-12B6, M27C256B-12B3 Datasheet

M27C256B

256 Kbit (32Kb x 8) UV EPROM and OTP EPROM

■5V ± 10% SUPPLY VOLTAGE in READ OPERATION

■ACCESS TIME: 45ns

■LOW POWER CONSUMPTION:

±Active Current 30mA at 5MHz

±Standby Current 100μA

■PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■PROGRAMMING TIME: 100μs/word

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: 8Dh

DESCRIPTION

The M27C256B is a 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768 by 8 bits.

The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27C256B is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.

28	28
1	1
FDIP28W (F)	PDIP28 (B)

PLCC32 (C)	TSOP28 (N)
	8 x 13.4 mm

Figure 1. Logic Diagram

VCC	VPP
15	8
A0-A14	Q0-Q7

E M27C256B

G

VSS

AI00755B

April 2001

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M27C256B

Figure 2A. DIP Connections

VPP	1	28	VCC
A12	2	27	A14
A7	3	26	A13
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	22	G
A2	8	M27C256B	A10
		21
A1	9	20	E
A0	10	19	Q7
Q0	11	18	Q6
Q1	12	17	Q5
Q2	13	16	Q4
VSS	14	15	Q3
		AI00756

Figure 2B. LCC Connections

	A7	A12	PP	DU	CC	A14	A13
			V		V
A6				1	32		A8
A5							A9
A4							A11
A3							NC
A2	9	M27C256B					25 G
A1							A10
A0							E
NC							Q7
Q0				17			Q6
			SS
	Q1	Q2		DU	Q3	Q4	Q5
			V

AI00757

Figure 2C. TSOP Connections				Table 1. Signal Names
				A0-A14	Address Inputs
				Q0-Q7	Data Outputs
G	22	21	A10	E	Chip Enable
A11			E	G	Output Enable
A9			Q7
A8			Q6	VPP	Program Supply
A13			Q5	VCC
A14			Q4		Supply Voltage
VCC	28	15	Q3	VSS	Ground
VPP		M27C256B	VSS
	1	14
A12			Q2	NC	Not Connected Internally
A7			Q1	DU	Don't Use
A6			Q0
A5			A0
A4			A1
A3	7	8	A2
		AI00614B

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M27C256B

Table 2. Absolute Maximum Ratings (1)

Symbol

TA

TBIAS

TSTG

VIO (2)

VCC

VA9 (2)

VPP

Parameter	Value	Unit
Ambient Operating Temperature (3)	±40 to 125	°C
Temperature Under Bias	±50 to 125	°C
Storage Temperature	±65 to 150	°C
Input or Output Voltage (except A9)	±2 to 7	V
Supply Voltage	±2 to 7	V
A9 Voltage	±2 to 13.5	V
Program Supply Voltage	±2 to 14	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3.Depends on range.

Table 3. Operating Modes

Mode	E	G	A9	VPP	Q7-Q0
Read	VIL	VIL	X	VCC	Data Out
Output Disable	VIL	VIH	X	VCC	Hi-Z
Program	VIL Pulse	VIH	X	VPP	Data In
Verify	VIH	VIL	X	VPP	Data Out
Program Inhibit	VIH	VIH	X	VPP	Hi-Z
Standby	VIH	X	X	VCC	Hi-Z
Electronic Signature	VIL	VIL	VID	VCC	Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier	A0	Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0	Hex Data
Manufacturer's Code	VIL	0	0	1	0	0	0	0	0	20h
Device Code	VIH	1	0	0	0	1	1	0	1	8Dh

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M27C256B

Table 5. AC Measurement Conditions

	High Speed	Standard
Input Rise and Fall Times	≤ 10ns	≤ 20ns
Input Pulse Voltages	0 to 3V	0.4V to 2.4V
Input and Output Timing Ref. Voltages	1.5V	0.8V and 2V

Figure 3. AC Testing Input Output Waveform	Figure 4. AC Testing Load Circuit
	1.3V
High Speed
3V	1N914
1.5V
0V	3.3kΩ
	DEVICE
Standard	UNDER	OUT
	TEST
2.4V	CL
2.0V
0.8V
0.4V
AI01822	CL = 30pF for High Speed
	CL = 100pF for Standard
	CL includes JIG capacitance	AI01823B

Table 6. Capacitance (1) (T = 25 °C, f = 1 MHz)
	A
Symbol	Parameter	Test Condit ion	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		6	pF
COUT	Output Capacitance	VOUT = 0V		12	pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

The operating modes of the M27C256B are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature.

Read Mode

The M27C256B has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the ad-

dresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

Standby Mode

The M27C256B has a standby mode which reduces the supply current from 30mA to 100μA. The M27C256B is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

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M27C256B

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70°C, ±40 to 85°C, ±40 to 105°C or ±40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

	ILI	Input Leakage Current
	ILO	Output Leakage Current
	ICC	Supply Current
	ICC1	Supply Current (Standby) TTL
	ICC2	Supply Current (Standby) CMOS
	IPP	Program Current
	VIL	Input Low Voltage
	(2)	Input High Voltage
	VIH
	VOL	Output Low Voltage
	VOH	Output High Voltage TTL
		Output High Voltage CMOS

0V ≤ VIN ≤ VCC		±10	μA
0V ≤ VOUT ≤ VCC		±10	μA
E = VIL, G = VIL,		30	mA
IOUT = 0mA, f = 5MHz
E = VIH		1	mA
E > VCC ± 0.2V		100	μA
VPP = VCC		100	μA
	±0.3	0.8	V
	2	VCC + 1	V
IOL = 2.1mA		0.4	V
IOH = ±1mA	3.6		V
IOH = ±100μA	VCC ± 0.7V		V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70°C, ±40 to 85°C, ±40 to 105°C or ±40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

									M27C256B
	Symbol		Alt	Parameter	Test Conditio n	-45 (3)		-60		-70		-80		Unit
						Min	Max	Min	Max	Min	Max	Min	Max
		tAVQV	tACC	Address Valid to	E = VIL, G = VIL		45		60		70		80	ns
				Output Valid
		tELQV	tCE	Chip Enable Low to	G = VIL		45		60		70		80	ns
				Output Valid
		tGLQV	tOE	Output Enable Low to	E = VIL		25		30		35		40	ns
				Output Valid
	tEHQZ (2)		tDF	Chip Enable High to	G = VIL	0	25	0	30	0	30	0	30	ns
				Output Hi-Z
	t	(2)	tDF	Output Enable High	E = VIL	0	25	0	30	0	30	0	30	ns
				to Output Hi-Z
	GHQZ
		tAXQX	tOH	Address Transition to	E = VIL, G = VIL	0		0		0		0		ns
				Output Transition

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2.Sampled only, not 100% tested.

3.Speed obtained with High Speed AC measurement conditions.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a.the lowest possible memory power dissipation,

b.complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.

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