SGS Thomson Microelectronics M24C02-S, M24C04-S, M24C08-S, M24C02-L, M24C01-S Datasheet

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M24C16, M24C08

M24C04, M24C02, M24C01

16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM

FEATURES SUMMARY

■Two Wire I2C Serial Interface Supports 400 kHz Protocol

■Single Supply Voltage:

–4.5V to 5.5V for M24Cxx

–2.5V to 5.5V for M24Cxx-W

–2.2V to 5.5V for M24Cxx-L

–1.8V to 5.5V for M24Cxx-R

■Write Control Input

■BYTE and PAGE WRITE (up to 16 Bytes)

■RANDOM and SEQUENTIAL READ Modes

■Self-Timed Programming Cycle

■Automatic Address Incrementing

■Enhanced ESD/Latch-Up Behavior

■More than 1 Million Erase/Write Cycles

■More than 40 Year Data Retention

Figure 1. Packages

PDIP8 (BN)

SO8 (MN) 150 mil width

TSSOP8 (DW) 169 mil width

TSSOP8 (DS) 3x3mm² body size (MSOP)

May 2003

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M24C16, M24C08, M24C04, M24C02, M24C01

SUMMARY DESCRIPTION

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02, M24C01).

Figure 2. Logic Diagram

VCC

E0-E2

SDA

SCL M24Cxx

VSS

AI02033

ter. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Table 1. Signal Names

	E0, E1, E2		Chip Enable

	SDA		Serial Data

	SCL		Serial Clock

			Write Control
	WC		Write Control

	VCC		Supply Voltage
	VSS		Ground

Power On Reset: VCC Lock-Out Write Protect

These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus mas-

Figure 3. DIP, SO and TSSOP Connections

In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal.

		M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0	1		8		VCC


NC / NC / E1 / E1 / E1	2		7
					WC

NC / E2 / E2 / E2 / E2	3		6		SCL

VSS		4	5	SDA

AI02034E

Note: 1. NC = Not Connected

2. See page 20 (onwards) for package dimensions, and how to identify pin-1.

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M24C16, M24C08, M24C04, M24C02, M24C01

SIGNAL DESCRIPTION Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to VCC or VSS, to establish the Device Select Code.

Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed.

When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.

Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

Maximum RP value (kΩ)

VCC

SDA

MASTER

CBUS

fc = 100kHz

SCL

fc = 400kHz

CBUS

100

1000

CBUS (pF)

AI01665

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SGS Thomson Microelectronics M24C02-S, M24C04-S, M24C08-S, M24C02-L, M24C01-S Datasheet

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 5. I2C Bus Protocol

SCL

SDA

START

SDA

STOP

Input

Change

Condition

SCL

SDA

MSB

ACK

START

Condition

SCL

SDA

MSB

ACK

STOP

Condition

AI00792B

Table 2. Device Select Code

Device Type Identifier1

Chip Enable2,3

M24C01 Select Code

M24C02 Select Code

M24C04 Select Code

M24C08 Select Code

M24C16 Select Code

A10

Note: 1. The most significant bit, b7, is sent first.

2.E0, E1 and E2 are compared against the respective external pins on the memory device.

3.A10, A9 and A8 represent most significant bits of the address.

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M24C16, M24C08, M24C04, M24C02, M24C01

DEVICE OPERATION

The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA)

Table 3. Operating Modes

must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.

Memory Addressing

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 (on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4- bit Device Type Identifier is 1010b.

When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.

Devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not available for devices that need to use address line A9, and E2 is not available for devices that need to use address line A10 (see Figure 3 and Table 2 for details). Using the E0, E1 and E2 inputs pins, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 device can be connected to one I2C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used).

Mode

bit

Bytes

Initial Sequence

Current Address Read

= 1

START, Device Select, RW

= 0, Address

Random Address Read

START, Device Select, RW

= 1

reSTART, Device Select, RW

Sequential Read

³ 1

Similar to Current or Random Address Read

Byte Write

VIL

= 0

START, Device Select, RW

Page Write

VIL

£ 16

= 0

START, Device Select, RW

Note: 1. X = VIH or VIL.

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M24C16, M24C08, M24C04, M24C02, M24C01

Figure 6. Write Mode Sequences with WC=1 (data write inhibited)

Byte Write

START

	ACK	ACK
DEV SEL	BYTE ADDR
	R/W

NO ACK

DATA IN

STOP

ACK

NO ACK

Page Write

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

DATA IN 3

START

WC (cont'd)

Page Write (cont'd)

R/W

NO ACK		NO ACK

	DATA IN N




			STOP

AI02803C

Write Operations

Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 7, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte.

When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests.

Byte Write

After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from

the Start condition until the end of the address byte), the device replies to the data byte with NoAck, as shown in Figure 6, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7.

Page Write

The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘rollover’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.

The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from the Start

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M24C16, M24C08, M24C04, M24C02, M24C01

condition until the end of the address byte), the device replies to the data bytes with NoAck, as shown in Figure 6, and the locations are not modified. After each byte is transferred, the internal

byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.

Figure 7. Write Mode Sequences with WC=0 (data write enabled)

BYTE WRITE

START

	ACK		ACK	ACK
DEV SEL		BYTE ADDR		DATA IN
DEV SEL		BYTE ADDR		DATA IN
				STOP
	R/W			STOP
	R/W

ACK

PAGE WRITE

START

WC (cont'd)

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

DATA IN 3

R/W

ACK ACK




PAGE WRITE						DATA IN N
(cont'd)
(cont'd)

STOP

AI02804B

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M24C16, M24C08, M24C04, M24C02, M24C01

Figure 8. Write Cycle Polling Flowchart using ACK

First byte of instruction with RW = 0 already decoded by the device

WRITE Cycle

in Progress

START Condition
DEVICE SELECT
	with RW = 0
NO	ACK
	Returned
	YES

Operation is

YES

Addressing the

Memory

Send Address

ReSTART

and Receive ACK

START

YES

STOP

Condition

DATA for the		DEVICE SELECT
WRITE Operation		with RW = 1

Continue the		Continue the
WRITE Operation	Random READ Operation		AI01847C

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Tables 19 to 21, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 8, is:

– Initial condition: a Write cycle is in progress.

–Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).

–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

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