SGS Thomson Microelectronics M27256-F6, M27256-F1, M27256-4F6, M27256-3F6, M27256-1F6 Datasheet

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FA ST ACCESS TIME: 170ns EXTENDED TEMPERATURE RANGE SINGLE 5V SUPPLY VOLTAGE LOW STANDBY CURRE NT: 40mA max

M27256

NMOS 256K (32K x 8) UV EPROM

TTL COMPATIBLE DURING READ and PROGRAM

FAST PROGRAMMING ALGORITHM ELECTRONIC SIGNATURE PROGRAMMING VOLTAGE: 12V

DESCRIPTION

The M27256 is a 262,144 bit UV erasable and electrically programmable memory EPROM. It is organized as 32.768 words by 8 bits.

The M27256 is housed in a 28 pin Window Ceramic Frit-Seal Dual-in-Line pac kage. The transparent lid allows the user to expose the chip t o ultraviolet light to erase the bit patt ern. A new pattern can then be written to the devic e by following t he programmi ng procedure.

FDIP28W (F)

Figure 1. Logic Diag ra m

A0-A14 Q0-Q7

T able 1. Signal Names

A0 - A14 Address Inputs Q0 - Q7 Data Outputs E Chip Enable G Output Enable V

March 1995 1/10

Program Supply Supply Voltage Ground

M27256

AI00767B

M27256

Tab le 2. Absol ute Maxim u m Ratin gs

Symbol Parameter Value Unit

BIAS

STG

Note: Except for the rating "Operating T emperature R ange", stresses above those lis ted in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and opera tion of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rati ng conditions for extended periods may affect device reliabil ity. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

Ambient Operating T empera ture grade 1

grade 6

Temperature Under Bias grade 1

grade 6 Storage Temperature –65 to 125 °C Input or Output Voltages –0.6 to 6.25 V Supply Voltage –0.6 to 6.25 V VA9 Voltage –0.6 to 13.5 V Program Supply –0.6 to 14 V

0 to 70

–40 to 85 –10 to 80

–50 to 95

°C

Figure 2. DIP Pin Connections

A12

A7 A6 A5 A4 A3 A2 A1 A0

Q2 SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

M27256

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI00768

A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

DEVICE OPERATION

The eight modes of operations of the M27256 are listed in the Operating Modes Table. A single 5V power supply is required in the read mode. All inputs are TTL lev els except for V

and 12V on A9

for Electronic Signature.

Read Mode

The M27256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (

E) is the power control and should be used for device selection. Output Enable (

G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are s table, addres s ac ces s time (t is equal to the delay from

E to output (t

ELQV

AVQV

). Data is available at the outputs after the falling edge of G, assuming that E has been low and the addresses have been stable for at least t

AVQV-tGLQV

Stand by Mod e

The M27256 has a standby mode which reduces the maximum active power current from 100mA to 40mA. The M27256 is placed in the standby mode by applying a TTL high signal to the

E input. Whe n in the standby mode, the outputs are in a high impedance state, independent of the

G input.

Two Line Output Control

Because EPROM s are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete ass urance that output bus contention

will not occur .

)

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M27256

DEVICE OPER ATION (cont’d)

For the most efficient us e of these two control lines, E should be decoded and used as the primary device selecting function, while

G should be made a common connection to all devices in the array and connected to the

READ line from the system

control bus. This ensures that all deselected memory devices

are in their low power standby mode and that the output pins are only active when data is requi red from a particular memory device.

System Considerati ons

The power switching characteristics of fast EPROMs require careful decoupling of the devices. The supply current, I

, has three segments that

are of interest to t he system designer : the s tandby current level, the active c urrent level, and transient current peaks that are produced by the falling and rising edges of

E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 1µF ceramic capacitor be used on every device between V

and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a

4.7µF bulk electrolytic capacitors should be used between V

and VSS for every eight devices. The

bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB trac es.

Programmain

When delivered, (and after each erasure for UV EPROM), all bits of the M27256 ar e in the “1" state. Data is introduced by selectively programming ”0s" into the desired bit locations. Alth ough only “0s” will be programmed, both “1s” and “0s” can be present in the data word. The only way to change a “0" to a ”1" is by ultraviolet light erasure. The M27256 is in the programming mode when V

12.5V and

E is at TTL low. The data to be pro-

input is at

grammed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

Fast Programmi ng Al gor ithm

Fast Programming Algorithm rapidly programs M27256 EPROMs using an efficient and reliable method suited to the production programming environment. Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. A flowchart of the M27256 Fast Programm ing A lgorithm is shown on the Flowchart. The Fast Programming Algorithm utilizes two different pulse types : initial and overprogram. The duration of the initial

E pulse(s) is 1ms, which will then be followed by a longer overprogram pulse of length 3ms by n (n is equal to the number of the initial one millisecond pulses applied

Table 3. Operating Modes

Mode E GA9VPPQ0 - Q7

Read V Output Disable V Program V Verify V Optional Verify V Program Inhibit V Standby V Electronic Signature V

Note: X = VIH or VIL, VID = 12V ± 0.5%.

Pulse V

XXVCCHi-Z

XVCCData Out XVCCHi-Z XVPPData In XVPPData Out XVPPData Out XVPPHi-Z

T ab le 4. Electron ic Sig natu r e

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code V Device Code V

00100000 20h 00000100 04h

Codes

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