SGS Thomson Microelectronics LNBP20PD-TR, LNBP12SP-TR, LNBP11SP-TR, LNBP10SP-TR, LNBP16SP-TR Datasheet

LNBP10 SERIES

LNBP20

LNBP SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE)

■COMPLETE INTERFACE FOR TWO LNBs REMOTE SUPPLY AND CONTROL

■LNB SELECTION AND STAND-BY FUNCTION

■BUILT-IN TONE OSCILLATOR FACTORY TRIMMED AT 22KHz

■FAST OSCILLATOR START-UP FACILITATES DiSEqC ENCODING

■TWO SUPPLY INPUTS FOR LOWEST DISSIPATION

■BYPASS FUNCTION FOR SLAVE OPERATION

■LNB SHORT CIRCUIT PROTECTION AND DIAGNOSTIC

■AUXILIARY MODULATION INPUT EXTENDS FLEXIBILITY

■CABLE LENGTH COMPENSATION

■INTERNAL OVER TEMPERATURE PROTECTION

■BACKWARD CURRENT PROTECTION

DESCRIPTION

Intended for analog and digital satellite receivers, the LNBP is a monolithic linear voltage regulator, assembled in Multiwatt-15, PowerSO-20 and PowerSO-10, specifically designed to provide the powering voltages and the interfacing signals to the LNB downconverter situated in the antenna via the coaxial cable. Since most satellite receivers have two antenna ports, the output voltage of the regulator is available at one of two logic-selectable output pins (LNBA, LNBB). When the IC is powered and put in Stand-by (EN pin LOW), both regulator outputs are disabled to allow the antenna downconverters to be supplied/ controlled by others satellite receivers sharing the same coaxial lines. In this occurrence the device will limit at 3 mA (max) the backward current that could flow from LNBA and LNBB output pins to GND.

For slave operation in single dish, dual receiver systems, the bypass function is implemented by an electronic switch between the Master Input pin (MI) and the LNBA pin, thus leaving all LNB powering and control functions to the Master Receiver. This electronic switch is closed when the device is powered and EN pin is LOW.

Multiwatt-15

	10
	1
Power SO-20	PowerSO-10

The regulator outputs can be logic controlled to be 13 or 18 V (typ.) by mean of the VSEL pin for remote controlling of LNBs. Additionally, it is possible to increment by 1V (typ.) the selected voltage value to compensate the excess voltage drop along the coaxial cable (LLC pin HIGH).

In order to reduce the power dissipation of the device when the lowest output voltage is selected, the regulator has two Supply Input pins VCC1 and VCC2. They must be powered respectively at 16V (min) and 23V (min), and an internal switch automatically will select the suitable supply pin according to the selected output voltage. If adequate heatsink is provided and higher power losses are acceptable, both supply pins can be powered by the same 23V source without affecting any other circuit performance.

The ENT (Tone Enable) pin activates the internal oscillator so that the DC output is modulated by a ±0.3 V, 22KHz (typ.) square wave. This internal oscillator is factory trimmed within a tolerance of ±2KHz, thus no further adjustments neither external components are required.

A burst coding of the 22KHz tone can be accomplished thanks to the fast response of the ENT input and the prompt oscillator start-up. This helps designers who want to implement the DiSEqC protocols (*).

In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation

June 2003

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LNBP10 SERIES - LNBP20

input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. When external modulation is not used, the relevant pin can be left open.

Two pins are dedicated to the overcurrent protection/monitoring: CEXT and OLF. The overcurrent protection circuit works dynamically: as soon as an overload is detected in either LNB output, the output is shut-down for a time toff determined by the capacitor connected between CEXT and GND. Simultaneously the OLF pin, that is an open collector diagnostic output flag, from HIGH IMPEDANCE state goes LOW.

After the time has elapsed, the output is resumed for a time ton=1/15toff (typ.) and OLF goes in HIGH

IMPEDANCE. If the overload is still present, the protection circuit will cycle again through toff and ton until the overload is removed. Typical ton+toff value is 1200ms when a 4.7μF external capacitor is used.

This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up even with highly capacitive loads on LNB outputs.

The device is packaged in Multiwatt15 for thru-holes mounting and in PowerSO-20 for surface mounting. When a limited functionality in a smaller package matches design needs, a range of cost-effective PowerSO-10 solutions is also offered. All versions have built-in thermal protection against overheating damage.

(*): External components are needed to comply to level 2.x and above (bidirectional) DiSEqC bus hardware requirements. DiSEqC is a trademark or EUTELSAT.

ORDERING CODES

TYPE	Multiwatt-15	PowerSO-20	PowerSO-10
LNBP10			LNBP10SP-TR (*)
LNBP11			LNBP11SP-TR (*)
LNBP12			LNBP12SP-TR (*)
LNBP13			LNBP13SP-TR (*)
LNBP14			LNBP14SP-TR (*)
LNBP15			LNBP15SP-TR (*)
LNBP16			LNBP16SP-TR (*)
LNBP20	LNBP20CR	LNBP20PD-TR

(*) Available on request

PIN CONFIGUARATION (top view)

Multiwatt-15	PowerSo-20	PowerSO-10
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LNBP10 SERIES - LNBP20

TABLE A: PIN CONFIGURATIONS

	SYMBOL	NAME	FUNCTION		PIN NUMBER vs SALES TYPE (LNBP)
				20CR	20PD	10SP	11SP	12SP	13SP	14SP	15SP	16SP
	VCC1	Supply Input 1	15V to 25V supply. It is	1	2	1	1	1		1	1	1
			automatically selected
			when VOUT= 13 or 14V
	VCC2	Supply Input 2	22V to 25V supply. It is	2	3	2	2	2	2	2	2	2
			automatically selected
			when VOUT= 18 or 19V
	LNBA	Output Port	See truth table voltage	3	4	3	3	3	3	3	3	3
			and port selection. In
			stand-by mode this port
			is powered by the MI pin
			via the internal Bypass
			Switch
	VSEL	Output Voltage	Logic control input: see	4	5	4	4	4	4	4	4	4
		Selection:13 or	truth table
		18V (typ)
	EN	Port Enable	Logic control input: see	5	6	5	5	5	5	5	5	5
			truth table
	OSEL	Port Selection	Logic control input: see	7	7	9	NA	NA	NA	NA	NA	NA
			truth table
	GND	Ground	Circuit Ground. It is	8	1	6	6		6	6	6	6
			internally connected to		10
			the die frame		11
					20
	ENT	22KHz Tone	Logic control input: see	9	13	7	7	7	7	7	7	7
		Enable	truth table
	CEXT	External	Timing Capacitor used	10	14	8	8	8	8	8	8	8
		Capacitor	by the Dynamic
			Overload protection.
			Typical application is
			4.7μF for a 1200ms
			cycle
	EXTM	External	External Modulation	11	15	NA	NA	NA	9	NA	9	9
		Modulator	Input. Needs DC
			decoupling to the AC
			source. if not used, can
			be left open.
	LLC	Line Length	Logic control input: see	12	16	NA	NA	9	NA	9	NA	10
		Compens.	truth table
		(1V typ)
	OLF	Over Load	Logic output (open	13	17	NA	9	NA	NA	10	10	NA
		Flag	collector). Normally in
			HIGH IMPEDANCE,
			goes LOW when current
			or thermal overload
			occurs
	MI	Master Input	In stand-by mode, the	14	18	NA	10	10	10	NA	NA	NA
			voltage on MI is routed
			to LNBA pin. Can be left
			open if bypass function
			is not needed
	LNBB	Output Port	See truth tables for	15	19	10	NA	NA	NA	NA	NA	NA
			voltage and port
			selection
	NOTE: the limited pin availability of the PowerSO-10 package leads to drop some functions.
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LNBP10 SERIES - LNBP20

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter²	Value	Unit
VI	DC Input Voltage (VCC1, VCC2, MI)	28	V
IO	Output Current (LNBA, LNBB)	Internally Limited	mA
VI	Logic Input Voltage (ENT, EN OSEL, VSEL, LLC)	-0.5 to 7	V
ISW	Bypass Switch Current	900	mA
PD	Power Dissipation at Tcase < 85°C	14	W
Tstg	Storage Temperature Range	-40 to +150	°C
Top	Operating Junction Temperature Range	-40 to +125	°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

THERMAL DATA

Symbol	Parameter	Value	Unit
Rthj-case	Thermal Resistance Junction-case	2	°C/W

LOGIC CONTROLS TRUTH TABLE

CONTROL I/O		PIN NAME		L	H
	OUT		OLF	IOUT > IOMAX or Tj > 150°C	I OUT < IOMAX
	IN		ENT	22KHz tone OFF	22KHz tone ON
	IN		EN	See Table Below	See Table Below
	IN		OSEL	See Table Below	See Table Below
	IN		VSEL	See Table Below	See Table Below
	IN		LLC	See Table Below	See Table Below
EN	OSEL	VSEL	LLCO	VLNBA	VLNBB
L	X	X	X	VMI - 0.4V (typ.)	Disabled
H	L	L	L	13V (typ.)	Disabled
H	L	H	L	18V (typ.)	Disabled
H	L	L	H	14V (typ.)	Disabled
H	L	H	H	19V (typ.)	Disabled
H	H	L	L	Disabled	13V (typ.)
H	H	H	L	Disabled	18V (typ.)
H	H	L	H	Disabled	14V (typ.)
H	H	H	H	Disabled	19V (typ.)

NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ)

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LNBP10 SERIES - LNBP20

BLOCK DIAGRAM

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LNBP10 SERIES - LNBP20

ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (TJ = 0 to 85°C, CI = 0.22μF, CO =0.1μF, EN=H, ENT=L, LLC=L, VIN1=16V, VIN2=23V IOUT=50mA, unless otherwise specified.)

Symbol	Parameter		Test Conditions				Min.	Typ.	Max.	Unit
VIN1	VCC1 Supply Voltage	IO = 500 mA ENT=H, VSEL=L,				LLC=L	15		25	V
		IO = 500 mA ENT=H, VSEL=L,				LLC=H	16		25	V
VIN2	VCC2 Supply Voltage	IO = 500 mA ENT=H, VSEL=L,				LLC=L	22		25	V
		IO = 500 mA VSEL=L,			LLC=H		23		25	V
VO1	Output Voltage	IO = 500 mA VSEL=L,			LLC=L		17.3	18	18.7	V
		IO = 500 mA ENT=H, VSEL=L,				LLC=H		19		V
VO2	Output Voltage	IO = 500 mA VSEL=L,			LLC=L		12.5	13	13.5	V
		IO = 500 mA ENT=H, VSEL=L,				LLC=H		14		V
VO	Line Regulation	VIN1=15 to 18V		VOUT=13V				4	40	mV
		VIN2=22 to 25V		VOUT=18V				4	40	mV
VO	Load Regulation	VIN1=VIN2=22V		VOUT=13 or 18V				80	180	mV
		IO = 50 to 500mA
SVR	Supply Voltage Rejection	VIN1 = VIN2 = 23 ± 0.5Vac fac = 120 Hz,						45		dB
IMAX	Output Current Limiting						500	650	800	mA
tOFF	Dynamic Overload	Output Shorted		CEXT =4.7μF				1100		ms
	protection OFF Time
tON	Dynamic Overload	Output Shorted		CEXT =4.7μF				tOFF/15		ms
	protection ON Time
fTONE	Tone Frequency	ENT=H					20	22	24	KHz
ATONE	Tone Amplitude	ENT=H					0.55	0.72	0.9	Vpp
DTONE	Tone Duty Cycle	ENT=H					40	50	60	%
tr, tf	Tone Rise and Fall Time	ENT=H					5	10	15	μs
GEXTM	External Modulation Gain	VOUT/ VEXTM,		f = 10Hz to 40KHz				5
VEXTM	External Modulation Input	AC Coupling							400	mVpp
	Voltage
ZEXTM	External Modulation	f = 10Hz to 40KHz						400		Ω
	Impedance
VSW	Bypass Switch Voltage	EN=L,	ISW=300mA,		VCC2-VMI=4V			0.35	0.6	V
	Drop (MI to LNBA)
VOL	Overload Flag Pin Logic	IOL=8mA						0.28	0.5	V
	LOW
IOZ	Overload Flag Pin OFF	VOH = 6V							10	μA
	State Leakage Current
VIL	Control Input Pin Logic								0.8	V
	LOW
VIH	Control Input Pin Logic						2.5			V
	HIGH
IIH	Control Pins Input Current	VIH = 5V						20		μA
ICC	Supply Current	Output Disabled (EN=L)						0.3	1	mA
		ENT=H,	IOUT=500mA					3.1	6	mA
IOBK	Output Backward Current	EN=L	VLNBA = VLNBB = 18V					0.2	3	mA
		VIN1 = VIN2 = 22V or floating
TSHDN	Temperature Shutdown							150		°C
	Threshold

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