SGS Thomson Microelectronics M48T18-150MH1, M48T18-120MH1, M48T18-100PC1, M48T18, M48T18-150PC1 Datasheet

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M48T08

M48T18

64 Kbit (8Kb x 8) TIMEKEEPER®SRAM

INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY

BYTEWIDEä RAM-LIKE CLOCK ACCESS

BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES and SECONDS

TYPICAL CLOCK ACCURACY of ± 1 MINUTE a MONTH, at 25°C

AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION

WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):

– M48T08: 4.5V £ VPFD £ 4.75V

– M48T18: 4.2V £ VPFD £ 4.5V

SOFTWARE CONTROLLED CLOCK CALIBRATION for HIGH ACCURACY APPLICATIONS

SELF-CONTAINED BATTERY and CRYSTAL in the CAPHAT DIP PACKAGE

PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP

(to be Ordered Separately)

SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL

PIN and FUNCTION COMPATIBLE with DS1643 and JEDEC STANDARD 8K x 8 SRAMs

Table 1. Signal Names

	A0-A12					Address Inputs

	DQ0-DQ7					Data Inputs / Outputs

						Power Fail Interrupt (Open Drain)
	INT					Power Fail Interrupt (Open Drain)

						Chip Enable 1
	E1					Chip Enable 1

	E2					Chip Enable 2

						Output Enable
	G					Output Enable

						Write Enable
	W					Write Enable

	VCC					Supply Voltage

	VSS					Ground

SNAPHAT (SH)
Battery/Crystal
	28
28	1
1	PCDIP28 (PC)
	PCDIP28 (PC)
SOH28 (MH)	Battery/Crystal
SOH28 (MH)	CAPHAT

Figure 1. Logic Diagram

	VCC
	13	8
A0-A12		DQ0-DQ7
W
E1	M48T08	INT
E1	M48T18	INT
E2
G

VSS

AI01020

May 1999

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M48T08, M48T18

Figure 2A. DIP Pin Connections

				28
INT		1			VCC
A12		2		27	W
	A7	3		26	E2
	A6	4		25	A8
	A5	5		24	A9
	A4	6		23	A11
	A3	7		22
			M48T08		G
	A2	8	M48T18	21	A10
	A1	9		20	E1
	A0	10		19	DQ7
DQ0		11		18	DQ6
DQ1		12		17	DQ5
DQ2		13		16	DQ4
VSS		14		15	DQ3
			AI01182

Figure 2B. SOIC Pin Connections

		1		28
INT					VCC
A12		2		27	W
	A7	3		26	E2
	A6	4		25	A8
	A5	5		24	A9
	A4	6		23	A11
	A3	7		22
			M48T18		G
	A2	8		21	A10
	A1	9		20
					E1
	A0	10		19	DQ7
DQ0		11		18	DQ6
DQ1		12		17	DQ5
DQ2		13		16	DQ4
VSS		14		15	DQ3
			AI01021B

Table 2. Absolute Maximum Ratings (1)

Symbol	Parameter	Value		Unit

TA	Ambient Operating Temperature	0 to 70		°C

TSTG	Storage Temperature (VCC Off, Oscillator Off)	–40 to	85	°C

(2)	Lead Solder Temperature for 10 seconds	260		°C
TSLD	Lead Solder Temperature for 10 seconds	260		°C
VIO	Input or Output Voltages	–0.3 to	7	V

VCC	Supply Voltage	–0.3 to	7	V

IO	Output Current	20		mA
PD	Power Dissipation	1		W

Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Table 3. Operating Modes

Mode

VCC

DQ0-DQ7

Power

Deselect

VIH

High Z

Standby

4.75V to 5.5V

Deselect

VIL

High Z

Standby

Write

VIL

VIH

VIL

DIN

Active

4.5V to 5.5V

Read

VIL

VIH

VIL

VIH

DOUT

Active

Read

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

High Z

CMOS Standby

Deselect

≤ VSO

High Z

Battery Back-up Mode

Notes: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

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SGS Thomson Microelectronics M48T18-150MH1, M48T18-120MH1, M48T18-100PC1, M48T18, M48T18-150PC1 Datasheet

M48T08, M48T18

Figure 3. Block Diagram

OSCILLATOR AND		8 x 8 BiPORT
CLOCK CHAIN		8 x 8 BiPORT
CLOCK CHAIN		SRAM ARRAY
		SRAM ARRAY
32,768 Hz
CRYSTAL			A0-A12
		POWER
		8184 x 8	DQ0-DQ7
		8184 x 8
LITHIUM		SRAM ARRAY
LITHIUM
CELL			E1
VOLTAGE SENSE		VPFD	E2
	AND	VPFD	W
SWITCHING			W
CIRCUITRY			G
			G
VCC	INT	VSS	AI01333

DESCRIPTION

The M48T08/18 TIMEKEEPER® RAM is an 8K x 8 non-volatile static RAM and real time clock which is pin and functional compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution.

The M48T08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed.

The 28 pin 600mil DIP CAPHATä houses the M48T08/18 silicon with a quartz crystal and a long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.

Table 4. AC Measurement Conditions

Input Rise and Fall Times	≤ 5ns

Input Pulse Voltages	0 to 3V

Input and Output Timing Ref. Voltages	1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 4. AC Testing Load Circuit

1.8kΩ

DEVICE

UNDER OUT TEST

1kΩ

CL = 100pF

CL includes JIG capacitance

AI01019

3/19

M48T08, M48T18

Table 5. Capacitance (1, 2)

(TA = 25 °C, f = 1 MHz )

Symbol	Parameter	Test Condition	Min	Max	Unit

CIN	Input Capacitance	VIN = 0V		10	pF
CIO (3)	Input / Output Capacitance	VOUT = 0V		10	pF

Notes: 1. Effective capacitance measured with power supply at 5V.

2.Sampled only, not 100% tested.

3.Outputs deselected.

Table 6. DC Characteristics

(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Symbol	Parameter				Test Condition			Min	Max	Unit

ILI (1)	Input Leakage Current				0V ≤ VIN ≤ VCC				±1	μA
(1)	Output Leakage Current				0V ≤ VOUT ≤ VCC				±5	μA
ILO	Output Leakage Current				0V ≤ VOUT ≤ VCC				±5	μA
ICC	Supply Current				Outputs open				80	mA

(2)
(2)	Supply Current (Standby) TTL			E1 = VIH, E2 = VIL					3	mA
ICC1	Supply Current (Standby) TTL			E1 = VIH, E2 = VIL					3	mA

(2)	Supply Current (Standby) CMOS				E1		= VCC – 0.2V,		3	mA
ICC2	Supply Current (Standby) CMOS				E2 = VSS + 0.2V				3	mA
					E2 = VSS + 0.2V

VIL(3)	Input Low Voltage							–0.3	0.8	V
VIH	Input High Voltage							2.2	VCC + 0.3	V

VOL	Output Low Voltage					IOL = 2.1mA			0.4	V

	Output Low Voltage		(4)			IOL = 0.5mA			0.4	V
	Output Low Voltage	(INT)	(4)			IOL = 0.5mA			0.4	V

VOH	Output High Voltage					IOH = –1mA		2.4		V

Notes: 1. Outputs Deselected.

2.Measured with Control Bits set as follows: R = ’1’; W, ST, FT = ’0’.

3.Negative spikes of –1V allowed for up to 10ns once per Cycle.

4.The INT pin is Open Drain.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70°C)

Symbol		Parameter	Min	Typ	Max	Unit

VPFD		Power-fail Deselect Voltage (M48T08)	4.5	4.6	4.75	V

VPFD		Power-fail Deselect Voltage (M48T18)	4.2	4.3	4.5	V

VSO		Battery Back-up Switchover Voltage		3.0		V

(2)		Expected Data Retention Time	10			YEARS
tDR		Expected Data Retention Time	10			YEARS
Notes: 1.	All voltages referenced to VSS.
2.	At 25°C

DESCRIPTION (cont’d)

The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28-BR12SH1".

As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T08/18 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.

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Notes: 1. VPFD

M48T08, M48T18

Table 8. Power Down/Up Mode AC Characteristics

(TA = 0 to 70°C)

Symbol						Parameter	Min	Max	Unit

tPD					at VIH or E2 at VIL before Power Down		0		μs
tPD	E1	or		W	at VIH or E2 at VIL before Power Down		0		μs

tF (1)	VPFD (max) to VPFD (min) VCC Fall Time						300		μs
(2)	VPFD (min) to VSO VCC Fall Time						10		μs
tFB	VPFD (min) to VSO VCC Fall Time						10		μs
tR	VPFD(min) to VPFD (max) VCC Rise Time						0		μs

tRB	VSO to VPFD (min) VCC Rise Time						1		μs


tREC	E1	or		W	at VIH or E2 at VIL after Power Up		1		ms
tPFX							10	40	μs
tPFX	INT		Low to Auto Deselect				10	40	μs

(3)									μs
(3)	VPFD (max) to INT High							120
tPFH	VPFD (max) to INT High							120

(max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after VCC passes VPFD (min).

2.VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.

3.INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).

Figure 5. Power Down/Up Mode AC Waveforms

VCC
VPFD (max)
VPFD (min)
VSO
	tF
tPD	tFB
	tPFX
INT
INPUTS	RECOGNIZED
OUTPUTS	VALID

tDR

tRB

DON'T CARE

HIGH-Z

tR
	tPFH
	tREC
NOTE	RECOGNIZED

VALID

(PER CONTROL INPUT)

AI00566

Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD(min). Some systems may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is runn ing.

5/19

M48T08, M48T18

Table 9. Read Mode AC Characteristics

(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

				M48T08 / M48T18
Symbol		Parameter						Unit
Symbol		Parameter	-100			-150		Unit
			-100			-150

			Min		Max	Min	Max

tAVAV	Read Cycle Time		100			150		ns

tAVQV	Address Valid to Output Valid				100		150	ns

tE1LQV	Chip Enable 1 Low to Output Valid				100		150	ns

tE2HQV	Chip Enable 2 High to Output Valid				100		150	ns

tGLQV	Output Enable Low to Output Valid				50		75	ns

tE1LQX	Chip Enable 1	Low to Output Transition	10			10		ns

tE2HQX	Chip Enable 2	High to Output Transition	10			10		ns

tGLQX	Output Enable Low to Output Transition		5			5		ns

tE1HQZ	Chip Enable 1	High to Output Hi-Z			50		75	ns

tE2LQZ	Chip Enable 2	Low to Output Hi-Z			50		75	ns

tGHQZ	Output Enable High to Output Hi-Z				40		60	ns

tAXQX	Address Transition to Output Transition		5			5		ns

Figure 6. Read Mode AC Waveforms
	tAVAV
A0-A12	VALID
tAVQV	tAXQX
tE1LQV	tE1HQZ
E1
tE1LQX
tE2HQV	tE2LQZ
E2
tE2HQX
tGLQV	tGHQZ
G
tGLQX
DQ0-DQ7	VALID
	AI00962
Note: Write Enable (W) = High.

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