SGS Thomson Microelectronics M48Z128Y, M48Z128-85PM1, M48Z128-70PM1, M48Z128-120PM1, M48Z128 Datasheet

M48Z128

M48Z128Y

1 Mbit (128Kb x8) ZEROPOWER SRAM

■INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY

■CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

■10 YEARS of DATA RETENTION in the ABSENCE of POWER

■AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION

■WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):

±M48Z128: 4.50V ≤ VPFD ≤ 4.75V

±M48Z128Y: 4.20V ≤ VPFD ≤ 4.50V

■BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED

■PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 128K x 8 SRAMs

■SURFACE MOUNT CHIP SET PACKAGING INCLUDES a 28-PIN SOIC and a 32-LEAD TSOP (SNAPHAT TOP TO BE ORDERED SEPARATELY)

■SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP WHICH CONTAINS the BATTERY

■SNAPHAT HOUSING (BATTERY) IS REPLACEABLE

Table 1. Signal Names

A0-A16	Address Inputs
DQ0-DQ7	Data Inputs / Outputs
E	Chip Enable
G	Output Enable
W	Write Enable
VCC	Supply Voltage
VSS	Ground
NC	Not Connected Internally

32

1

PMDIP32 (PM)

Module

SNAPHAT (SH)

Battery

	TSOP32	SOH28
	(8 x 20mm)

Surface Mount Chip Set Solution (CS)

Figure 1. Logic Diagram

	VCC
17	8
A0-A16	DQ0-DQ7

W M48Z128

M48Z128Y

E

G

VSS

AI01194

June 2000

1/17

M48Z128, M48Z128Y

Table 2. Absolute Maximum Ratings (1)

Symbol	Parameter			Value	Unit
TA	Ambient Operating Temperature			0 to 70	°C
T	Storage Temperature (V	CC	Off)	±40 to 70	°
STG					C
TBIAS	Temperature Under Bias			±10 to 70	°C
(2)	Lead Solder Temperature for 10 seconds			260	°C
TSLD
VIO	Input or Output Voltages			±0.3 to 7	V
VCC	Supply Voltage			±0.3 to 7	V

Note: 1. Stresses greater than those listed under ºAbsolute Maximum Ratingsº may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below ±0.3V are not allowed on any pin while in the Battery Back-up mode.

Table 3. Operating Modes

Mode

VCC

E

G

W

DQ0-DQ7

Power

Deselect

Write

Read

Read

Deselect

Deselect

Note: 1. X = VIH

4.75V to 5.5V or

4.5V to 5.5V

VSO to VPFD (min)

≤ VSO

VIH	X	X	High Z	Standby
VIL	X	VIL	DIN	Active
VIL	VIL	VIH	DOUT	Active
VIL	VIH	VIH	High Z	Active
X	X	X	High Z	CMOS Standby
X	X	X	High Z	Battery Back-up Mode

or VIL; VSO = Battery Back-up Switchover Voltage.

Figure 2. DIP Connections

NC	1		32	VCC
A16	2		31	A15
A14	3		30	NC
A12	4		29	W
A7	5		28	A13
A6	6		27	A8
A5	7		26	A9
A4	8	M48Z128	25	A11
A3	9	M48Z128Y 24		G
A2	10		23	A10
A1	11		22	E
A0	12		21	DQ7
DQ0	13		20	DQ6
DQ1	14		19	DQ5
DQ2	15		18	DQ4
VSS	16		17	DQ3
		AI01195

DESCRIPTION

The M48Z128/128Y ZEROPOWER RAM is a 128 Kbit x8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution.

The M48Z128/128Y is a non-volatile pin and function equivalent to any JEDEC standard 128K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 32 pin 600mil DIP Module houses the M48Z128/128Y silicon with a long life lithium button cell in a single package.

For surface mount environments ST provides a Chip Set solution consisting of a 28 pin 330mil SOIC NVRAM Supervisor (M40Z300) and a 32 pin TSOP (8 x 20mm) LPSRAM (M68Z128) packages.

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery.

2/17

M48Z128, M48Z128Y

Figure 3. Block Diagram

	VCC		A0-A16
		POWER	DQ0-DQ7
			131,072 x 8
	VOLTAGE SENSE		SRAM ARRAY
E	AND
		E
	SWITCHING
	CIRCUITRY		W
			G

INTERNAL

BATTERY

VSS

AI01196

The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.

The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is ºM4Z28-BRxxSH1º.

The M48Z128/128Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns.

READ MODE

The M48Z128/128Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. Thus, the unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins

within Address Access time (tAVQV) after the last address input signal is stable, providing that the E

and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight threestate Data I/O signals is controlled by E and G. If

the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until

tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for

Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.

3/17

M48Z128, M48Z128Y

Figure 4. Hardware Hookup for SMT Chip Set (1)

THS(2)	VOUT	VCC
SNAPHAT		E2
BATTERY(3)		M68Z128
M40Z300
		DQ0-DQ7
E	E1CON	E
	E2CON
	E3CON
	E4CON	A0-A16
A
	RST
B		W
	BL
VSS		VSS

AI03625

Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z128 at www.st.com.

2.Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z128).

3.SNAPHAT ordered separately.

Table 4. AC Measurement Conditions

Input Rise and Fall Times	≤ 5ns
Input Pulse Voltages	0 to 3V
Input and Output Timing Ref. Voltages	1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 5. AC Testing Load Circuit

	5V
	1.9kΩ
DEVICE
UNDER		OUT
TEST
1kΩ	CL	= 100pF or 5pF

CL includes JIG capacitance

AI01030

4/17

Table 5. Capacitance (1, 2)

(TA = 25 °C, f = 1MHz)

Symbol	Parameter
CIN	Input Capacitance
(3)	Input / Output Capacitance
CIO

Note: 1. Effective capacitance measured with power supply at 5V.

2.Sampled only, not 100% tested.

3.Outputs deselected.

M48Z128, M48Z128Y

Test Condit ion	Min	Max	Unit
VIN = 0V		10	pF
VOUT = 0V		10	pF

Table 6. DC Characteristics

(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Symbol	Parameter	Test Conditio n	Min	Max	Unit
ILI (1)	Input Leakage Current	0V ≤ VIN ≤ VCC		±1	μA
ILO (1)	Output Leakage Current	0V ≤ VOUT ≤ VCC		±1	μA
ICC	Supply Current	E = VIL, Outputs open		105	mA
ICC1	Supply Current (Standby) TTL	E = VIH		7	mA
ICC2	Supply Current (Standby) CMOS	E ≥ VCC ± 0.2V		4	mA
VIL	Input Low Voltage		±0.3	0.8	V
VIH	Input High Voltage		2.2	VCC + 0.3	V
VOL	Output Low Voltage	IOL = 2.1mA		0.4	V
VOH	Output High Voltage	IOH = ±1mA	2.4		V

Note: 1. Outputs deselected.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C)

Symbol		Parameter	Min	Typ	Max	Unit
VPFD		M48Z128	4.5	4.6	4.75	V
		Power-fail Deselect Voltage	4.2	4.3	4.5	V
		M48Z128Y
VSO		Battery Back-up Switchover Voltage		3		V
tDR (2)		Data Retention Time	10			YEARS
Note: 1.	All voltages referenced to VSS.
2.	At 25 °C.

5/17

M48Z128, M48Z128Y

Table 8. Power Down/Up AC Characteristics

(TA = 0 to 70 °C)

Symbol

Parameter

Min

Max

Unit

tF (1)

tFB (2)

tWP

tR

tER

VPFD (max) to VPFD (min) VCC Fall Time	300		μs
VPFD (min) to VSO VCC Fall Time	10		μs
Write Protect Time from VCC = VPFD	40	150	μs
VSO to VPFD (max) VCC Rise Time	0		μs
E Recovery Time	40	120	ms

Note: 1.	VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200μs after VCC pass-
	es VPFD (min).
2.	VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.

Figure 6. Power Down/Up Mode AC Waveforms

VCC

VPFD (max)

VPFD (min)

VSO

tF	tDR	tR
	tFB
tWP		tER

E	RECOGNIZED

DON'T CARE	RECOGNIZED
HIGH-Z

OUTPUTS	VALID	VALID
	(PER CONTROL INPUT)	(PER CONTROL INPUT)
		AI01031

6/17