SGS Thomson Microelectronics M29F160BT90N6, M29F160BT70N1, M29F160BT, M29F160BB90N6, M29F160BB70N1 Datasheet

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M29F160BT

M29F160BB

16 Mbit (2Mb x8 or 1Mb x16, Boot Block) Single Supply Flash Memory

PRELIMINARY DATA

■SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 55ns

■PROGRAMMING TIME

–8µs per Byte/Word typical

■35 MEMORY BLOCKS

–1 Boot Block (Top or Bottom Location)

–2 Parameter and 32 Main Blocks

■PROGRAM/ERASE CONTROLLER

–Embedded Byte/Word Program algorithm

–Embedded Multi-Block/Chip Erase algorithm

–Status Register Polling and Toggle Bits

–Ready/Busy Output Pin

■ERASE SUSPEND and RESUME MODES

–Read and Program another Block during Erase Suspend

■UNLOCK BYPASS PROGRAM COMMAND

–Faster Production/Batch Programming

■TEMPORARY BLOCK UNPROTECTION MODE

■LOW POWER CONSUMPTION

–Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■20 YEARS DATA RETENTION

–Defectivity below 1 ppm/year

■ELECTRONIC SIGNATURE

–Manufacturer Code: 0020h

–Top Device Code M29F160BT: 22CCh

–Bottom Device Code M29F160BB: 224Bh

TSOP48 (N) 12 x 20mm

Figure 1. Logic Diagram

	VCC
20		15
A0-A19		DQ0-DQ14
W		DQ15A–1
E	M29F160BT	BYTE
E	M29F160BB	BYTE
	M29F160BB
G		RB
RP

VSS

AI02920

March 2000

1/22

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F160BT, M29F160BB

Figure 2. TSOP Connections

Table 1. Signal Names

A0-A19

Address Inputs

A15

A16

DQ0-DQ7

Data Inputs/Outputs

A14

BYTE

A13

VSS

DQ8-DQ14

Data Inputs/Outputs

A12

DQ15A–1

Data Input/Output or Address Input

A11

DQ7

A10

DQ14

Chip Enable

DQ6

Output Enable

DQ13

A19

DQ5

Write Enable

DQ12

DQ4

Reset/Block Temporary Unprotect

VCC

M29F160BT

Ready/Busy Output

M29F160BB

DQ11

DQ3

Byte/Word Organization Select

BYTE

DQ10

VCC

Supply Voltage

A18

DQ2

A17

DQ9

VSS

Ground

DQ1

Not Connected Internally

DQ8

DQ0

VSS

AI02921

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

°C

Ambient Operating Temperature (Temperature Range Option 6)

–40 to 85

°C

Ambient Operating Temperature (Temperature Range Option 3)

–40 to 125

°C

TBIAS

Temperature Under Bias

–50 to 125

°C

TSTG

Storage Temperature

–65 to 150

°C

VIO (2)

Input or Output Voltage

–0.6 to 6

VCC

Supply Voltage

–0.6 to 6

VID

Identification Voltage

–0.6 to 13.5

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

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M29F160BT, M29F160BB

SUMMARY DESCRIPTION

The M29F160B is a 16Mbit (2Mb x8 or 1Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in a TSOP48 (12 x 20mm) package and it is supplied with all the bits erased (set to ’1’).

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M29F160BT, M29F160BB

Table 3. Top Boot Block Addresses

M29F160BT

#	Size	Address Range	Address Range
#	(Kbytes)	(x8)	(x16)
	(Kbytes)	(x8)	(x16)

34	16	1FC000h-1FFFFFh	FE000h-FFFFFh

33	8	1FA000h-1FBFFFh	FD000h-FDFFFh

32	8	1F8000h-1F9FFFh	FC000h-FCFFFh

31	32	1F0000h-1F7FFFh	F8000h-FBFFFh

30	64	1E0000h-1EFFFFh	F0000h-F7FFFh

29	64	1D0000h-1DFFFFh	E8000h-EFFFFh

28	64	1C0000h-1CFFFFh	E0000h-E7FFFh

27	64	1B0000h-1BFFFFh	D8000h-DFFFFh

26	64	1A0000h-1AFFFFh	D0000h-D7FFFh

25	64	190000h-19FFFFh	C8000h-CFFFFh

24	64	180000h-18FFFFh	C0000h-C7FFFh

23	64	170000h-17FFFFh	B8000h-BFFFFh

22	64	160000h-16FFFFh	B0000h-B7FFFh

21	64	150000h-15FFFFh	A8000h-AFFFFh

20	64	140000h-14FFFFh	A0000h-A7FFFh

19	64	130000h-13FFFFh	98000h-9FFFFh

18	64	120000h-12FFFFh	90000h-97FFFh

17	64	110000h-11FFFFh	88000h-8FFFFh

16	64	100000h-10FFFFh	80000h-87FFFh

15	64	0F0000h-0FFFFFh	78000h-7FFFFh

14	64	0E0000h-0EFFFFh	70000h-77FFFh

13	64	0D0000h-0DFFFFh	68000h-6FFFFh

12	64	0C0000h-0CFFFFh	60000h-67FFFh

11	64	0B0000h-0BFFFFh	58000h-5FFFFh

10	64	0A0000h-0AFFFFh	50000h-57FFFh

9	64	090000h-09FFFFh	48000h-4FFFFh

8	64	080000h-08FFFFh	40000h-47FFFh

7	64	070000h-07FFFFh	38000h-3FFFFh

6	64	060000h-06FFFFh	30000h-37FFFh

5	64	050000h-05FFFFh	28000h-2FFFFh

4	64	040000h-04FFFFh	20000h-27FFFh

3	64	030000h-03FFFFh	18000h-1FFFFh

2	64	020000h-02FFFFh	10000h-17FFFh

1	64	010000h-01FFFFh	08000h-0FFFFh

0	64	000000h-00FFFFh	00000h-07FFFh

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Table 4. Bottom Boot Block Addresses

M29F160BB

#	Size	Address Range	Address Range
#	(Kbytes)	(x8)	(x16)
	(Kbytes)	(x8)	(x16)

34	64	1F0000h-1FFFFFh	F8000h-FFFFFh

33	64	1E0000h-1EFFFFh	F0000h-F7FFFh

32	64	1D0000h-1DFFFFh	E8000h-EFFFFh

31	64	1C0000h-1CFFFFh	E0000h-E7FFFh

30	64	1B0000h-1BFFFFh	D8000h-DFFFFh

29	64	1A0000h-1AFFFFh	D0000h-D7FFFh

28	64	190000h-19FFFFh	C8000h-CFFFFh

27	64	180000h-18FFFFh	C0000h-C7FFFh

26	64	170000h-17FFFFh	B8000h-BFFFFh

25	64	160000h-16FFFFh	B0000h-B7FFFh

24	64	150000h-15FFFFh	A8000h-AFFFFh

23	64	140000h-14FFFFh	A0000h-A7FFFh

22	64	130000h-13FFFFh	98000h-9FFFFh

21	64	120000h-12FFFFh	90000h-97FFFh

20	64	110000h-11FFFFh	88000h-8FFFFh

19	64	100000h-10FFFFh	80000h-87FFFh

18	64	0F0000h-0FFFFFh	78000h-7FFFFh

17	64	0E0000h-0EFFFFh	70000h-77FFFh

16	64	0D0000h-0DFFFFh	68000h-6FFFFh

15	64	0C0000h-0CFFFFh	60000h-67FFFh

14	64	0B0000h-0BFFFFh	58000h-5FFFFh

13	64	0A0000h-0AFFFFh	50000h-57FFFh

12	64	090000h-09FFFFh	48000h-4FFFFh

11	64	080000h-08FFFFh	40000h-47FFFh

10	64	070000h-07FFFFh	38000h-3FFFFh

9	64	060000h-06FFFFh	30000h-37FFFh

8	64	050000h-05FFFFh	28000h-2FFFFh

7	64	040000h-04FFFFh	20000h-27FFFh

6	64	030000h-03FFFFh	18000h-1FFFFh

5	64	020000h-02FFFFh	10000h-17FFFh

4	64	010000h-01FFFFh	08000h-0FFFFh

3	32	008000h-00FFFFh	04000h-07FFFh

2	8	006000h-007FFFh	03000h-03FFFh

1	8	004000h-005FFFh	02000h-02FFFh

0	16	000000h-003FFFh	00000h-01FFFh

M29F160BT, M29F160BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 17 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure 10, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode.

VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4.

Vss Ground. The VSS Ground is the reference for all voltage measurements.

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M29F160BT, M29F160BB

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 14, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip

Table 5. Bus Operations, BYTE = VIL

Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 15 and 16, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current, ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 13, DC Characteristics.

Address Inputs

Data Inputs/Outputs

Operation

DQ15A–1, A0-A19

DQ14-DQ8

DQ7-DQ0

Bus Read

VIL

VIH

Cell Address

Hi-Z

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Hi-Z

Data Input

Output Disable

VIH

Hi-Z

Standby

VIH

Hi-Z

Read Manufacturer

VIL

VIH

A0 = VIL, A1 = VIL, A9 = VID,

Hi-Z

20h

Code

Others VIL or VIH

Read Device Code

VIL

VIH

A0 = VIH, A1 = VIL, A9 = VID,

Hi-Z

CCh (M29F160BT)

Others VIL or VIH

4Bh (M29F160BB)

Note: X = VIL or VIH.

Table 6. Bus Operations, BYTE = VIH

Address Inputs

Data Inputs/Outputs

Operation

A0-A19

DQ15A–1, DQ14-DQ0

Bus Read

VIL

VIH

Cell Address

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Data Input

Output Disable

VIH

Hi-Z

Standby

VIH

Hi-Z

Read Manufacturer

VIL

VIH

A0 = VIL, A1 = VIL, A9 = VID,

0020h

Code

Others VIL or VIH

Read Device Code

VIL

VIH

A0 = VIH, A1 = VIL, A9 = VID,

22CCh (M29F160BT)

Others VIL or VIH

224Bh (M29F160BB)

Note: X = VIL or VIH.

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M29F160BT, M29F160BB

During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4, for Program or Erase operations until the operation completes.

Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 5 and 6, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or 8- bit mode. See either Table 7, or 8, depending on the configuration that is being used, for a summary of the commands.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10µs to abort. During the abort period no valid data can

be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F160BT is 22CCh and for the M29F160BB is 224Bh.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 9. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

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