SGS Thomson Microelectronics M95640-W, M95640-RMN5T, M95640-RMN5, M95640-RBN5, M95640-R Datasheet

M95640, M95320

M95160, M95080

64/32/16/8 Kbit Serial SPI Bus EEPROM

With High Speed Clock

PRELIMINARY DATA

■SPI Bus Compatible Serial Interface

■Supports Positive Clock SPI Modes

■5 MHz Clock Rate (maximum)

■Single Supply Voltage:

–4.5V to 5.5V for M95xxx

–2.7V to 5.5V for M95xxx-V

–2.5V to 5.5V for M95xxx-W

–1.8V to 3.6V for M95xxx-R

■Status Register

■Hardware and Software Protection of the Status Register

■BYTE and PAGE WRITE (up to 32 Bytes)

■Self-Timed Programming Cycle

■Adjustable Size Read-Only EEPROM Area

■Enhanced ESD Protection

■100,000 Erase/Write Cycles (minimum)

■40 Year Data Retention (minimum)

DESCRIPTION

These electrically erasable programmable memory (EEPROM) devices are fabricated with STMicroelectronics’ High Endurance, Double Polysilicon, CMOS technology. This guarantees an endurance typically well above one hundred

Table 1. Signal Names

	C				Serial Clock
	D				Serial Data Input
	Q				Serial Data Output
					Chip Select
	S
					Write Protect
	W
					Hold
	HOLD
	VCC				Supply Voltage
	VSS				Ground

8	14
1	1
PSDIP8 (BN)	TSSOP14 (DL)
0.25 mm frame	169 mil width

8

1

SO8 (MN) 150 mil width

Figure 1. Logic Diagram

	VCC
D	Q
C
S	M95xxx
W
HOLD
	VSS

AI01789C

June 1999

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M95640, M95320, M95160, M95080

Figure 2A. DIP Connections									Figure 2C. TSSOP Connections
											M95128
				M95xxx
									S		1	14		VCC
				1	8				Q		2	13		HOLD
	S					VCC
									NC		3	12		NC
	Q			2	7	HOLD
									NC		4	11		NC
				3	6	C
W
									NC		5	10		NC
VSS				4	5	D
									W		6	9		C
					AI01790C
									VSS		7	8		D
												AI02346
									Note: 1. NC = Not Connected

Figure 2B. SO Connections

	M95xxx
S	1	8	VCC
Q	2	7	HOLD
W	3	6	C
VSS	4	5	D
		AI01791C

Table 2. Absolute Maximum Ratings 1

thousand Erase/Write cycles, with a data retention of 40 years. The memories are organised as 8K x 8 bits and 4K x 8 bits (M95640, M95320) and 2K x 8 bits and 1K x 8 bits (M95160, M95080), and operate down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R version of each device).

The M95640, M95320 and M95160, M95080 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages.

Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 3.

The device is selected when the chip select input

(S) is held low. Communications with the chip can be interrupted using the hold input (HOLD).

Symbol	Parameter		Value	Unit
TA	Ambient Operating Temperature		-40 to 125	°C
TSTG	Storage Temperature		-65 to 150	°C
TLEAD		PSDIP8: 10 sec	260
	Lead Temperature during Soldering	SO8: 40 sec	215	°C
		TSSOP14: t.b.c.	t.b.c.
VO	Output Voltage Range		-0.3 to VCC+0.6	V
VI	Input Voltage Range		-0.3 to 6.5	V
VCC	Supply Voltage Range		-0.3 to 6.5	V
VESD	Electrostatic Discharge Voltage (Human Body model) 2		4000	V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

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M95640, M95320, M95160, M95080

Figure 3. Microcontroller and Memory Devices on the SPI Bus

SPI Interface with			D
(CPOL, CPHA) =			Q
('0', '0') or ('1', '1')
			C
	Master
(ST6, ST7, ST9,			C	Q D	C	Q D	C	Q	D
ST10, Others)
			M95xxx		M95xxx		M95xxx
CS3	CS2	CS1	S		S		S
									AI01958B

SIGNAL DESCRIPTION Serial Output (Q)

The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock.

Serial Input (D)

The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock.

Serial Clock (C)

The serial clock provides the timing for the serial interface (as shown in Figure 4). Instructions, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the Q pin changes state after the falling edge of the clock input.

Chip Select (S)

When S is high, the memory device is deselected, and the Q output pin is held in its high impedance state. Unless an internal write operation is underway, the memory device is placed in its stand-by power mode.

After power-on, a high-to-low transition on S is required prior to the start of any operation.

Write Protect (W)

The protection features of the memory device are summarized in Table 3.

The hardware write protection, controlled by the W pin, restricts write access to the Status Register

(though not to the WIP and WEL bits, which are set or reset by the device internal logic).

Bit 7 of the status register (as shown in Table 5) is the Status Register Write Disable bit (SRWD). When this is set to 0 (its initial delivery state) it is possible to write to the status register if the WEL bit (Write Enable Latch) has been set by the WREN instruction (irrespective of the level being applied to the W input).

When bit 7 (SRWD) of the status register is set to 1, the ability to write to the status register depends on the logic level being presented at pin W:

–If W pin is high, it is possible to write to the status register, after having set the WEL bit using the WREN instruction (Write Enable Latch).

–If W pin is low, any attempt to modify the status register is ignored by the device, even if the WEL bit has been set. As a consequence, all the data bytes in the EEPROM area, protected by the BPn bits of the status register, are also hardware protected against data corruption, and appear as a Read Only EEPROM area for the microcontroller. This mode is called the Hardware Protected Mode (HPM).

It is possible to enter the Hardware Protected Mode (HPM) either by setting the SRWD bit after pulling low the W pin, or by pulling low the W pin after setting the SRWD bit.

The only way to abort the Hardware Protected Mode, once entered, is to pull high the W pin.

If W pin is permanently tied to the high level, the Hardware Protected Mode is never activated, and the memory device only allows the user to protect

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M95640, M95320, M95160, M95080

Figure 4. Data and Clock Timing

CPOL CPHA

0	0	C
1	1	C
		D or Q	MSB	LSB

AI01438

a part of the memory, using the BPn bits of the status register, in the Software Protected Mode (SPM).

Hold (HOLD)

The HOLD pin is used to pause the serial communications between the SPI memory and controller, without losing bits that have already been decoded in the serial sequence. For a hold condition to occur, the memory device must already have been selected (S = 0). The hold condition starts when the HOLD pin is held low while the clock pin (C) is also low (as shown in Figure 14).

During the hold condition, the Q output pin is held in its high impedance state, and the levels on the input pins (D and C) are ignored by the memory device.

It is possible to deselect the device when it is still in the hold state, thereby resetting whatever transfer had been in progress. The memory remains in the hold state as long as the HOLD pin is low. To restart communication with the device, it is neces- sary both to remove the hold condition (by taking HOLD high) and to select the memory (by taking S low).

OPERATIONS

All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (D) sampled on the first rising edge of the clock (C) after the chip select (S) goes low.

Every instruction starts with a single-byte code, as summarised in Table 4. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S held low). If an invalid instruction is sent (one not contained in Table 4), the chip automatically deselects itself.

Write Enable (WREN) and Write Disable (WRDI)

The write enable latch, inside the memory device, must be set prior to each WRITE and WRSR operation. The WREN instruction (write enable) sets this latch, and the WRDI instruction (write disable) resets it.

The latch becomes reset by any of the following events:

–Power on

–WRDI instruction completion

–WRSR instruction completion

–WRITE instruction completion.

Table 3. Write Protection Control on the M95640, M95320, M95160, M95080

			SRWD				Data Bytes
W				Mode	Status Register
			Bit
							Protected Area	Unprotected Area
0 or 1			0	Software	Writeable (if the WREN		Software write protected	Writeable (if the WREN
				Protected	instruction has set the		by the BPn of the status	instruction has set the
1			1
				(SPM)	WEL bit)		register	WEL bit)
				Hardware			Hardware write protected	Writeable (if the WREN
0			1	Protected	Hardware write protected		by the BPn bits of the	instruction has set the
				(HPM)			status register	WEL bit)

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M95640, M95320, M95160, M95080

Figure 5. Block Diagram

HOLD		High Voltage
W	Control Logic
		Generator
S
C
D	I/O Shift Register
Q
	Address Register	Data
	and Counter	Register
		Status
		Register
	An - 31	An	Size of the
			Read only
			EEPROM
			area
	Y Decoder
		32 Bytes
	0000h	001Fh
		X Decoder
			AI01792C

Note: 1. The cell An represents the byte at the highest address in the memory

As soon as the WREN or WRDI instruction is received, the memory device first executes the instruction, then enters a wait mode until the device is deselected.

Read Status Register (RDSR)

The RDSR instruction allows the status register to be read, and can be sent at any time, even during a Write operation. Indeed, when a Write is in progress, it is recommended that the value of the Write-In-Progress (WIP) bit be checked. The value in the WIP bit (whose position in the status register is shown in Table 5) can be continuously polled, before sending a new WRITE instruction. This can be performed in one of two ways:

■Repeated RDSR instructions (each one consisting of S being taken low, C being clocked 8 times for the instruction and 8 times for the read operation, and S being taken high)

■A single, prolonged RDSR instruction (consisting of S being taken low, C being clocked 8 times for the instruction and kept running for repeated read operations), as shown in Figure 6.

The Write-In-Process (WIP) bit is read-only, and indicates whether the memory is busy with a Write

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M95640, M95320, M95160, M95080

Table 4. Instruction Set

	Instruc	Description	Instruction
	tion		Format
	WREN	Set Write Enable Latch	0000 0110
	WRDI	Reset Write Enable Latch	0000 0100
	RDSR	Read Status Register	0000 0101
	WRSR	Write Status Register	0000 0001
	READ	Read Data from Memory Array	0000 0011
	WRITE	Write Data to Memory Array	0000 0010

Table 5. Status Register Format

b7	b0
SRWD X	X X BP1 BP0 WEL WIP

Note: 1. SRWD, BP0 and BP1 are Read and write bits. 2. WEL and WIP are Read only bits.

operation. A ’1’ indicates that a write is in progress, and a ’0’ that no write is in progress.

The Write Enable Latch (WEL) bit indicates the status of the write enable latch. It, too, is read-only. Its value can only be changed by one of the events listed in the previous paragraph, or as a result of executing WREN or WRDI instruction. It cannot be changed using a WRSR instruction. A ’1’ indicates that the latch is set (the forthcoming Write instruction will be executed), and a ’0’ that it is reset (and any forthcoming Write instructions will be ignored).

The Block Protect (BP0 and BP1) bits indicate the amount of the memory that is to be write-protect- ed. These two bits are non-volatile. They are set using a WRSR instruction.

During a Write operation (whether it be to the memory area or to the status register), all bits of the status register remain valid, and can be read

using the RDSR instruction. However, during a Write operation, the values of the non-volatile bits (SRWD, BP0, BP1) become frozen at a constant value. The updated value of these bits becomes available when a new RDSR instruction is executed, after completion of the write cycle. On the other hand, the two read-only bits (WEL, WIP) are dynamically updated during internal write cycles. Using this facility, it is possible to poll the WIP bit to detect the end of the internal write cycle.

Write Status Register (WRSR)

The format of the WRSR instruction is shown in Figure 7. After the instruction and the eight bits of the status register have been latched-in, the internal Write cycle is triggered by the rising edge of the S line. This must occur after the falling edge of the 16th clock pulse, and before the rising edge of the 17th clock (as indicated in Figure 7), otherwise the internal write sequence is not performed.

The WRSR instruction is used for the following:

■to select the size of memory area that is to be write-protected

■to select between SPM (Software Protected Mode) and HPM (Hardware Protected Mode).

The size of the write-protection area applies equally in SPM and HPM. The BP1 and BP0 bits of the status register have the appropriate value (see Table 6) written into them after the contents of the protected area of the EEPROM have been written.

The initial delivery state of the BP1 and BP0 bits is 00, indicating a write-protection size of 0.

Software Protected Mode (SPM)

The act of writing a non-zero value to the BP1 and BP0 bits causes the Software Protected Mode (SPM) to be started. All attempts to write a byte or page in the protected area are ignored, even if the Write Enable Latch is set. However, writing is still allowed in the unprotected area of the memory ar-

Figure 6. RDSR: Read Status Register Sequence

S
0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
C
		INSTRUCTION
D
HIGH IMPEDANCE									STATUS REG. OUT								STATUS REG. OUT
Q								7	6	5	4	3	2	1	0	7	6	5	4	3	2	1	0	7
							MSB									MSB								MSB
																								AI02031
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