SGS Thomson Microelectronics M24C64-WMW6T, M24C64-WMW6, M24C64-WMN6T, M24C64-WMN6, M24C64-W Datasheet

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M24C64

M24C32

64/32 Kbit Serial I²C Bus EEPROM

■Compatible with I2C Extended Addressing

■Two Wire I2C Serial Interface Supports 400 kHz Protocol

■Single Supply Voltage:

–4.5V to 5.5V for M24Cxx

–2.5V to 5.5V for M24Cxx-W

–1.8V to 3.6V for M24Cxx-R

■Hardware Write Control

■BYTE and PAGE WRITE (up to 32 Bytes)

■RANDOM and SEQUENTIAL READ Modes

■Self-Timed Programming Cycle

■Automatic Address Incrementing

■Enhanced ESD/Latch-Up Behavior

■1 Million Erase/Write Cycles (minimum)

■40 Year Data Retention (minimum)

DESCRIPTION

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits (M24C64) and 4096x8 bits (M24C32), and operate down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R version of each device).

The M24C64 and M24C32 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages.

Table 1. Signal Names

	E0, E1, E2		Chip Enable Inputs

	SDA		Serial Data/Address Input/
			Output

	SCL		Serial Clock

			Write Control
	WC		Write Control

	VCC		Supply Voltage
	VSS		Ground

8	8
8
1	1
PSDIP8 (BN)	TSSOP8 (DW)
0.25 mm frame	169 mil width
0.25 mm frame
8	8
1	1
SO8 (MN)	SO8 (MW)
150 mil width	200 mil width

Figure 1. Logic Diagram

VCC

E0-E2

SDA

M24C64

SCL M24C32

VSS

AI01844B

December 1999

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M24C64, M24C32

Figure 2A. DIP Connections

Figure 2B. SO and TSSOP Connections

M24C64

M24C32

VCC

SCL

VSS

SDA

VSS

SDA

AI01845B

AI01846B

These memory devices are compatible with the I2C extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4- bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition.

The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by

Table 2. Absolute Maximum Ratings 1

a STOP condition after an Ack for WRITE, and after a NoAck for READ.

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the VCC voltage has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal.

SIGNAL DESCRIPTION Serial Clock (SCL)

The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slow-

Symbol	Parameter		Value	Unit

TA	Ambient Operating Temperature		-40 to 125	°C

TSTG	Storage Temperature		-65 to 150	°C

		PSDIP8: 10 seconds	260
TLEAD	Lead Temperature during Soldering	SO8: 40 seconds	215	°C
		TSSOP8: 40 seconds	215

VIO	Input or Output range		-0.6 to 6.5	V

VCC	Supply Voltage		-0.3 to 6.5	V

VESD	Electrostatic Discharge Voltage (Human Body model) 2		4000	V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

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M24C64, M24C32

er clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code (but note that the VIL and VIH levels for the inputs are CMOS compatible, not TTL compatible).

Write Control (WC)

The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed.

When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.

Please see the Application Note AN404 for a more detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication.

Start Condition

START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

Maximum RP value (kΩ)

VCC

SDA

MASTER

CBUS

SCL

fc = 100kHz

fc = 400kHz

CBUS

100

1000

CBUS (pF)

AI01665

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SGS Thomson Microelectronics M24C64-WMW6T, M24C64-WMW6, M24C64-WMN6T, M24C64-WMN6, M24C64-W Datasheet

M24C64, M24C32

Figure 4. I2C Bus Protocol

SCL
SDA
START	SDA	SDA	STOP
CONDITION	INPUT	CHANGE	CONDITION

SCL	1	2	3	7	8	9
SDA	MSB					ACK
	START
	CONDITION
SCL	1	2	3	7	8	9
SDA	MSB					ACK

STOP

CONDITION

AI00792

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low.

Memory Addressing

To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0).

To address the memory array, the 4-bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins.

The 8th bit is the RW bit. This is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match

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Table 3. Device Select Code 1

Device Type Identifier

Chip Enable

Device Select Code

Note: 1. The most significant bit, b7, is sent first.

the Device Select Code, it deselects itself from the bus, and goes into stand-by mode.

There are two modes both for read and write. These are summarized in Table 6 and described later. A communication between the master and the slave is ended with a STOP condition.

Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. Bits b15 to b13 are treated as a Don’t Care bit on the M24C64 memory. Bits b15 to b12 are treated as Don’t Care bits on the M24C32 memory.

Write Operations

Following a START condition the master sends a Device Select Code with the RW bit set to ’0’, as shown in Table 6. The memory acknowledges this, and waits for two address bytes. The memory responds to each address byte with an acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC=1 (during a period of time from the START condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes will not be acknowledged (as shown in Figure 5).

Byte Write

In the Byte Write mode, after the Device Select Code and the address bytes, the master sends one data byte. If the addressed location is write

Table 6. Operating Modes

Table 4. Most Significant Byte

b15	b14	b13	b12	b11	b10	b9	b8

Note: 1. b15 to b13 are Don’t Care on the M24C64 series. b15 to b12 are Don’t Care on the M24C32 series.

Table 5. Least Significant Byte

b7	b6	b5	b4	b3	b2	b1	b0

protected by the WC pin, the memory replies with a NoAck, and the location is not modified. If, instead, the WC pin has been held at 0, as shown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition.

Page Write

The Page Write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory address bits (b12-b5 for the M24C64 and b11-b5 for the M24C32) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet).

The master sends from one up to 32 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal

Mode

bit

Bytes

Initial Sequence

Current Address Read

= ‘1’

START, Device Select, RW

= ‘0’, Address

Random Address Read

START, Device Select, RW

= ‘1’

reSTART, Device Select, RW

Sequential Read

³ 1

Similar to Current or Random Address Read

Byte Write

VIL

= ‘0’

START, Device Select, RW

Page Write

VIL

£ 32

= ‘0’

START, Device Select, RW

Note: 1. X = VIH or VIL.

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M24C64, M24C32

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

ACK

NO ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

START

R/W

STOP

PAGE WRITE

START

WC (cont'd)

PAGE WRITE (cont'd)

ACK

NO ACK

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

R/W

NO ACK

DATA IN N

STOP

AI01120B

byte address counter (the 5 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition.

When the master generates a STOP condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not trigger the internal write cycle.

During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests.

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