SGS Thomson Microelectronics M27C4001-90XN6X, M27C4001-90XN6TR, M27C4001-90XN1X, M27C4001-90XN1TR, M27C4001-90XL6X Datasheet

M27C4001

4 Mbit (512Kb x 8) UV EPROM and OTP EPROM

■5V ± 10% SUPPLY VOLTAGE in READ OPERATION

■ACCESS TIME: 35ns

■LOW POWER CONSUMPTION:

±Active Current 30mA at 5MHz

±Standby Current 100μA

■PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■PROGRAMMING TIME: 100μs/word

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: 41h

DESCRIPTION

The M27C4001 is a 4 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organised as 524,288 by 8 bits.

The FDIP32W (window ceramic frit-seal package) and LCCC32W (leadless chip carrier package) have a transparent lid which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27C4001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

32	32
1	1
FDIP32W (F)	PDIP32 (B)

LCCC32W (L)

PLCC32 (C)	TSOP32 (N)
	8 x 20 mm

Figure 1. Logic Diagram

VCC	VPP
19	8
A0-A18	Q0-Q7

E M27C4001

G

VSS

AI00721B

November 2000

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M27C4001

Figure 2A. DIP Connections

VPP	1	32	VCC
A16	2	31	A18
A15	3	30	A17
A12	4	29	A14
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	M27C4001 25	A11
A3	9	24	G
A2	10	23	A10
A1	11	22	E
A0	12	21	Q7
Q0	13	20	Q6
Q1	14	19	Q5
Q2	15	18	Q4
VSS	16	17	Q3
		AI00722

Figure 2C. TSOP Connections

A11	1		32	G
A9				A10
A8				E
A13				Q7
A14				Q6
A17				Q5
A18				Q4
VCC	8	M27C4001	25	Q3
VPP	9	(Normal)	24	VSS
A16				Q2
A15				Q1
A12				Q0
A7				A0
A6				A1
A5				A2
A4	16		17	A3
		AI01155B

Figure 2B. LCC Connections

	A12	A15	A16	PP	CC	A18	A17
				V	V
A7				1	32			A14
A6								A13
A5								A8
A4								A9
A3	9		M27C4001				25	A11
A2								G
A1								A10
A0								E
Q0				17				Q7
			SS
	Q1	Q2		Q3	Q4	Q5	Q6
			V

AI00723

Table 1. Signal Names

A0-A18	Address Inputs
Q0-Q7	Data Outputs
E	Chip Enable
G	Output Enable
VPP	Program Supply
VCC	Supply Voltage
VSS	Ground

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M27C4001

Table 2. Absolute Maximum Ratings (1)

Symbol

TA

TBIAS

TSTG

VIO (2)

VCC

VA9 (2)

VPP

Parameter	Value	Unit
Ambient Operating Temperature (3)	±40 to 125	°C
Temperature Under Bias	±50 to 125	°C
Storage Temperature	±65 to 150	°C
Input or Output Voltage (except A9)	±2 to 7	V
Supply Voltage	±2 to 7	V
A9 Voltage	±2 to 13.5	V
Program Supply Voltage	±2 to 14	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3.Depends on range.

Table 3. Operating Modes (1)

Mode	E	G	A9	Vpp	Q7 - Q0
Read	VIL	VIL	X	VCC or VSS	Data Out
Output Disable	VIL	VIH	X	VCC or VSS	Hi-Z
Program	VIL Pulse	VIH	X	VPP	Data In
Verify	VIH	VIL	X	VPP	Data Out
Program Inhibit	VIH	VIH	X	VPP	Hi-Z
Standby	VIH	X	X	VCC or VSS	Hi-Z
Electronic Signature	VIL	VIL	VID	VCC	Codes

Note: 1. X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier	A0	Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0	Hex Data
Manufacturer's Code	VIL	0	0	1	0	0	0	0	0	20h
Electronic Signature	VIH	0	1	0	0	0	0	0	1	41h

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M27C4001

Table 5. AC Measurement Conditions

	High Speed	Standard
Input Rise and Fall Times	≤ 10ns	≤ 20ns
Input Pulse Voltages	0 to 3V	0.4 to 2.4V
Input and Output Timing Ref. Voltages	1.5V	0.8 and 2V

Figure 3. AC Testing Input Output Waveform	Figure 4. AC Testing Load Circuit
	1.3V
High Speed
3V	1N914
1.5V
0V	3.3kΩ
	DEVICE
Standard	UNDER	OUT
	TEST
2.4V	CL
2.0V
0.8V

0.4V

CL = 30pF for High Speed

AI01822

CL = 100pF for Standard
CL includes JIG capacitance	AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol	Parameter	Test Condition	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		6	pF
COUT	Output Capacitance	VOUT = 0V		12	pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

The operating modes of the M27C4001 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature.

Read Mode

The M27C4001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the ad-

dresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

Standby Mode

The M27C4001 has a standby mode which reduces the supply current from 30mA to 100μA. The M27C4001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

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M27C4001

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

	ILI	Input Leakage Current
	ILO	Output Leakage Current
	ICC	Supply Current
	ICC1	Supply Current (Standby) TTL
	ICC2	Supply Current (Standby) CMOS
	IPP	Program Current
	VIL	Input Low Voltage
	VIH (2)	Input High Voltage
	VOL	Output Low Voltage
	VOH	Output High Voltage TTL
		Output High Voltage CMOS

0V ≤ VIN ≤ VCC		±10	μA
0V ≤ VOUT ≤ VCC		±10	μA
E = VIL, G = VIL,		30	mA
IOUT = 0mA, f = 5MHz
E = VIH		1	mA
E > VCC ± 0.2V		100	μA
VPP = VCC		10	μA
	±0.3	0.8	V
	2	VCC + 1	V
IOL = 2.1mA		0.4	V
IOH = ±400μA	2.4		V
IOH = ±100μA	VCC ± 0.7V		V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C4001

Symbol

Alt

Parameter

Test Condit ion

-35 (3)

-45 (3)

-55 (3)

Unit

Min

Max

Min

Max

Min

Max

tAVQV

tACC

Address Valid to

E = VIL, G = VIL

35

45

55

ns

Output Valid

tELQV

tCE

Chip Enable Low to

G = VIL

35

45

55

ns

Output Valid

tGLQV

tOE

Output Enable Low to

E = VIL

20

25

30

ns

Output Valid

tEHQZ (2)

tDF

Chip Enable High to

G = VIL

0

30

0

30

0

30

ns

Output Hi-Z

t

(2)

tDF

Output Enable High to

E = VIL

0

30

0

30

0

30

ns

Output Hi-Z

GHQZ

tAXQX

tOH

Address Transition to

E = VIL, G = VIL

0

0

0

ns

Output Transition

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP

2.Sampled only, not 100% tested.

3.Speed obtained with High Speed AC measurement conditions.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a.the lowest possible memory power dissipation,

b.complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

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M27C4001

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C4001

Symbol

Alt

Parameter

Test Conditi on

-70

-80/-90

-10/-12/-15 Unit

Min

Max

Min

Max

Min

Max

tAVQV

tACC

Address Valid to

E = VIL, G = VIL

70

80

100

ns

Output Valid

tELQV

tCE

Chip Enable Low to

G = VIL

70

80

100

ns

Output Valid

tGLQV

tOE

Output Enable Low to

E = VIL

35

40

50

ns

Output Valid

t

(2)

tDF

Chip Enable High to

G = VIL

0

30

0

30

0

30

ns

EHQZ

Output Hi-Z

t

(2)

tDF

Output Enable High to

E = VIL

0

30

0

30

0

30

ns

Output Hi-Z

GHQZ

tAXQX

tOH

Address Transition to

E = VIL, G = VIL

0

0

0

ns

Output Transition

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A18	VALID	VALID
	tAVQV	tAXQX
E
	tGLQV	tEHQZ
G
	tELQV	tGHQZ
Q0-Q7		Hi-Z
		AI00724B

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line

output control and by properly selected decoupling capacitors. It is recommended that a 0.1μF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7μF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

6/17