SGS Thomson Microelectronics M29W160BB90N1, M29W160BB70N1, M29W160BB, M29W160BT90N6, M29W160BT90N1 Datasheet

M29W160BT

M29W160BB

16 Mbit (2Mb x8 or 1Mb x16, Boot Block) Low Voltage Single Supply Flash Memory

PRELIMINARY DATA

■SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 70ns

■PROGRAMMING TIME

±10μs per Byte/Word typical

■35 MEMORY BLOCKS

±1 Boot Block (Top or Bottom Location)

±2 Parameter and 32 Main Blocks

■PROGRAM/ERASE CONTROLLER

±Embedded Byte/Word Program algorithm

±Embedded Multi-Block/Chip Erase algorithm

±Status Register Polling and Toggle Bits

±Ready/Busy Output Pin

■ERASE SUSPEND and RESUME MODES

±Read and Program another Block during Erase Suspend

■UNLOCK BYPASS PROGRAM COMMAND

±Faster Production/Batch Programming

■TEMPORARY BLOCK UNPROTECTION MODE

■SECURITY MEMORY BLOCK

■LOW POWER CONSUMPTION

±Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■20 YEARS DATA RETENTION

±Defectivity below 1 ppm/year

■ELECTRONIC SIGNATURE

±Manufacturer Code: 0020h

±Top Device Code M29W160BT: 22C4h

±Bottom Device Code M29W160BB: 2249h

44

	1
TSOP48 (N)	SO44 (M)
12 x 20mm

FBGA

LFBGA48 (ZA) 8 x 6 solder balls

Figure 1. Logic Diagram

		VCC
	20		15
	A0-A19		DQ0-DQ14
	W		DQ15A±1
	E	M29W160BT	BYTE
		M29W160BB
	G		RB
	RP

VSS

AI00981

Note: RB not available on SO44 package.

February 2000

1/25

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29W160BT, M29W160BB

Figure 2. TSOP Connections

A15	1		48	A16
A14				BYTE
A13				VSS
A12				DQ15A±1
A11				DQ7
A10				DQ14
A9				DQ6
A8				DQ13
A19				DQ5
NC				DQ12
W				DQ4
RP	12	M29W160BT	37	VCC
NC	13	M29W160BB	36	DQ11
NC				DQ3
RB				DQ10
A18				DQ2
A17				DQ9
A7				DQ1
A6				DQ8
A5				DQ0
A4				G
A3				VSS
A2				E
A1	24		25	A0
		AI02994

Table 1. Signal Names

	A0-A19	Address Inputs
	DQ0-DQ7	Data Inputs/Outputs
	DQ8-DQ14	Data Inputs/Outputs
	DQ15A±1	Data Input/Output or Address Input
	E	Chip Enable
	G	Output Enable
	W	Write Enable
	RP	Reset/Block Temporary Unprotect
	RB	Ready/Busy Output
		(Not available on SO44 package)
	BYTE	Byte/Word Organization Select
	VCC	Supply Voltage
	VSS	Ground
	NC	Not Connected Internally
	DU	Don't Use as internally connected

Figure 3. SO Connections

RP	1	44	W
A18	2	43	A19
A17	3	42	A8
A7	4	41	A9
A6	5	40	A10
A5	6	39	A11
A4	7	38	A12
A3	8	37	A13
A2	9	36	A14
A1	10	35	A15
A0	11 M29W160BT 34		A16
E	12 M29W160BB 33		BYTE
VSS	13	32	VSS
G	14	31	DQ15A±1
DQ0	15	30	DQ7
DQ8	16	29	DQ14
DQ1	17	28	DQ6
DQ9	18	27	DQ13
DQ2	19	26	DQ5
DQ10	20	25	DQ12
DQ3	21	24	DQ4
DQ11	22	23	VCC
		AI00978

2/25

M29W160BT, M29W160BB

Figure 4. LFBGA Connections (Top view through package)

		1	2	3	4	5	6	7	8
	F	A13	A12	A14	A15	A16	BYTE	DQ15	VSS
								A±1
	E	A9	A8	A10	A11	DQ7	DQ14	DQ13	DQ6
	D	W	RP	DU	A19	DQ5	DQ12	VCC	DQ4
	C	RB	DU	A18	DU	DQ2	DQ10	DQ11	DQ3
	B	A7	A17	A6	A5	DQ0	DQ8	DQ9	DQ1
	A	A3	A4	A2	A1	A0	E	G	VSS

AI02985B

3/25

M29W160BT, M29W160BB

Table 2. Absolute Maximum Ratings (1)

	Symbol	Parameter	Value	Unit
	TA	Ambient Operating Temperature (Temperature Range Option 1)	0 to 70	°C
		Ambient Operating Temperature (Temperature Range Option 6)	±40 to 85	°C
	T	Temperature Under Bias	±50 to 125	°
	BIAS			C
	T	Storage Temperature	±65 to 150	°
	STG			C
	VIO (2)	Input or Output Voltage	±0.6 to 4	V
	VCC	Supply Voltage	±0.6 to 4	V
	VID	Identification Voltage	±0.6 to 13.5	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to ±2V during transition and for less than 20ns during transitions.

SUMMARY DESCRIPTION

The M29W160B is a 16 Mbit (2Mb x8 or 1Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents.

The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 (0.8mm pitch) packages and it is supplied with all the bits erased (set to '1').

4/25

M29W160BT, M29W160BB

Table 3. Top Boot Block Addresses,

M29W160BT

Table 4. Bottom Boot Block Addresses,

M29W160BB

	#	Size	Address Range	Address Range	#	Size	Address Range	Address Range
		(Kbytes)	(x8)	(x16)		(Kbytes)	(x8)	(x16)
	34	16	1FC000h-1FFFFFh FE000h-FFFFFh		34	64	1F0000h-1FFFFFh F8000h-FFFFFh
	33	8	1FA000h-1FBFFFh FD000h-FDFFFh		33	64	1E0000h-1EFFFFh F0000h-F7FFFh
	32	8	1F8000h-1F9FFFh FC000h-FCFFFh		32	64	1D0000h-1DFFFFh E8000h-EFFFFh
	31	32	1F0000h-1F7FFFh F8000h-FBFFFh		31	64	1C0000h-1CFFFFh E0000h-E7FFFh
	30	64	1E0000h-1EFFFFh F0000h-F7FFFh		30	64	1B0000h-1BFFFFh D8000h-DFFFF h
	29	64	1D0000h-1DFFFFh E8000h-EFFFFh		29	64	1A0000h-1AFFFFh D0000h-D7FFFh
	28	64	1C0000h-1CFFFFh E0000h-E7FFFh		28	64	190000h-19FFFFh C8000h-CFFFF h
	27	64	1B0000h-1BFFFFh D8000h-DFFFFh		27	64	180000h-18FFFFh C0000h-C7FFFh
	26	64	1A0000h-1AFFFFh D0000h-D7FFFh		26	64	170000h-17FFFFh B8000h-BFFFFh
	25	64	190000h-19FFFFh C8000h-CFFFFh		25	64	160000h-16FFFFh B0000h-B7FFFh
	24	64	180000h-18FFFFh C0000h-C7FFFh		24	64	150000h-15FFFFh A8000h-AFFFFh
	23	64	170000h-17FFFFh B8000h-BFFFFh		23	64	140000h-14FFFFh A0000h-A7FFFh
	22	64	160000h-16FFFFh B0000h-B7FFFh		22	64	130000h-13FFFFh 98000h-9FFFF h
	21	64	150000h-15FFFFh A8000h-AFFFFh		21	64	120000h-12FFFFh 90000h-97FFFh
	20	64	140000h-14FFFFh A0000h-A7FFFh		20	64	110000h-11FFFFh 88000h-8FFFF h
	19	64	130000h-13FFFFh 98000h-9FFFFh		19	64	100000h-10FFFFh 80000h-87FFFh
	18	64	120000h-12FFFFh 90000h-97FFFh		18	64	0F0000h-0FFFFFh 78000h-7FFFF h
	17	64	110000h-11FFFFh 88000h-8FFFFh		17	64	0E0000h-0EFFFFh 70000h-77FFFh
	16	64	100000h-10FFFFh 80000h-87FFFh		16	64	0D0000h-0DFFFFh 68000h-6FFFF h
	15	64	0F0000h-0FFFFFh 78000h-7FFFFh		15	64	0C0000h-0CFFFFh 60000h-67FFFh
	14	64	0E0000h-0EFFFFh	70000h-77FFFh	14	64	0B0000h-0BFFFFh 58000h-5FFFF h
	13	64	0D0000h-0DFFFFh 68000h-6FFFFh		13	64	0A0000h-0AFFFFh 50000h-57FFFh
	12	64	0C0000h-0CFFFFh	60000h-67FFFh	12	64	090000h-09FFFFh 48000h-4FFFF h
	11	64	0B0000h-0BFFFFh 58000h-5FFFFh		11	64	080000h-08FFFFh 40000h-47FFFh
	10	64	0A0000h-0AFFFFh 50000h-57FFFh		10	64	070000h-07FFFFh 38000h-3FFFF h
	9	64	090000h-09FFFFh 48000h-4FFFFh		9	64	060000h-06FFFFh 30000h-37FFFh
	8	64	080000h-08FFFFh 40000h-47FFFh		8	64	050000h-05FFFFh 28000h-2FFFF h
	7	64	070000h-07FFFFh 38000h-3FFFFh		7	64	040000h-04FFFFh 20000h-27FFFh
	6	64	060000h-06FFFFh 30000h-37FFFh		6	64	030000h-03FFFFh 18000h-1FFFF h
	5	64	050000h-05FFFFh 28000h-2FFFFh		5	64	020000h-02FFFFh 10000h-17FFFh
	4	64	040000h-04FFFFh 20000h-27FFFh		4	64	010000h-01FFFFh 08000h-0FFFF h
	3	64	030000h-03FFFFh 18000h-1FFFFh		3	32	008000h-00FFFFh 04000h-07FFFh
	2	64	020000h-02FFFFh 10000h-17FFFh		2	8	006000h-007FFFh 03000h-03FFFh
	1	64	010000h-01FFFFh 08000h-0FFFFh		1	8	004000h-005FFFh 02000h-02FFFh
	0	64	000000h-00FFFFh	00000h-07FFFh	0	16	000000h-003FFFh	00000h-01FFFh

5/25

M29W160BT, M29W160BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A±1 Low will select the LSB of the Word on the other addresses, DQ15A±1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 18 and Figure 12, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 18 and Figure 12, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode.

VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1μF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3.

Vss Ground. The VSS Ground is the reference for all voltage measurements.

6/25

M29W160BT, M29W160BB

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Read Mode AC Waveforms,

Table 5. Bus Operations, BYTE = VIL

and Table 15, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 10 and 11, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing requirements.

	Operation	E	G	W
	Bus Read	VIL	VIL	VIH
	Bus Write	VIL	VIH	VIL
	Output Disable	X	VIH	VIH
	Standby	VIH	X	X
	Read Manufacturer	VIL	VIL	VIH
	Code
	Read Device Code	VIL	VIL	VIH
	Note: X = VIL or VIH.

Address Inputs

DQ15A±1, A0-A19

Cell Address

Command Address

X

X

A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH

Data Inpu ts/Outputs

	DQ14-DQ8	DQ7-DQ0
	Hi-Z	Data Output
	Hi-Z	Data Input
	Hi-Z	Hi-Z
	Hi-Z	Hi-Z
	Hi-Z	20h
	Hi-Z	C4h (M29W160BT)
		49h (M29W160BB)

Table 6. Bus Operations, BYTE = VIH

	Operation	E	G	W
	Bus Read	VIL	VIL	VIH
	Bus Write	VIL	VIH	VIL
	Output Disable	X	VIH	VIH
	Standby	VIH	X	X
	Read Manufacturer	VIL	VIL	VIH
	Code
	Read Device Code	VIL	VIL	VIH
	Note: X = VIL or VIH.

	Address Inputs	Data Inpu ts/Outputs
	A0-A19	DQ15A±1, DQ14-DQ0
	Cell Address	Data Output
	Command Address	Data Input
	X	Hi-Z
	X	Hi-Z
	A0 = VIL, A1 = VIL, A9 = VID,	0020h
	Others VIL or VIH
	A0 = VIH, A1 = VIL, A9 = VID,	22C4h (M29W160BT)
	Others VIL or VIH	2249h (M29W160BB)

7/25

M29W160BT, M29W160BB

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14, DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.

Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 5 and 6, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or 8- bit mode. See either Table 7, or 8, depending on the configuration that is being used, for a summary of the commands.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless stated otherwise (see Security Data command). It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10μs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29W160BT is 22C4h and for the M29W160BB is 2249h.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 10. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

8/25