SGS Thomson Microelectronics M48Z02, M48Z12-150PC1, M48Z12, M48Z02-70PC1, M48Z02-200PC1 Datasheet

M48Z02

M48Z12

16 Kbit (2Kb x 8) ZEROPOWER®SRAM

INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY

UNLIMITED WRITE CYCLES

READ CYCLE TIME EQUALS WRITE CYCLE TIME

AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION

WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):

– M48Z02: 4.50V £ VPFD £ 4.75V

– M48Z12: 4.20V £ VPFD £ 4.50V

SELF-CONTAINED BATTERY in the CAPHAT DIP PACKAGE

PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 2K x 8 SRAMs

DESCRIPTION

The M48Z02/12 ZEROPOWER® RAM is a 2K x 8 non-volatile static RAM which is pin and functional compatible with the DS1220.

A special 24 pin 600mil DIP CAPHATä package houses the M48Z02/12 silicon with a long life lithium button cell to form a highly integrated battery backed-up memory solution.

The M48Z02/12 button cell has sufficient capacity and storage life to maintain data and clock functionality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range.

Table 1. Signal Names

	A0-A10				Address Inputs
	DQ0-DQ7				Data Inputs / Outputs
					Chip Enable
	E
					Output Enable
	G
					Write Enable
	W
	VCC				Supply Voltage
	VSS				Ground

24

1

PCDIP24 (PC)

Battery CAPHAT

Figure 1. Logic Diagram

	VCC
11	8
A0-A10	DQ0-DQ7
W	M48Z02
E	M48Z12
G

VSS

AI01186

May 1999

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M48Z02, M48Z12

Table 2. Absolute Maximum Ratings (1)

Symbol	Parameter	Value	Unit
TA	Ambient Operating Temperature	–40 to 85	°C
TSTG	Storage Temperature (VCC Off)	–40 to 85	°C
(2)	Lead Solder Temperature for 10 seconds	260	°C
TSLD
VIO	Input or Output Voltages	–0.3 to 7	V
VCC	Supply Voltage	–0.3 to 7	V
IO	Output Current	20	mA
PD	Power Dissipation	1	W

Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

Table 3. Operating Modes

Mode

VCC

E

G

W

DQ0-DQ7

Power

Deselect

4.75V to 5.5V

VIH

X

X

High Z

Standby

Write

VIL

X

VIL

DIN

Active

or

Read

4.5V to 5.5V

VIL

VIL

VIH

DOUT

Active

Read

VIL

VIH

VIH

High Z

Active

Deselect

VSO to VPFD (min)

X

X

X

High Z

CMOS Standby

Deselect

≤ VSO

X

X

X

High Z

Battery Back-up Mode

Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

Figure 2. DIP Pin Connections

A7	1		24	VCC
A6	2		23	A8
A5	3		22	A9
A4	4		21
				W
A3	5		20
				G
A2	6	M48Z02	19	A10
A1	7	M48Z12	18
				E
A0	8		17	DQ7
DQ0	9		16	DQ6
DQ1	10		15	DQ5
DQ2	11		14	DQ4
VSS	12		13	DQ3
		AI01187

DESCRIPTION (cont’d)

The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed.

The M48Z02/12 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.

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M48Z02, M48Z12

Figure 3. Block Diagram

				A0-A10
	LITHIUM			DQ0-DQ7
	CELL	POWER	2K x 8
	VOLTAGE SENSE		SRAM ARRAY
	AND			E
	SWITCHING	VPFD
	CIRCUITRY			W
				G
	VCC		VSS	AI01255

READ MODE

The M48Z02/12 is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV).

The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.

Table 4. AC Measurement Conditions

Input Rise and Fall Times	≤ 5ns
Input Pulse Voltages	0V to 3V
Input and Output Timing Ref. Voltages	1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 4. AC Testing Load Circuit

5V

1.8kΩ

DEVICE

UNDER OUT TEST

1kΩ

CL = 100pF

CL includes JIG capacitance

AI01019

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M48Z02, M48Z12

Table 5. Capacitance (1)

(TA = 25 °C)

Symbol		Parameter	Test Condition	Min	Max	Unit
CIN		Input Capacitance	VIN = 0V		10	pF
CIO (2)		Input / Output Capacitance	VOUT = 0V		10	pF
Notes: 1.	Effective capacitance measured with power supply at 5V.
2.	Outputs deselected

Table 6. DC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Symbol	Parameter	Test Condition					Min	Max	Unit
ILI (1)	Input Leakage Current		0V ≤ VIN ≤ VCC					±1	μA
(1)	Output Leakage Current	0V ≤ VOUT ≤ VCC						±5	μA
ILO
ICC	Supply Current		Outputs open					80	mA
ICC1	Supply Current (Standby) TTL							3	mA
					E	= VIH
ICC2	Supply Current (Standby) CMOS							3	mA
			E	= VCC – 0.2V
VIL (2)	Input Low Voltage						–0.3	0.8	V
VIH	Input High Voltage						2.2	VCC + 0.3	V
VOL	Output Low Voltage			IOL = 2.1mA				0.4	V
VOH	Output High Voltage			IOH = –1mA			2.4		V

Notes: 1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per cycle.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70°C or –40 to 85°C)

Symbol	Parameter	Min	Typ	Max	Unit
VPFD	Power-fail Deselect Voltage (M48Z02)	4.5	4.6	4.75	V
VPFD	Power-fail Deselect Voltage (M48Z12)	4.2	4.3	4.5	V
VSO	Battery Back-up Switchover Voltage		3.0		V
tDR	Expected Data Retention Time	10			YEARS

Note: 1. All voltages referenced to VSS.

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