NSC 5962R8969301VFA, 5962R8969301VEA, 5962-8969301EA, 5962-8969301FA, 5962-89693012A Datasheet
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August 1998
54AC175 · 54ACT175 Quad D Flip-Flop
General Description
The 'AC/'ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.
nBuffered positive edge-triggered clock
nAsynchronous common reset
nTrue and complement output
nOutputs source/sink 24 mA
n'ACT175 has TTL-compatible inputs
nStandard Microcircuit Drawing (SMD)
Ð'AC175: 5962-89552
Ð'ACT175: 5962-89693
Features
n Edge-triggered D-type inputs
Logic Symbols |
Connection Diagrams |
Pin Assignment for DIP and Flatpak
DS100278-1
IEEE/IEC
DS100278-3
Pin Assignment for LCC
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DS100278-2 |
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DS100278-4 |
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Pin Names |
Description |
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D0±D3 |
Data Inputs |
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CP |
Clock Pulse Input |
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Master Reset Input |
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MR |
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Q0±Q3 |
True Outputs |
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Q |
0±Q |
3 |
Complement Outputs |
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FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Flop-Flip D Quad 54ACT175 · 54AC175
© 1998 National Semiconductor Corporation |
DS100278 |
www.national.com |
Functional Description
The 'AC/'ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 'AC/'ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
Logic Diagram
Truth Table
Inputs |
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Outputs |
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@ tn, |
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= H |
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@ tn+1 |
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MR |
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Dn |
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Qn |
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Q |
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L |
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L |
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H |
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H |
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H |
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L |
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H = HIGH Voltage Level |
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L = LOW Voltage Level |
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tn = Bit Time before Clock Pulse |
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tn+1 = Bit Time after Clock Pulse |
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DS100278-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com |
2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
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2.0V to 6.0V |
'ACT |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54AC/ACT |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate ( |
V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate ( |
V/ |
t) |
'ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
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54AC |
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Symbol |
Parameter |
VCC |
TA = −55ÊC to +125ÊC |
Units |
Conditions |
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(V) |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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5.5 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.9 |
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IOUT = −50 µA |
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Output Voltage |
4.5 |
4.4 |
V |
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5.5 |
5.4 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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IOH = −12 mA |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
VOL |
Maximum Low Level |
3.0 |
0.1 |
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IOUT = 50 µA |
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Output Voltage |
4.5 |
0.1 |
V |
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5.5 |
0.1 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
0.50 |
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IOL = 12 mA |
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4.5 |
0.50 |
V |
IOL = 24 mA |
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5.5 |
0.50 |
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IOL = 24 mA |
IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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(Note 3) |
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IOLD |
Minimum Dynamic |
5.5 |
50 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current |
5.5 |
−50 |
mA |
V OHD = 3.85V Min |
3 |
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