Motorola MCM32A932SG33, MCM32A964SG33, MCM32A764SG33, MCM32A832SG33, MCM32A732SG33 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM32A732/D

Advance Information

128KB/256KB Secondary Cache Module

With Tag, Valid, and Dirty for i486 Processor Systems

This family of cache modules is well suited to provide the secondary cache for the Intel 82420 PCI chipset. This family provides the 128K Byte and 256K Byte cache sizes with valid, dirty and a choice of 7, 8, or 9 tag bits. The tag/valid bits have 12 ns access times for zero wait states at 33 MHz clock speeds. The PD pins map into the configuration register of the 82420 for auto±configuration of the cache controller during system startup.

•Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48

•Single 5 V ± 10% Power Supply

•All Inputs and Outputs are TTL Compatible

•Three State Outputs

•Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz

•Cache Byte Write, Bank Chip Enable, Bank Output Enable

•Decoupling Capacitors are Used for Each Fast Static RAM

•High Quality Multi±Layer FR4 PWB With Separate Power and Ground Planes

MCM32A732

MCM32A832

MCM32A932

MCM32A764

MCM32A864

MCM32A964

112±LEAD CARD EDGE CASE 1112±01 TOP VIEW

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BurstRAM is a registered trademark of Motorola.

I486 is a registered trademark Intel Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1 6/95

Motorola, Inc. 1994

PIN ASSIGNMENT CACHE MODULE 112±LEAD CARDEDGE TOP VIEW

						Main
					Cache	Memory
PD4	PD3	PD2	PD1	PD0	Size	Max	Module
NC	NC	NC	NC	NC	Ð	Ð	No Module
VCC	VCC	NC	NC	VCC	128KB	16MB	32A732
VCC	NC	NC	NC	VCC	128KB	32MB	32A832
VCC	NC	VCC	NC	VCC	128KB	64MB	32A932
VCC	VCC	NC	VCC	NC	256KB	32MB	32A764
VCC	NC	NC	VCC	NC	256KB	64MB	32A864
VCC	NC	VCC	VCC	NC	256KB	128MB	32A964

PIN NAMES

A4 ± A19 . . . . . . .

. . . . . . . . . . . . . . . Address Inputs

HCA2, HCA3 . . . .

. . . Upper Bank Address Inputs

LCA2, LCA3 . . . . .

. . . Lower Bank Address Inputs

ALE . . . . . . . . . . . .

. . . . . . . . Address Latch Enable

Byte Write Enable

Wx

E0,

E1

.

. .

. . . . . . .

. . . . . . . . . . . Bank Chip Enable

G0,

G1

.

. .

. . . . . . .

. . . . . . . . . Bank Output Enable

DQ0 ± DQ31 . . . . .

. . . . . Cache Data Input/Output

TDQ0 ± TDQ8 . . .

. . . . . . . . Tag Data Input/Output

Tag Write Enable

TWE

TG

. . . .

. .

. . . . . . .

. . . . . . . . . . . Tag Output Enable

TE

. . . .

. .

. . . . . . .

. . . . . . . . . . . . . Tag Chip Enable

VALID . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . Valid Bit

Dirty Write Enable

DIRTYWE

DIRTYE

. . . . . . . . .

. . . . . . . . . . . . Dirty Chip Enable

DIRTYD . . . . . . . . .

. . . . . . . . . . . . . Dirty Data Input

DIRTYQ . . . . . . . . .

. . . . . . . . . . . . Dirty Data Output

PD0 ± PD4 . . . . . .

. . . . . . . . . . . . Presence Detect

NC . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . No Connect

VCC . . . . . . . . . . . .

. . . . . . . . . . +5 V Power Supply

VSS . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . Ground

*No Connect for 32A864, 32A832

**No Connect for 32A764, 32A864, 32A732, 32A832

		VSS								57	1		VSS
		DQ0								58	2		DQ1
		DQ2								59	3		DQ3
		DQ4								60	4		DQ5
		DQ6								61	5		DQ7
		VCC								62	6		VCC
		NC								63	7		NC
		DQ8								64	8		DQ9
	DQ10									65	9		DQ11
	DQ12									66	10		DQ13
		VSS								67	11		VSS
	DQ14									68	12		DQ15
	DQ16									69	13		DQ17
	DQ18									70	14		DQ19
	DQ20									71	15		DQ21
		VCC								72	16		VCC
	DQ22									73	17		DQ23
		NC								74	18		NC
	DQ24									75	19		DQ25
	DQ26									76	20		DQ27
		VSS								77	21		VSS
	DQ28									78	22		DQ29
	DQ30									79	23		DQ31
		LA2								80	24		HA2
		LA3								81	25		HA3
		VCC								82	26		VCC
				A4						83	27		A5
				A6						84	28		A7
				A8						85	29		A9
		A10								86	30		A11
		A12								87	31		A13
		A14								88	32		A15
		A16								89	33		NC
		NC								90	34		NC
		VSS								91	35		VSS
DIRTYD										92	36		DIRTYQ
	TDQ0									93	37		TDQ1
	TDQ2									94	38		TDQ3
	TDQ4									95	39		TDQ5
		VSS								96	40		VSS
	TDQ6									97	41		TDQ7*
	VALID									98	42		TDQ8**
			TE							99	43		ALE
		TWE								100	44		WE0
		VCC								101	45		VCC
		VSS								102	46		VSS
		TG								103	47		WE1
DIRTYWE										104	48		WE2
	DIRTYE									105	49		WE3
		VCC								106	50		VCC
		G0								107	51		G1
				E0						108	52
													E1
		PD0								109	53		PD1
		PD2								110	54		PD3
		PD4								111	55		NC
		VSS								112	56		VSS

MCM32A732/764•MCM32A832/864•MCM32A932/964	MOTOROLA FAST SRAM
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486 256KB CACHE MODULE BLOCK DIAGRAM

WITH 9 TAG BITS

E0

G0

LCA3

LCA2

DQ0 ± DQ7

DQ8 ± DQ15

DQ16 ± DQ23

DQ24 ± DQ31

DIRTYQ

DIRTYD

DIRTYWE

ALE

A4 ± A17 TDQ0 ± TDQ8 VALID TWE

	32K x 8
	A2 ± A14
	DQ0 ± DQ7
	W
	A0	W0
	A1
E	G
	32K x 8
	A2 ± A14
	DQ0 ± DQ7
	W
	A0	W1
	A1
E	G
	32K x 8
	A2 ± A14
	DQ0 ± DQ7
	W
	A0	W2
	A1
E	G
	32K x 8
	A2 ± A14
	DQ0 ± DQ7
	W
	A0	W3
	A1
E	G
	8
	8
	8
	8
		74F373
	14

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

A1

G E

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

A1

G E

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

A1

G E

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

A1

G E

A0 ± A13

16K x 1

Dout

Din

W

A0 ± A13

DQ0 ± DQ8

DQ9

16K x 10

W

E1

G1

HCA3

HCA2

DIRTYE

TE

TG

MOTOROLA FAST SRAM	MCM32A732/764•MCM32A832/864•MCM32A932/964
	3

E0

G0

LCA3

LCA2

DQ0 ± DQ7

DQ8 ± DQ15

DQ16 ± DQ23

DQ24 ± DQ31

DIRTYQ

DIRTYD

DIRTYWE

ALE

A4 ± A17 TDQ0 ± TDQ8 VALID TWE

486 128KB CACHE MODULE BLOCK DIAGRAM

WITH 9 TAG BITS

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

W0

A1

E

G

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

W1

A1

E

G

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

W2

A1

E

G

32K x 8

A2 ± A14

DQ0 ± DQ7

W

A0

W3

A1

E

G

NC

NC

NC

NC

A0 ± A12

8K x 1

Dout

Din

W

74F373

A0 ± A12

DQ0 ± DQ8

DQ9

8K x 10

W

E1

G1

HCA3

HCA2

DIRTYE

TE

TG

MCM32A732/764•MCM32A832/864•MCM32A932/964	MOTOROLA FAST SRAM
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