Microchip Technology Inc 93LCS66T-I-SN, 93LCS66T-I-SM, 93LCS66T-I-SL, 93LCS66T-I-P, 93LCS66T-SN Datasheet

93LCS56/66

2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect

FEATURES

•Single supply with programming operation down to 2.5V

•Low power CMOS technology

-1 mA active current typical

-5 A standby current (typical) at 3.0V

•x16 memory organization

-128x16 (93LCS56)

-256x16 (93LCS66)

•Software write protection of user defined memory space

•Self timed erase and write cycles

•Automatic ERAL before WRAL

•Power on/off data protection

•Industry standard 3-wire serial I/O

•Device status signal during E/W

•Sequential READ function

•1,000,000 E/W cycles guaranteed

•Data retention > 200 years

•8-pin PDIP/SOIC and 14-pin SOIC packages

•Temperature ranges supported

-	Commercial (C):	0˚C	to	+70˚C
-	Industrial (I):	-40˚C	to	+85˚C

BLOCK DIAGRAM

	VCC	VSS
	MEMORY		ADDRESS
	ARRAY		DECODER
			ADDRESS
			COUNTER
	DATA REGISTER		OUTPUT	DO
			BUFFER
DI
PRE	MODE
	DECODE
PE
	LOGIC
CS

CLOCK

CLK

GENERATOR

DESCRIPTION

The Microchip Technology Inc. 93LCS56/66 are low voltage Serial Electrically Erasable PROMs with memory capacities of 2K bits/4K bits respectively. A write protect register is included in order to provide a user defined region of write protected memory. All memory locations greater than or equal to the address placed in the write protect register will be protected from any attempted write or erase operation. It is also possible to protect the address in the write protect register permanently by using a one time only instruction (PRDS). Any attempt to alter data in a register whose address is equal to or greater than the address stored in the protect register will be aborted. Advanced CMOS technology makes this device ideal for low power non-volatile memory applications.

PACKAGE TYPES

																							SOIC
																		NC				1	14			NC
																						2	13
																		CS								VCC
																						3	12
				DIP									SOIC					CLK								PRE
CS			1		8				VCC	CS		1		8			VCC	NC				4	11			NC
			2		7					CLK		2		7			PRE					5	10
CLK									PRE									DI								PE
			3		6					DI		3		6			PE
DI									PE									DO				6	9			VSS
			4		5					DO		4		5			VSS
DO									VSS									NC				7	8			NC
			93LCS56									93LCS56										93LCS56
			93LCS66									93LCS66										93LCS66

Microwire is a registered trademark of National Semiconductor Incorporated.

1996 Microchip Technology Inc.

Preliminary

DS11181D-page 1

93LCS56/66

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. VSS ...............	-0.6V to VCC +1.0V
Storage temperature .....................................		-65˚C to +150˚C
Ambient temp. with power applied ................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins................................................		4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name	Function
CS	Chip Select
CLK	Serial Data Clock
DI	Serial Data Input
DO	Serial Data Output
VSS	Ground
PE	Program Enable
PRE	Protect Register Enable
VCC	Power Supply

TABLE 1-2:	DC AND AC ELECTRICAL CHARACTERISTICS
		VCC = +2.5V to +6.0V
		Commercial(C): Tamb = 0˚C to +70˚C
		Industrial (I):		Tamb = -40˚C to +85˚C
Parameter		Symbol		Min	Max		Units	Conditions
High level input voltage		VIH		2.0	VCC +1		V	VCC ≥ 2.5V
Low level input voltage		VIL		-0.3	0.8		V	VCC ≥ 2.5V
Low level output voltage		VOL1		—	0.4		V	I OL = 2.1 mA; VCC = 4.5V
		VOL2		—	0.2		V	I OL = 100 A; VCC = 2.5V
High level output voltage		VOH1		2.4	—		V	I OH = -400 A; VCC = 4.5V
		VOH2		VCC-0.2	—		V	I OH = -100 A; VCC = 2.5V
Input leakage current		ILI		-10	10		A	VIN = 0.1V to VCC
Output leakage current		ILO		-10	10		A	VOUT = 0.1V to Vcc
Pin capacitance		CIN, COUT		—	7		pF	V IN/VOUT = 0V (Note 1 & 2)
(all inputs/outputs)								Tamb = +25˚C; FCLK = 1 MHz
Operating current		ICC Write		—	3		mA	F CLK = 2 MHz; VCC = 3.0V (Note 2)
		ICC Read		—	1		mA	FCLK = 2 MHz; VCC = 6.0V
					500		A	FCLK = 1 MHz; VCC = 3.0V
Standby current		ICCS		—	100		A	CLK = CS = 0V; VCC = 6.0V
					30		A	CLK = CS = 0V; VCC = 3.0V
Clock frequency		FCLK		—	2		MHz	VCC ≥ 4.5V
					1		MHz	VCC < 4.5V
Clock high time		TCKH		250	—		ns
Clock low time		TCKL		250	—		ns
Chip select setup time		TCSS		50	—		ns	Relative to CLK
Chip select hold time		TCSH		0	—		ns	Relative to CLK
Chip select low time		TCSL		250	—		ns
PRE setup time		TPRES		100	—		ns	Relative to CLK
PE setup time		TPES		100	—		ns	Relative to CLK
PRE hold time		TPREH		0	—		ns	Relative to CLK
PE hold time		TPEH		500	—		ns	Relative to CLK
Data input setup time		TDIS		100	—		ns	Relative to CLK
Data input hold time		TDIH		100	—		ns	Relative to CLK
Data output delay time		TPD		—	400		ns	CL=100 pF
Data output disable time		TCZ		—	100		ns	CL=100 pF (Note 2)

Note 1: This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested.

DS11181D-page 2

Preliminary

1996 Microchip Technology Inc.

							93LCS56/66
TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS							(Continued)
	VCC = +2.5V to +6.0V
	Commercial(C): Tamb = 0˚C to +70˚C
	Industrial (I):		Tamb = -40˚C to +85˚C
Parameter	Symbol		Min	Max		Units	Conditions
Status valid time	TSV			500		ns	CL=100 pF
Program cycle time	TWC			10		ms	ERASE/WRITE mode (Note 3)
	TEC			15		ms	ERAL mode
	TWL			30		ms	WRAL mode
Endurance	—		1M	—		cycles	25 °C, Vcc = 5.0V, Block Mode
							(Note 4)

3:Typical program cycle time is 4 ms per word.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

TABLE 1-3:

INSTRUCTION SET FOR 93LCS56*/66

93LCS56/66 (x 16 organization)

Instruction

SB

Opcode

Address

Data In

Data Out

PRE

PE

Comments

READ

1

10

A7 - A0

—

D15-D0

0

X

Reads data stored in memory, start-

ing at specified address (.Note).

EWEN

1

00

11XXXXXX

—

High-Z

0

1

Erase/Write Enable must precede all

programming modes.

ERASE

1

11

A7 - A0

—

(RDY/

1

Erase data at specified address

BSY)

location if address is unprotected

(Note).

ERAL

1

00

10XXXXXX

—

(RDY/

0

1

Erase all registers to “FF”. Valid only

when Protect Register is cleared.

BSY)

WRITE

1

01

A7 - A0*

D15 - D0

(RDY/

0

1

Writes register if address is unpro-

BSY)

tected.

WRAL

1

00

01XXXXXX

D15 - D0

(RDY/

0

1

Writes all registers. Valid only when

Protect Register is cleared.

BSY)

EWDS

1

00

00XXXXXX

—

High-Z

0

X

Erase/Write Disable deactivates all

programming instructions.

PRREAD

1

10

XXXXXXXX

—

A7-A0

1

X

Reads address stored in Protect

Register.

PREN

1

00

11XXXXXX

—

High-Z

1

1

Must immediately precede

PRCLEAR, PRWRITE and PRDS

instructions.

PRCLEAR

1

11

11111111

—

(RDY/

1

1

Clears the Protect Register such that

all data are NOT write-protected.

BSY)

PRWRITE

1

01

A7 - A0*

—

(RDY/

1

1

Programs address into Protect Reg-

BSY)

ister. Thereafter, memory addresses

greater than or equal to the address

in Protect Register are write-pro-

tected.

PRDS

1

00

00000000

—

(RDY/

1

1

ONE TIME ONLY instruction after

BSY)

which the address in the Protect

Register cannot be altered.

Note: Address A7 bit is a “don’t care” on 93LCS56.

1996 Microchip Technology Inc.

Preliminary

DS11181D-page 3

93LCS56/66

2.0FUNCTIONAL DESCRIPTION

The 93LCS56/66 is organized as 128/256 registers by 16 bits. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the ready/busy status during a programming operation. The ready/busy status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS.

2.1START Condition

The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time.

Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and PRDS). As soon as CS is HIGH, the device is no longer in the standby mode.

An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected.

2.2DI/DO

It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation, if A0 is a logic HIGH level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin.

2.3Data Protection

During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V.

The EWEN and EWDS commands give additional protection against accidentally programming during normal operation.

After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.

2.4READ

The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16 bit output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially.

2.5Erase/Write Enable and Disable (EWEN, EWDS)

The 93LCS56/66 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction.

The PE pin MUST be held “high” while loading the EWEN instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/ Write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.

2.6ERASE

The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The PE pin MUST be latched “high” during loading the ERASE instruction but becomes a “don't care” after loading the instruction.

The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCLS). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. ERASE instruction is valid if specified address is unprotected.

The ERASE cycle takes 4 ms per word typical.

2.7WRITE

The WRITE instruction is followed by 16 bits of data which are written into the specified address. After the last data bit is put on the DI pin, CS must be brought low before the next rising edge of the CLK clock. Both CS and CLK must be low to initiate the self-timed autoerase and programming cycle. The PE pin MUST be latched “high” while loading the WRITE instruction but becomes a “don't care” thereafter.

DS11181D-page 4

Preliminary

1996 Microchip Technology Inc.