62X.bk Page 1 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
OTP 8-Bit CMOS MCU with EEPROM Data Memory
Devices included in this data sheet:
•PIC16CE623
•PIC16CE624
•PIC16CE625
High Performance RISC CPU:
•Only 35 instructions to learn
•All single-cycle instructions (200 ns), except for program branches which are two-cycle
•Operating speed:
-DC - 20 MHz clock input
-DC - 200 ns instruction cycle
Device |
Program |
RAM |
EEPROM |
|
Memory |
Data |
Data |
|
|
Memory |
Memory |
|
|
|
|
|
|
|
|
PIC16CE623 |
512x14 |
96x8 |
128x8 |
|
|
|
|
PIC16CE624 |
1Kx14 |
96x8 |
128x8 |
|
|
|
|
PIC16CE625 |
2Kx14 |
128x8 |
128x8 |
|
|
|
|
•Interrupt capability
•16 special function hardware registers
•8-level deep hardware stack
•Direct, Indirect and Relative addressing modes
Peripheral Features:
•13 I/O pins with individual direction control
•High current sink/source for direct LED drive
•Analog comparator module with:
-Two analog comparators
-Programmable on-chip voltage reference (VREF) module
-Programmable input multiplexing from device inputs and internal voltage reference
-Comparator outputs can be output signals
•Timer0: 8-bit timer/counter with 8-bit programmable prescaler
Special Microcontroller Features:
•In-Circuit Serial Programming (ICSP™) (via two pins)
•Power-on Reset (POR)
•Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
•Brown-out Reset
•Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
RA2/AN2/VREF |
•1 |
PIC16CE62X |
18 |
RA1/AN1 |
RB2 |
8 |
11 |
RB5 |
|
RA3/AN3 |
2 |
|
17 |
RA0/AN0 |
RA4/T0CKI |
3 |
|
16 |
OSC1/CLKIN |
MCLR |
4 |
|
15 |
OSC2/CLKOUT |
VSS |
5 |
|
14 |
VDD |
RB0/INT |
6 |
|
13 |
RB7 |
RB1 |
7 |
|
12 |
RB6 |
RB3 |
9 |
|
10 |
RB4 |
SSOP |
|
|
|
|
RA2/AN2/VREF |
•1 |
PIC16CE62X |
20 |
RA1/AN1 |
RA3/AN3 |
2 |
19 |
RA0/AN0 |
|
RA4/T0CKI |
3 |
|
18 |
OSC1/CLKIN |
MCLR |
4 |
|
17 |
OSC2/CLKOUT |
VSS |
5 |
|
16 |
VDD |
VSS |
6 |
|
15 |
VDD |
RB0/INT |
7 |
|
14 |
RB7 |
RB1 |
8 |
|
13 |
RB6 |
RB2 |
9 |
|
12 |
RB5 |
RB3 |
10 |
|
11 |
RB4 |
Special Microcontroller Features (cont’d)
•1,000,000 erase/write cycle EEPROM data memory
•EEPROM data retention > 40 years
•Programmable code protection
•Power saving SLEEP mode
•Selectable oscillator options
•Four user programmable ID locations
CMOS Technology:
•Low-power, high-speed CMOS EPROM/EEPROM technology
•Fully static design
•Wide operating voltage range
-3.0V to 5.5V
•Commercial, industrial and extended temperature range
•Low power consumption
-< 2.0 mA @ 5.0V, 4.0 MHz
-15 A typical @ 3.0V, 32 kHz
-< 1.0 A typical standby current @ 3.0V
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 1
62X.bk Page 2 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X |
|
|
Table of Contents |
|
|
1.0 |
General Description ..................................................................................................................................................................... |
3 |
2.0 |
PIC16CE62X Device Varieties .................................................................................................................................................... |
5 |
3.0 |
Architectural Overview ................................................................................................................................................................ |
7 |
4.0 |
Memory Organization ................................................................................................................................................................ |
11 |
5.0 |
I/O Ports .................................................................................................................................................................................... |
23 |
6.0 |
EEPROM Peripheral Operation ................................................................................................................................................. |
29 |
7.0 |
Timer0 Module .......................................................................................................................................................................... |
35 |
8.0 |
Comparator Module ................................................................................................................................................................... |
41 |
9.0 |
Voltage Reference Module ........................................................................................................................................................ |
47 |
10.0 |
Special Features of the CPU ..................................................................................................................................................... |
49 |
11.0 |
Instruction Set Summary ........................................................................................................................................................... |
65 |
12.0 |
Development Support ................................................................................................................................................................ |
77 |
13.0 |
Electrical Specifications ............................................................................................................................................................. |
81 |
14.0 |
Packaging Information ............................................................................................................................................................... |
93 |
Appendix A: Code for Accessing EEPROM Data Memory ............................................................................................................. |
99 |
|
Index |
.................................................................................................................................................................................................. |
101 |
PIC16CE62X ......................................................................................................................................Product Identification System |
105 |
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and product. As in any conversion process, information may have accidently been altered or deleted. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error from the previous version of this data sheet (PIC16CE62X Data Sheet, Literature Number DS40182A), please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS40182A-page 2 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 3 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
1.0GENERAL DESCRIPTION
The PIC16CE62X are 18 and 20 Pin EPROM-based members of the versatile PICmicro™ family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with EEPROM data memory.
All PICmicro™ m icrocontrollers employ an advanced RISC architecture. The PIC16CE62X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.
PIC16CE62X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.
The PIC16CE623 and PIC16CE624 have 96 bytes of RAM. The PIC16CE625 has 128 bytes of RAM. Each microcontroller contains a 128x8 EEPROM memory array for storing non-volatile information such as calibration data or security codes. This memory has an endurance of 1,000,000 erase/write cycles and a retention of 40 plus years.
Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, the PIC16CE62X adds two analog comparators with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc).
PIC16CE62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake up the chip from SLEEP through several external and internal interrupts and reset.
A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.
A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume.
Table 1-1 shows the features of the PIC16CE62X mid-range microcontroller families.
A simplified block diagram of the PIC16CE62X is shown in Figure 3-1.
The PIC16CE62X series fit perfectly in applications ranging from multi-pocket battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O flexibility make the PIC16CE62X very versatile.
1.1Development Support
The PIC16CE62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A “C”compiler and fuzzy logic support tools are also available.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 3
62X.bk Page 4 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
TABLE 1-1: |
PIC16CE62X FAMILY OF DEVICES |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PIC16CE623 |
|
PIC16CE624 |
|
PIC16CE625 |
|
|
|
|
|
|
|
Clock |
Maximum Frequency |
20 |
|
20 |
|
20 |
of Operation (MHz) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
EPROM Program |
512 |
|
1K |
|
2K |
Memory |
Memory |
|
|
|
|
|
(x14 words) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Data Memory (bytes) |
96 |
|
96 |
|
128 |
|
EEPROM Data Memory (bytes) |
128 |
|
128 |
|
128 |
|
|
|
|
|
|
|
|
Timer Module(s) |
TMR0 |
|
TMR0 |
|
TMR0 |
Peripherals |
|
|
|
|
|
|
Comparators(s) |
2 |
|
2 |
|
2 |
|
|
|
|
|
|
|
|
|
Internal Reference |
Yes |
|
Yes |
|
Yes |
|
Voltage |
|
|
|
|
|
|
Interrupt Sources |
4 |
|
4 |
|
4 |
|
|
|
|
|
|
|
|
I/O Pins |
13 |
|
13 |
|
13 |
|
|
|
|
|
|
|
|
Voltage Range (Volts) |
3.0-5.5 |
|
3.0-5.5 |
|
3.0-5.5 |
Features |
|
|
|
|
|
|
Brown-out Reset |
Yes |
|
Yes |
|
Yes |
|
|
|
|
||||
|
|
|
|
|
|
|
|
Packages |
18-pin DIP, |
|
18-pin DIP, |
|
18-pin DIP, |
|
|
SOIC; |
|
SOIC; |
|
SOIC; |
|
|
20-pin SSOP |
|
20-pin SSOP |
|
20-pin SSOP |
|
|
|
|
|
|
|
All PICmicro™ F amily devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40182A-page 4 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 5 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
2.0PIC16CE62X DEVICE VARIETIES
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16CE62X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.
2.1UV Erasable Devices
The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.
Microchip's PICSTART and PRO MATE programmers both support programming of the PIC16CE62X.
2.2One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.
2.3Quick-Turn-Programming (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.4Serialized Quick-Turn-Programming (SQTPSM) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 5
62X.bk Page 6 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
DS40182A-page 6 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 7 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
3.0ARCHITECTURAL OVERVIEW
The high performance of the PIC16CE62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CE62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a sin- gle-cycle (200 ns @ 20 MHz) except for program branches.
The PIC16CE623 addresses 512 x 14 on-chip program memory. The PIC16CE624 addresses 1K x 14 program memory. The PIC16CE625 addresses 2K x 14 program memory. All program memory is internal.
The PIC16CE62X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CE62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CE62X simple yet efficient. In addition, the learning curve is reduced significantly.
The PIC16CE62X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.
The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 7
62X.bk Page 8 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 3-1: |
BLOCK DIAGRAM |
|
|
|
|||
|
|
|
|
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|
|
|
|
Device |
Program Memory |
Data Memory |
EEPROM DATA |
|
||
|
|
(RAM) |
|
MEMORY |
|
||
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||
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|
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|
|
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|
|
|
|
|
|
|
|
PIC16CE623 |
512 X 14 |
96 |
X 8 |
128 |
X 8 |
|
|
PIC16CE624 |
1K X14 |
96 |
X 8 |
128 |
X 8 |
|
|
PIC16CE625 |
2K X 14 |
128 X 8 |
128 |
X 8 |
|
|
|
|
|
|
|
|
|
|
|
13 |
Data Bus |
8 |
|
Program Counter |
|
|
|
|
|
|
EPROM |
|
|
|
Program |
8 Level Stack |
RAM |
|
Memory |
|
||
(13-bit) |
File |
|
|
|
|
||
|
|
Registers |
|
Program |
14 |
RAM Addr (1) |
9 |
Bus |
Instruction reg |
|
|
|
Addr MUX |
|
|
|
|
|
|
|
|
Direct Addr |
7 |
|
8 |
Indirect |
|
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|
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Addr |
|
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|
|
FSR reg |
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STATUS reg |
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|
3 |
MUX |
|
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Power-up |
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||
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Timer |
|
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|
Instruction |
Oscillator |
|
|
|
|
Decode & |
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|
ALU |
|
|
Start-up Timer |
|
|
|
||
Control |
|
|
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||
|
|
|
|
|
|
|
Power-on |
|
|
|
|
Timing |
Reset |
|
|
W reg |
|
Generation |
Watchdog |
|
|
|
|
|
|
|
|
||
OSC1/CLKIN |
|
|
|
|
|
Timer |
|
|
|
|
|
OSC2/CLKOUT |
Brown-out |
|
|
|
|
|
|
|
|
|
|
|
Reset |
|
|
|
|
MCLR VDD, VSS
Note 1: Higher order bits are from the STATUS register.
Voltage
Reference
Comparator |
|
|
RA0/AN0 |
- |
RA1/AN1 |
|
|
+ |
RA2/AN2/VREF |
|
|
- |
RA3/AN3 |
+ |
|
TMR0 |
|
|
RA4/T0CKI |
I/O Ports
PORTB |
SCL |
SDA |
EEPROM |
|
Data |
||
|
||
VDD |
Memory |
|
128x8 |
EEINTF
DS40182A-page 8 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 9 Tuesday, March 10, 1998 3:40 PM
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PIC16CE62X |
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TABLE 3-1: |
PIC16CE62X PINOUT DESCRIPTION |
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|||||||||
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Name |
|
DIP/ |
SSOP |
|
I/O/P |
|
Buffer |
|
Description |
|
||
|
SOIC |
|
|
|
|
|||||||
|
Pin # |
|
Type |
|
Type |
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|||||
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Pin # |
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OSC1/CLKIN |
|
16 |
18 |
|
I |
|
ST/CMOS |
Oscillator crystal input/external clock source input. |
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|||
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|
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|||
OSC2/CLKOUT |
|
15 |
17 |
|
O |
|
— |
Oscillator crystal output. Connects to crystal or resonator |
|
|||
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|
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in crystal oscillator mode. In RC mode, OSC2 pin outputs |
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CLKOUT which has 1/4 the frequency of OSC1, and |
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|
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denotes the instruction cycle rate. |
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||
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4 |
4 |
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I/P |
|
ST |
Master clear (reset) input/programming voltage input. |
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|
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MCLR/VPP |
|||||||||||
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This pin is an active low reset to the device. |
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PORTA is a bi-directional I/O port. |
|
|
RA0/AN0 |
|
17 |
19 |
|
I/O |
|
ST |
|
Analog comparator input |
|
||
RA1/AN1 |
|
18 |
20 |
|
I/O |
|
ST |
|
Analog comparator input |
|
||
|
RA2/AN2/VREF |
|
1 |
1 |
|
I/O |
|
ST |
|
Analog comparator input or VREF output |
|
|
RA3/AN3 |
|
2 |
2 |
|
I/O |
|
ST |
|
Analog comparator input /output |
|
||
RA4/T0CKI |
|
3 |
3 |
|
I/O |
|
ST |
|
Can be selected to be the clock input to the Timer0 |
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||
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timer/counter or a comparator output. Output is open |
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drain type. |
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PORTB is a bi-directional I/O port. PORTB can be |
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software programmed for internal weak pull-up on all |
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inputs. |
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RB0/INT |
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6 |
7 |
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I/O |
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TTL/ST(1) |
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RB0/INT can also be selected as an external |
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interrupt pin. |
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RB1 |
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7 |
8 |
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I/O |
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TTL |
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RB2 |
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8 |
9 |
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I/O |
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TTL |
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RB3 |
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9 |
10 |
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I/O |
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TTL |
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RB4 |
|
10 |
11 |
|
I/O |
|
TTL |
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Interrupt on change pin. |
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RB5 |
|
11 |
12 |
|
I/O |
|
TTL |
|
Interrupt on change pin. |
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||
RB6 |
|
12 |
13 |
|
I/O |
|
TTL/ST(2) |
|
Interrupt on change pin. Serial programming clock. |
|
||
RB7 |
|
13 |
14 |
|
I/O |
|
TTL/ST(2) |
|
Interrupt on change pin. Serial programming data. |
|
||
VSS |
|
5 |
5,6 |
|
P |
|
— |
Ground reference for logic and I/O pins. |
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VDD |
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14 |
15,16 |
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P |
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— |
Positive supply for logic and I/O pins. |
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Legend: |
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O = output |
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I/O = input/output |
P = power |
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— = Not used |
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I = Input |
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ST = Schmitt Trigger input |
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TTL = TTL input |
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Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 9
62X.bk Page 10 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
3.1Clocking Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
3.2Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC) incrementing in Q1.
In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
Q1 |
Q2 |
Q3 |
Q4 |
Q1 |
Q2 |
Q3 |
Q4 |
Q1 |
Q2 |
Q3 |
Q4 |
OSC1 |
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Q1 |
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Q2 |
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Internal |
Q3 |
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phase |
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clock |
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Q4 |
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PC |
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PC |
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PC+1 |
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PC+2 |
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OSC2/CLKOUT |
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(RC mode) |
Fetch INST (PC) |
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Execute INST (PC-1) |
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Fetch INST (PC+1) |
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Execute INST (PC) |
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Fetch INST (PC+2) |
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Execute INST (PC+1) |
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EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. |
MOVLW |
55h |
Fetch 1 |
Execute 1 |
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2. |
MOVWF |
PORTB |
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Fetch 2 |
Execute 2 |
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3. |
CALL |
SUB_1 |
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Fetch 3 |
Execute 3 |
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4. |
BSF |
PORTA, BIT3 |
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Fetch 4 |
Flush |
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5. |
Instruction @ |
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Fetch SUB_1 |
Execute SUB_1 |
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address SUB_1 |
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All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40182A-page 10 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 11 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.0MEMORY ORGANIZATION
4.1Program Memory Organization
The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16CE623, 1K x 14 (0000h - 03FFh) for the PIC16CE624 and 2K x 14 (0000h - 07FFh) for the PIC16CE625 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 space (PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K x 14 space (PIC16CE625). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).
FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE623
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PC<12:0> |
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CALL, RETURN |
13 |
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RETFIE, RETLW |
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Stack Level 1 |
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Stack Level 2 |
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Stack Level 8 |
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Reset Vector |
000h |
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Interrupt Vector |
0004 |
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0005 |
On-chip Program |
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Memory |
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01FFh |
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0200h |
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1FFFh |
FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE624
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PC<12:0> |
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CALL, RETURN |
13 |
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RETFIE, RETLW |
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Stack Level 1 |
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Stack Level 2 |
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Stack Level 8 |
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Reset Vector |
000h |
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Interrupt Vector |
0004 |
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0005 |
On-chip Program |
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Memory |
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03FFh |
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0400h |
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1FFFh |
FIGURE 4-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE625
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PC<12:0> |
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CALL, RETURN |
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13 |
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RETFIE, RETLW |
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Stack Level 1 |
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Stack Level 2 |
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Stack Level 8 |
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Reset Vector |
000h |
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Interrupt Vector |
0004 |
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0005 |
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On-chip Program |
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Memory |
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07FFh |
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0800h |
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1FFFh
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 11
62X.bk Page 12 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.2Data Memory Organization
The data memory (Figure 4-4 and Figure 4-5) is partitioned into two Banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-7Fh (Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16CE625 are general purpose registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. In all three microcontrollers, address space F0h-FFh is mapped to 70-7Fh.
4.2.1GENERAL PURPOSE REGISTER FILE
The register file is organized as 96 x 8 in the PIC16CE623/624 and 128 x 8 in the PIC16CE625. Each is accessed either directly or indirectly through the File Select Register FSR (Section 4.4).
DS40182A-page 12 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 13 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
FIGURE 4-4: DATA MEMORY MAP FOR THE PIC16CE623/624
File |
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File |
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Address |
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Address |
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00h |
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INDF(1) |
INDF(1) |
80h |
01h |
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TMR0 |
OPTION |
81h |
02h |
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PCL |
PCL |
82h |
03h |
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STATUS |
STATUS |
83h |
04h |
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FSR |
FSR |
84h |
05h |
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PORTA |
TRISA |
85h |
06h |
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PORTB |
TRISB |
86h |
07h |
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87h |
08h |
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88h |
09h |
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89h |
0Ah |
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PCLATH |
PCLATH |
8Ah |
0Bh |
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INTCON |
INTCON |
8Bh |
0Ch |
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PIR1 |
PIE1 |
8Ch |
0Dh |
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8Dh |
0Eh |
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PCON |
8Eh |
0Fh |
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8Fh |
10h |
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EEINTF |
90h |
11h |
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91h |
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12h |
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92h |
13h |
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93h |
14h |
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94h |
15h |
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95h |
16h |
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96h |
17h |
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97h |
18h |
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98h |
19h |
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99h |
1Ah |
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9Ah |
1Bh |
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9Bh |
1Ch |
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9Ch |
1Dh |
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9Dh |
1Eh |
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9Eh |
1Fh |
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CMCON |
VRCON |
9Fh |
20h |
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A0h |
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General |
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Purpose |
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Register |
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EFh |
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Accesses |
F0h |
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70h-7Fh |
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7Fh |
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FFh |
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Bank 0 |
Bank 1 |
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Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
FIGURE 4-5: DATA MEMORY MAP FOR THE PIC16CE625
File |
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File |
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Address |
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Address |
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00h |
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INDF(1) |
INDF(1) |
80h |
01h |
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TMR0 |
OPTION |
81h |
02h |
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PCL |
PCL |
82h |
03h |
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STATUS |
STATUS |
83h |
04h |
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FSR |
FSR |
84h |
05h |
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PORTA |
TRISA |
85h |
06h |
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PORTB |
TRISB |
86h |
07h |
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87h |
08h |
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88h |
09h |
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89h |
0Ah |
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PCLATH |
PCLATH |
8Ah |
0Bh |
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INTCON |
INTCON |
8Bh |
0Ch |
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PIR1 |
PIE1 |
8Ch |
0Dh |
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8Dh |
0Eh |
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PCON |
8Eh |
0Fh |
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8Fh |
10h |
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EEINTF |
90h |
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11h |
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91h |
12h |
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92h |
13h |
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93h |
14h |
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94h |
15h |
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95h |
16h |
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96h |
17h |
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97h |
18h |
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98h |
19h |
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99h |
1Ah |
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9Ah |
1Bh |
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9Bh |
1Ch |
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9Ch |
1Dh |
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9Dh |
1Eh |
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9Eh |
1Fh |
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CMCON |
VRCON |
9Fh |
20h |
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A0h |
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General |
General |
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Purpose |
Purpose |
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Register |
Register |
BFh |
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C0h |
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F0h |
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Accesses |
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70h-7Fh |
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7Fh |
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FFh |
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Bank 0 |
Bank 1 |
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Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 13
62X.bk Page 14 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.2.2SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM.
The special registers can be classified into two sets (core and peripheral). The special function registers associated with the “core”functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1: |
SPECIAL REGISTERS FOR THE PIC16CE62X |
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Value on |
Value on all |
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Address |
Name |
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Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
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Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
POR/BOR |
other |
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Reset |
resets(1) |
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Bank 0 |
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00h |
INDF |
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Addressing this location uses contents of FSR to address data memory (not a physical |
xxxx xxxx |
xxxx xxxx |
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register) |
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01h |
TMR0 |
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Timer0 Module’s Register |
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xxxx xxxx |
uuuu uuuu |
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02h |
PCL |
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Program Counter's (PC) Least Significant Byte |
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0000 |
0000 |
0000 |
0000 |
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03h |
STATUS |
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IRP(2) |
RP1(2) |
RP0 |
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TO |
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PD |
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Z |
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DC |
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C |
0001 |
1xxx |
000q |
quuu |
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04h |
FSR |
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Indirect data memory address pointer |
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xxxx xxxx |
uuuu uuuu |
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05h |
PORTA |
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— |
— |
— |
RA4 |
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RA3 |
RA2 |
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RA1 |
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RA0 |
---x 0000 |
---u 0000 |
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06h |
PORTB |
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RB7 |
RB6 |
RB5 |
RB4 |
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RB3 |
RB2 |
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RB1 |
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RB0 |
xxxx xxxx |
uuuu uuuu |
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07h |
Unimplemented |
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— |
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— |
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08h |
Unimplemented |
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— |
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— |
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09h |
Unimplemented |
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— |
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— |
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0Ah |
PCLATH |
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— |
— |
— |
Write buffer for upper 5 bits of program counter |
---0 0000 |
---0 0000 |
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0Bh |
INTCON |
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GIE |
PEIE |
T0IE |
INTE |
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RBIE |
T0IF |
INTF |
RBIF |
0000 |
000x |
0000 |
000x |
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0Ch |
PIR1 |
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— |
CMIF |
— |
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— |
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— |
— |
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— |
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— |
-0-- ---- |
-0-- ---- |
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0Dh-1Eh |
Unimplemented |
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— |
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— |
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1Fh |
CMCON |
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C2OUT |
C1OUT |
— |
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— |
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CIS |
CM2 |
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CM1 |
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CM0 |
00-- 0000 |
00-- 0000 |
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Bank 1 |
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80h |
INDF |
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Addressing this location uses contents of FSR to address data memory (not a physical |
xxxx xxxx |
xxxx xxxx |
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register) |
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81h |
OPTION |
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RBPU |
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INTEDG |
T0CS |
T0SE |
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PSA |
PS2 |
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PS1 |
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PS0 |
1111 1111 |
1111 1111 |
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82h |
PCL |
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Program Counter's (PC) Least Significant Byte |
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0000 0000 |
0000 0000 |
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83h |
STATUS |
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IRP |
RP1 |
RP0 |
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TO |
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PD |
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Z |
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DC |
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C |
0001 1xxx |
000q quuu |
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84h |
FSR |
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Indirect data memory address pointer |
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xxxx xxxx |
uuuu uuuu |
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85h |
TRISA |
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— |
— |
— |
TRISA4 |
TRISA3 |
TRISA2 |
TRISA1 |
TRISA0 |
---1 1111 |
---1 1111 |
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86h |
TRISB |
|
TRISB7 |
TRISB6 |
TRISB5 |
TRISB4 |
TRISB3 |
TRISB2 |
TRISB1 |
TRISB0 |
1111 1111 |
1111 1111 |
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87h |
Unimplemented |
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— |
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— |
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88h |
Unimplemented |
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— |
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— |
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89h |
Unimplemented |
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— |
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— |
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8Ah |
PCLATH |
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— |
— |
— |
Write buffer for upper 5 bits of program counter |
---0 0000 |
---0 0000 |
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8Bh |
INTCON |
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GIE |
PEIE |
T0IE |
INTE |
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RBIE |
T0IF |
INTF |
RBIF |
0000 000x |
0000 000x |
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8Ch |
PIE1 |
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— |
CMIE |
— |
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— |
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— |
— |
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— |
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— |
-0-- ---- |
-0-- ---- |
|||||||
8Dh |
Unimplemented |
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— |
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— |
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8Eh |
PCON |
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— |
— |
— |
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— |
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— |
— |
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POR |
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BOR |
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---- --0x |
---- --uq |
|||||
8Fh-9Eh |
Unimplemented |
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— |
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— |
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90h |
EEINTF |
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— |
— |
— |
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— |
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— |
EESCL |
EESDA |
EEVDD |
uuuu u111 |
uuuu u111 |
|||||||||
9Fh |
VRCON |
|
|
VREN |
VROE |
VRR |
|
— |
|
VR3 |
VR2 |
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VR1 |
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VR0 |
0000000 |
0000000 |
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Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
Note 2: IRP & RPI bits are reserved, always maintain these bits clear.
DS40182A-page 14 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 15 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.2.2.1STATUS REGISTER
The STATUS register, shown in Figure 4-6, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the “Instruction Set Summary”.
Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16CE62X and should be programmed as ’0'.Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products.
Note 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 4-6: STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved |
Reserved |
R/W-0 |
R-1 |
R-1 |
R/W-x |
R/W-x |
R/W-x |
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|
||||
IRP |
RP1 |
RP0 |
|
TO |
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PD |
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Z |
DC |
C |
|
R = Readable bit |
bit7 |
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bit0 |
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W = Writable bit |
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U = Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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-x = Unknown at POR reset |
bit 7: IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5 RP1: RPO: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
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bit |
4: |
TO: Time-out bit |
||||||||
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1 |
= After power-up, CLRWDT instruction, or SLEEP instruction |
|||||||
|
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0 |
= A WDT time-out occurred |
|||||||
bit |
3: |
|
: Power-down bit |
|||||||
PD |
||||||||||
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|
1 |
= After power-up or by the CLRWDT instruction |
|||||||
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0 |
= By execution of the SLEEP instruction |
|||||||
bit |
2: |
Z: Zero bit |
||||||||
|
|
1 |
= The result of an arithmetic or logic operation is zero |
|||||||
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0 |
= The result of an arithmetic or logic operation is not zero |
|||||||
bit |
1: |
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||
DC: Digit carry/borrow |
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) |
|||||||||
|
|
1 |
= A carry-out from the 4th low order bit of the result occurred |
|||||||
|
|
0 |
= No carry-out from the 4th low order bit of the result |
|||||||
bit |
0: |
|
|
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) |
||||||
C: Carry/borrow |
||||||||||
|
|
1 |
= A carry-out from the most significant bit of the result occurred |
|||||||
|
|
0 |
= No carry-out from the most significant bit of the result occurred |
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 15
62X.bk Page 16 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.2.2.2OPTION REGISTER
The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB.
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1).
FIGURE 4-7: OPTION REGISTER (ADDRESS 81H)
|
R/W-1 |
|
|
R/W-1 |
|
R/W-1 |
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|
R/W-1 |
|
R/W-1 |
R/W-1 |
R/W-1 |
R/W-1 |
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|||||||
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|
RBPU |
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|
INTEDG |
|
T0CS |
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|
T0SE |
|
PSA |
PS2 |
PS1 |
|
PS0 |
|
R |
= Readable bit |
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|||||
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bit7 |
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bit0 |
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W |
= Writable bit |
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- n = Value at POR reset |
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bit 7: |
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: PORTB Pull-up Enable bit |
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RBPU |
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1 |
= PORTB pull-ups are disabled |
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0 |
= PORTB pull-ups are enabled by individual port latch values |
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bit |
6: |
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INTEDG: Interrupt Edge Select bit |
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1 |
= Interrupt on rising edge of RB0/INT pin |
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0 |
= Interrupt on falling edge of RB0/INT pin |
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bit |
5: |
|
T0CS: TMR0 Clock Source Select bit |
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1 |
= Transition on RA4/T0CKI pin |
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0 |
= Internal instruction cycle clock (CLKOUT) |
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bit |
4: |
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T0SE: TMR0 Source Edge Select bit |
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1 |
= Increment on high-to-low transition on RA4/T0CKI pin |
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0 |
= Increment on low-to-high transition on RA4/T0CKI pin |
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bit |
3: |
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PSA: Prescaler Assignment bit |
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1 |
= Prescaler is assigned to the WDT |
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0 |
= Prescaler is assigned to the Timer0 module |
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bit |
2-0: |
PS2:PS0: Prescaler Rate Select bits |
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Bit Value |
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TMR0 Rate WDT Rate |
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000 |
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1 : |
2 |
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1 |
: 1 |
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001 |
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1 : |
4 |
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1 |
: 2 |
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010 |
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1 : |
8 |
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1 |
: 4 |
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011 |
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1 : |
16 |
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1 |
: 8 |
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100 |
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1 : |
32 |
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1 |
: 16 |
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101 |
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1 : |
64 |
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1 |
: 32 |
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110 |
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1 : |
128 |
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1 |
: 64 |
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111 |
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1 : |
256 |
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1 |
: 128 |
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DS40182A-page 16 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 17 Tuesday, March 10, 1998 3:40 PM
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PIC16CE62X |
||
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4.2.2.3 |
INTCON REGISTER |
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|||||||||
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Note: Interrupt flag bits get set when an interrupt |
|||||||||||||||
The |
INTCON register |
is a |
readable |
and |
writable |
|
condition occurs regardless of the state of |
|||||||||||||
|
its corresponding enable bit or the global |
|||||||||||||||||||
register which contains the various enable and flag bits |
|
|||||||||||||||||||
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enable bit, GIE (INTCON<7>). |
|||||||||||||||||||
for all interrupt sources except the comparator module. |
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|||||||||||||||||||
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|||||||||||||||
See |
Section 4.2.2.4 |
and |
Section 4.2.2.5 |
for |
a |
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|
|||||||||
description of the comparator enable and flag bits. |
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||||||||||||
FIGURE 4-8: INTCON REGISTER (ADDRESS 0BH OR 8BH) |
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|||||||||||||||
|
R/W-0 |
|
|
R/W-0 |
R/W-0 |
|
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-x |
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|||||
|
|
GIE |
|
|
PEIE |
|
T0IE |
|
INTE |
RBIE |
|
T0IF |
|
INTF |
RBIF |
|
R |
= Readable bit |
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bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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-x = Unknown at POR reset |
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bit 7: |
|
GIE: Global Interrupt Enable bit |
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|||||||
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1 |
= Enables all un-masked interrupts |
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0 |
= Disables all interrupts |
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|||||
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bit |
6: |
|
PEIE: Peripheral Interrupt Enable bit |
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||||||||
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1 |
= Enables all un-masked peripheral interrupts |
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0 |
= Disables all peripheral interrupts |
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bit |
5: |
|
T0IE: TMR0 Overflow Interrupt Enable bit |
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||||||||
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1 |
= Enables the TMR0 interrupt |
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||||||
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0 |
= Disables the TMR0 interrupt |
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||||||
|
bit |
4: |
|
INTE: RB0/INT External Interrupt Enable bit |
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||||||||||
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|
|
1 |
= Enables the RB0/INT external interrupt |
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||||||||||
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0 |
= Disables the RB0/INT external interrupt |
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||||||||||
|
bit |
3: |
|
RBIE: RB Port Change Interrupt Enable bit |
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||||||||||
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1 |
= Enables the RB port change interrupt |
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||||||||
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0 |
= Disables the RB port change interrupt |
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||||||||||
|
bit |
2: |
|
T0IF: TMR0 Overflow Interrupt Flag bit |
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||||||||
|
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|
1 |
= TMR0 register has overflowed (must be cleared in software) |
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||||||||||||
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0 |
= TMR0 register did not overflow |
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||||||
|
bit |
1: |
|
INTF: RB0/INT External Interrupt Flag bit |
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||||||||
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|
1 |
= The RB0/INT external interrupt occurred (must be cleared in software) |
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||||||||||||||
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0 |
= The RB0/INT external interrupt did not occur |
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||||||||||
|
bit |
0: |
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RBIF: RB Port Change Interrupt Flag bit |
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1 |
= When at least one of the RB7:RB4 pins changed state (must be cleared in software) |
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= None of the RB7:RB4 pins have changed state |
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1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 17
62X.bk Page 18 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.2.2.4PIE1 REGISTER
This register contains the individual enable bit for the comparator interrupt.
FIGURE 4-9: PIE1 REGISTER (ADDRESS 8CH)
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U-0 |
R/W-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
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— |
CMIE |
— |
— |
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— |
— |
— |
— |
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R |
= Readable bit |
bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n |
= Value at POR reset |
bit 7: |
Unimplemented: Read as '0' |
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bit |
6: |
CMIE: Comparator Interrupt Enable bit |
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1 = Enables the Comparator interrupt |
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0 = Disables the Comparator interrupt |
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bit |
5-0: Unimplemented: Read as '0' |
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4.2.2.5PIR1 REGISTER
This register contains the individual flag bit for the comparator interrupt.
Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)
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R/W-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
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— |
CMIF |
— |
— |
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— |
— |
— |
— |
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R |
= Readable bit |
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bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n |
= Value at POR reset |
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bit 7: |
Unimplemented: Read as '0' |
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bit |
6: |
CMIF: Comparator Interrupt Flag bit |
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1 = Comparator input has changed |
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0 = Comparator input has not changed |
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bit |
5-0: Unimplemented: Read as '0' |
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DS40182A-page 18 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 19 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.2.2.6PCON REGISTER
The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset, WDT reset or a Brown-out Reset.
Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the Configuration word).
FIGURE 4-11: PCON REGISTER (ADDRESS 8Eh)
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U-0 |
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U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
R/W-0 |
R/W-0 |
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— |
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— |
— |
— |
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— |
— |
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R |
= Readable bit |
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POR |
BOR |
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bit7 |
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bit0 |
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= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7-2: |
Unimplemented: Read as '0' |
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bit |
1: |
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: Power-on Reset Status bit |
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1 |
= No Power-on Reset occurred |
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0 |
= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) |
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bit |
0: |
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: Brown-out Reset Status bit |
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BOR |
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1 |
= No Brown-out Reset occurred |
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0 |
= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) |
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1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 19
62X.bk Page 20 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.3PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-12 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-12: LOADING OF PC IN DIFFERENT SITUATIONS
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PCH |
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PCL |
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12 |
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8 |
7 |
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0 |
Instruction with |
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PC |
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PCL as |
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5 |
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PCLATH<4:0> |
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8 |
Destination |
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ALU result |
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PCLATH |
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PCH |
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PCL |
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12 |
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10 |
8 |
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7 |
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0 |
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PC |
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GOTO, CALL |
2 |
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PCLATH<4:3> |
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11 |
Opcode <10:0> |
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PCLATH |
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4.3.1COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note “Implementing aTable Read" (AN556).
4.3.2STACK
The PIC16CE62X family has an 8 level deep x 13-bit wide hardware stack (Figure 4-2 and Figure 4-3). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions.
Note 2: There are no instruction mnemonics called PUSH or POP. These are actions that occur from the execution of the
CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
DS40182A-page 20 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 21 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
4.4Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-13. However, IRP is not used in the PIC16CE62X.
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: INDIRECT ADDRESSING
|
movlw |
0x20 |
;initialize pointer |
|
movwf |
FSR |
;to RAM |
NEXT |
clrf |
INDF |
;clear INDF register |
|
incf |
FSR |
;inc pointer |
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btfss |
FSR,4 |
;all done? |
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goto |
NEXT |
;no clear next |
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;yes continue |
CONTINUE: |
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FIGURE 4-13: DIRECT/INDIRECT ADDRESSING PIC16CE62X
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Direct Addressing |
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Indirect Addressing |
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(1)RP1 RP0 |
6 |
from opcode |
0 |
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IRP(1) |
7 |
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FSR register |
0 |
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bank select |
location select |
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00 |
01 |
10 |
11 |
bank select |
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location select |
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00h |
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00h |
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not used
Data Memory
7Fh |
7Fh |
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Bank 0 |
Bank 1 Bank 2 Bank 3 |
For memory map detail see Figure 4-4 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 21
62X.bk Page 22 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
NOTES:
DS40182A-page 22 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 23 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
5.0I/O PORTS
The PIC16CE62X parts have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
5.1PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output.
A '1' in theTRISA register puts the corresponding output driver in a hiimpedance mode. A '0' in theTRISA register puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch.
The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as '0's.
FIGURE 5-1: BLOCK DIAGRAM OF RA1:RA0 PINS
Data
bus D Q
WR |
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VDD |
PortA |
CK |
Q |
P |
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Data Latch |
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D |
Q |
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WR |
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N |
I/O Pin |
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TRISA |
CK |
Q |
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TRIS Latch |
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VSS |
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Analog |
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Input Mode |
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Schmitt Trigger |
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RD TRISA |
Input Buffer |
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Q |
D |
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EN |
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RD PORTA |
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To Comparator
Note: I/O pins have protection diodes to VDD and VSS.
Note: On reset, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.
TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs.
The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high impedance output. The user must configure TRISA<2> bit as an input and use high impedance loads.
In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.
EXAMPLE 5-1: INITIALIZING PORTA
CLRF |
PORTA |
;Initialize PORTA by setting |
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;output data latches |
MOVLW |
0X07 |
;Turn comparators off and |
MOVWF |
CMCON |
;enable pins for I/O |
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;functions |
BSF |
STATUS, RP0 ;Select Bank1 |
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MOVLW |
0x1F |
;Value used to initialize |
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;data direction |
MOVWF |
TRISA |
;Set RA<4:0> as inputs |
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;TRISA<7:5> are always |
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;read as '0'. |
FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN
Data |
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bus |
D |
Q |
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WR |
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VDD |
PortA |
CK |
Q |
P |
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Data Latch |
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D |
Q |
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WR |
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N |
RA2 Pin |
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TRISA |
CK |
Q |
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TRIS Latch |
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VSS |
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Analog |
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Input Mode |
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Schmitt Trigger |
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RD TRISA |
Input Buffer |
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Q |
D |
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EN |
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RD PORTA |
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To Comparator |
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VROE |
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VREF |
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Note: I/O pins have protection diodes to VDD and VSS.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 23
62X.bk Page 24 Tuesday, March 10, 1998 3:40 PM |
|
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|||
PIC16CE62X |
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FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN |
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Data |
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Comparator Mode = 110 |
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bus |
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D |
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Q |
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WR |
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Comparator Output |
VDD |
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PortA |
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CK |
Q |
P |
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D |
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Q |
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WR |
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N |
RA3 Pin |
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TRISA |
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CK |
Q |
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TRIS Latch |
VSS |
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Analog |
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Input Mode |
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Schmitt Trigger |
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RD TRISA |
Input Buffer |
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Q |
D |
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EN |
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RD PORTA |
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To Comparator |
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Note: |
I/O pins have protection diodes to VDD and VSS |
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FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN |
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Data |
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Comparator Mode = 110 |
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bus |
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D |
Q |
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WR |
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Comparator Output |
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PortA |
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CK |
Q |
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Data Latch |
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D |
Q |
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WR |
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N |
RA4 Pin |
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TRISA |
CK |
Q |
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TRIS Latch |
VSS |
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Schmitt Trigger |
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RD TRISA |
Input Buffer |
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Q |
D |
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EN |
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RD PORTA |
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TMR0 Clock Input |
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Note: |
RA4 has protection diodes to VSS only |
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DS40182A-page 24 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 25 Tuesday, March 10, 1998 3:40 PM
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PIC16CE62X |
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TABLE 5-1: |
PORTA FUNCTIONS |
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Name |
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Bit # |
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Buffer |
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Function |
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Type |
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RA0/AN0 |
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bit0 |
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ST |
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Input/output or comparator input |
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RA1/AN1 |
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bit1 |
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ST |
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Input/output or comparator input |
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RA2/AN2/VREF |
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bit2 |
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ST |
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Input/output or comparator input or VREF output |
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RA3/AN3 |
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bit3 |
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ST |
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Input/output or comparator input/output |
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RA4/T0CKI |
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bit4 |
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ST |
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Input/output or external clock input for TMR0 or comparator output. |
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Output is open drain type. |
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Legend: ST = Schmitt Trigger input |
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TABLE 5-2: |
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA |
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Value on: |
Value on |
Address |
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Name |
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Bit 7 |
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Bit 6 |
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Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
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All Other |
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POR / BOR |
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Resets |
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05h |
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PORTA |
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— |
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— |
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— |
RA4 |
RA3 |
RA2 |
RA1 |
RA0 |
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---x 0000 |
---u 0000 |
||
85h |
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TRISA |
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— |
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— |
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— |
TRISA4 |
TRISA3 |
TRISA2 |
TRISA1 |
TRISA0 |
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---1 1111 |
---1 1111 |
||
1Fh |
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CMCON |
C2OUT |
C1OUT |
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— |
— |
CIS |
CM2 |
CM1 |
CM0 |
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00-- 0000 |
00-- 0000 |
||||
9Fh |
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VRCON |
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VREN |
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VROE |
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VRR |
— |
VR3 |
VR2 |
VR1 |
VR0 |
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0000000 |
0000000 |
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Legend: — = Unimplemented locations , read as ‘0’
Note: Note: Shaded bits are not used by PORTA.
1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 25
62X.bk Page 26 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
5.2PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in theTRISB register puts the contents of the output latch on the selected pin(s).
Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up (≈200 A typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch”outputs of RB7:RB4 are OR’ed together to generate the RBIF interrupt (flag latched in INTCON<0>).
FIGURE 5-5: BLOCK DIAGRAM OF RB7:RB4 PINS
VDD
RBPU(2) |
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P |
weak |
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pull-up |
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Data bus |
Data Latch |
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D |
Q |
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WR PortB |
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I/O |
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CK |
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pin(1) |
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TRIS Latch |
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D |
Q |
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WR TRISB |
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CK |
TTL |
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Input |
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Buffer |
ST |
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Buffer |
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RD TRISB |
Latch |
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Q |
D |
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Set RBIF |
RD PortB |
EN |
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From other |
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Q |
D |
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RB7:RB4 pins |
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EN |
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RD Port |
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RB7:RB6 in serial programming mode |
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Note 1: I/O pins have diode protection to VDD and VSS.
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).
This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:
a)Any read or write of PORTB. This will end the mismatch condition.
b)Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.)
Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-6: BLOCK DIAGRAM OF RB3:RB0 PINS
VDD
RBPU(2) |
weak |
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P |
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pull-up |
Data bus |
Data Latch |
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D |
Q |
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WR PortB |
CK |
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I/O |
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pin(1) |
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D |
Q |
TTL |
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WR TRISB |
CK |
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Input |
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Buffer |
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RD TRISB |
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Q |
D |
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RD PortB |
EN |
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RB0/INT |
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ST |
RD Port |
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Buffer |
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Note 1: I/O pins have diode protection to VDD and VSS.
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).
DS40182A-page 26 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 27 Tuesday, March 10, 1998 3:40 PM
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PIC16CE62X |
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TABLE 5-3: |
PORTB FUNCTIONS |
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Name |
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Bit # |
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Buffer Type |
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Function |
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RB0/INT |
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bit0 |
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TTL/ST(1) |
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Input/output or external interrupt input. Internal software programmable |
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weak pull-up. |
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RB1 |
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bit1 |
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TTL |
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Input/output pin. Internal software programmable weak pull-up. |
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RB2 |
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bit2 |
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TTL |
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Input/output pin. Internal software programmable weak pull-up. |
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RB3 |
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bit3 |
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TTL |
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Input/output pin. Internal software programmable weak pull-up. |
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RB4 |
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bit4 |
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TTL |
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Input/output pin (with interrupt on change). Internal software |
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programmable weak pull-up. |
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RB5 |
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bit5 |
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TTL |
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Input/output pin (with interrupt on change). Internal software |
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programmable weak pull-up. |
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RB6 |
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bit6 |
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TTL/ST(2) |
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Input/output pin (with interrupt on change). Internal software |
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programmable weak pull-up. Serial programming clock pin. |
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RB7 |
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bit7 |
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TTL/ST(2) |
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Input/output pin (with interrupt on change). Internal software |
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programmable weak pull-up. Serial programming data pin. |
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Legend: ST = Schmitt Trigger, TTL = TTL input |
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Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. |
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Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. |
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TABLE 5-4: |
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB |
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Value on: |
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Value on |
Address |
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Name |
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Bit 7 |
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Bit 6 |
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Bit 5 |
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Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
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Bit 0 |
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All Other |
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POR / BOR |
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Resets |
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06h |
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PORTB |
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RB7 |
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RB6 |
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RB5 |
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RB4 |
RB3 |
RB2 |
RB1 |
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RB0 |
xxxx xxxx |
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uuuu uuuu |
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86h |
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TRISB |
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TRISB7 |
TRISB6 |
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TRISB5 |
TRISB4 |
TRISB3 |
TRISB2 |
TRISB1 |
TRISB0 |
1111 1111 |
|
1111 1111 |
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81h |
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OPTION |
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INTEDG |
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T0CS |
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T0SE |
PSA |
PS2 |
PS1 |
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PS0 |
1111 1111 |
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1111 1111 |
|||
RBPU |
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Note: |
Shaded bits are not used by PORTB. |
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u = unchanged |
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x = unknown |
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1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 27
62X.bk Page 28 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
5.3I/O Programming Considerations
5.3.1BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.
Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.
Example 5-2 shows the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port.
A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”,“wired-and”). The resulting high output currents may damage the chip.
EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
; Initial PORT settings: PORTB<7:4> Inputs
; |
|
; |
PORTB<3:0> Outputs |
;PORTB<7:6> have external pull-up and are not
;connected to other circuitry
; |
|
|
; |
PORT latch |
PORT pins |
; |
---------- |
---------- |
BCF PORTB, 7 |
; 01pp pppp |
11pp pppp |
BCF PORTB, 6 |
; 10pp pppp |
11pp pppp |
BSF STATUS,RP0 |
; |
|
BCF TRISB, 7 |
; 10pp pppp |
11pp pppp |
BCF TRISB, 6 |
; 10pp pppp |
10pp pppp |
; |
|
|
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
5.3.2SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-7). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.
FIGURE 5-7: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC |
PC |
PC + 1 |
PC + 2 |
PC + 3 |
|
Instruction |
MOVWF PORTB |
MOVF PORTB, W |
NOP |
NOP |
|
fetched |
|||||
Write to |
Read PORTB |
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PORTB |
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RB7:RB0 |
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RB <7:0> |
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Port pin |
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TPD |
sampled here |
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Execute |
Execute |
Execute |
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MOVWF |
MOVF |
NOP |
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PORTB |
PORTB, W |
|
Note:
This example shows write to PORTB followed by a read from PORTB.
Note that:
data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40182A-page 28 |
Preliminary |
1998 Microchip Technology Inc. |
62X.bk Page 29 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
6.0EEPROM PERIPHERAL OPERATION
The PIC16CE623/624/625 each have 128 bytes of EEPROM data memory. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit1 and bit2, respectively, of the EEINTF register (SFR 90h). In addition, the power to the EEPROM can be controlled using bit0 (EEVDD) of the EEINTF register. For most applications, all that is required is calls to the following functions:
; Byte_Write: Byte write routine |
|
|
; |
Inputs: EEPROM Address |
EEADDR |
; |
EEPROM Data |
EEDATA |
;Outputs: Return 01 in W if OK, else
return 00 in W
;
;Read_Current: Read EEPROM at address currently held by EE device.
;Inputs: NONE
; |
Outputs: |
EEPROM Data |
EEDATA |
||
; |
|
Return |
01 |
in W if OK, else |
|
|
|
return |
00 |
in W |
|
;
; Read_Random: Read EEPROM byte at supplied address
;
;
;
The code for these functions is not yet determined, but will be available on our web site (www.microchip.com) when it is completed. The code will be accessed by either including the source code FLASH62X.INC or by linking FLASH62X.ASM.
6.0.1SERIAL DATA
SDA is a bi-directional pin used to transfer addresses and data into and data out of the memory.
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
6.0.2SERIAL CLOCK
This SCL input is used to synchronize the data transfer from and to the memory.
6.0.3EEINTF REGISTER
The EEINTF register (SFR 90h) controls the access to the EEPROM. Figure 6.1 details the function of each bit. User code must generate the clock and data signals.
FIGURE 6-1: EEINFT REGISTER (ADDRESS 90h)
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U-0 |
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U-0 |
U-0 |
U-0 |
U-0 |
R/W-1 |
R/W-1 |
R/W-1 |
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EESCL |
EESDA |
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EEVDD |
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= Readable bit |
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bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7-3: |
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Unimplemented: Read as '0' |
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EESCL: Clock line to the EEPROM |
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1 |
= Clock high |
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0 |
= Clock low |
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1: |
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EESDA: Data line to EEPROM |
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= Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor) |
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= Data line is low |
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0: |
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EEVDD: VDD control bit for EEPROM |
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1 |
= VDD is turned on EEPROM |
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= VDD is turned off EEPROM (all pins are tri-stated and the EEPROM is powered down) |
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Note: |
EESDA, EESCL and EEVDD will read ‘0’ if EEVDD is turned off |
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1998 Microchip Technology Inc. |
Preliminary |
DS40182A-page 29
62X.bk Page 30 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
6.1BUS CHARACTERISTICS
In this section, the term “processor”refers to the portion of the PIC16CE62X that interfaces to the EEPROM through software manipulating the EEINTF register. The following bus protocol is to be used with the EEPROM data memory.
•Data transfer may be initiated only when the bus is not busy.
•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted by the EEPROM as a START or STOP condition.
Accordingly, the following bus conditions have been defined (Figure 6-2).
6.1.1BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
6.1.2START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
6.1.3STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
6.1.4DATA VALID (D)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the processor and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in, first-out fashion.
6.1.5ACKNOWLEDGE
The EEPROM will generate an acknowledge after the reception of each byte. The processor must generate an extra clock pulse which is associated with this acknowledge bit.
Note: Acknowledge bits are not generated if an internal programming cycle is in progress.
When the EEPROM acknowledges, it pulls down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. The processor must signal an end of data to the EEPROM by not generating an acknowledge bit on the last byte that has been clocked out of the EEPROM. In this case, the EEPROM must leave the data line HIGH to enable the processor to generate the STOP condition (Figure 6-3).
DS40182A-page 30 |
Preliminary |
1998 Microchip Technology Inc. |