Microchip Technology Inc 24LC128-E-SM, 24LC128-E-P, 24LC128T-E-ST, 24LC128T-E-SN, 24LC128T-E-SM Datasheet

M 24AA128/24LC128

128K I2C™ CMOS Serial EEPROM

DEVICE SELECTION TABLE

Part	VCC	Max Clock	Temp
Number	Range	Frequency	Ranges
24AA128	1.8-5.5V	400 kHz†	I
24LC128	2.5-5.5V	400 kHz‡	I, E

† 100 kHz for VCC < 2.5V.

‡ 100 kHz for E temperature range.

FEATURES

•Low power CMOS technology

-Maximum write current 3 mA at 5.5V

-Maximum read current 400 A at 5.5V

-Standby current 100 nA typical at 5.5V

•2-wire serial interface bus, I2C compatible

•Cascadable for up to eight devices

•Self-timed ERASE/WRITE cycle

•64-byte page-write mode available

•5 ms max write-cycle time

•Hardware write protect for entire array

•Output slope control to eliminate ground bounce

•Schmitt trigger inputs for noise suppression

•1,000,000 erase/write cycles guaranteed

•Electrostatic discharge protection > 4000V

•Data retention > 200 years

•8-pin PDIP and SOIC (150 and 208 mil) packages

•14-pin TSSOP package

•Temperature ranges:

-	Industrial (I):	-40°C	to	+85°C
-	Automotive (E):	-40°C	to	+125°C

DESCRIPTION

The Microchip Technology Inc. 24AA128/24LC128 (24xx128*) is a 16K x 8 (128K bit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 128K boundary. Functional address lines allow up to eight devices on the same bus, for up to 1M bit address space. This device is available in the standard 8-pin plastic DIP, 8-pin SOIC (150 and 208 mil), and 14-pin TSSOP packages.

PACKAGE TYPE

PDIP
	A0					1					24xx128		8						Vcc
	A1					2							7						WP
	A2					3							6						SCL
SOIC	Vss					4							5						SDA
	A0								1		24xx128		8						VCC
									2				7
	A1																		WP
									3				6						SCL
	A2
													5						SDA
TSSOP	VSS								4
	A0								1				14					Vcc
	A1																	WP
									2		24xx128		13
	NC								3				12					NC
	NC																	NC
									4				11
	NC																	NC
									5				10
	A2								6				9					SCL
	Vss												8					SDA
									7

BLOCK DIAGRAM

		A0…A2	WP		HV GENERATOR
	I/O	MEMORY			EEPROM
	CONTROL	CONTROL		XDEC
					ARRAY
	LOGIC		LOGIC
					PAGE LATCHES
	I/O
	SCL
					YDEC
	SDA
	VCC
	VSS				SENSE AMP
					R/W CONTROL

I2C is a trademark of Philips Corporation.

*24xx128 is used in this document as a generic part number for the 24AA128/24LC128 devices.

1998 Microchip Technology Inc.

DS21191B-page 1

24AA128/24LC128

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC.................................................................................................	7.0V
All inputs and outputs w.r.t. VSS .............................	-0.6V to VCC +1.0V
Storage temperature ...................................................	-65°C to +150°C
Ambient temp. with power applied...............................	-65°C to +125°C
Soldering temperature of leads (10 seconds) ...........................	+300°C
ESD protection on all pins...........................................................	≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1	PIN FUNCTION TABLE
Name	Function
A0, A1, A2	User Configurable Chip Selects
VSS	Ground
SDA	Serial Data
SCL	Serial Clock
WP	Write Protect Input
VCC	+1.8 to 5.5V (24AA128)
	+2.5 to 5.5V (24LC128)

TABLE 1-2	DC CHARACTERISTICS
All parameters apply across the		Industrial (I):		VCC = +1.8V to 5.5V			Tamb = -40°C to +85°C
specified operating ranges, unless		Automotive (E): VCC = +4.5V to 5.5V					Tamb = -40°C to 125°C
otherwise noted.
Parameter		Symbol		Min	Max	Units			Conditions
A0, A1, A2, SCL, SDA, and WP
pins:
High level input voltage		VIH		0.7 VCC	—	V
Low level input voltage		VIL		—	0.3 V CC	V			VCC ≥ 2.5V
					0.2 VCC	V			VCC < 2.5V
Hysteresis	of Schmitt Trigger	VHYS	0.05 VCC		—	V			V CC ≥ 2.5V (Note)
inputs (SDA, SCL pins)
Low level output voltage		VOL		—	0.40	V		I OL = 3.0 mA @ VCC = 4.5V
									IOL = 2.1 mA @ VCC = 2.5V
Input leakage current		ILI		-10	10	A			VIN = VSS or VCC, WP = VSS
									VIN = VSS or VCC, WP = VCC
Output leakage current		ILO		-10	10	A			VOUT = VSS or VCC
Pin capacitance		CIN, COUT		—	10	pF		V CC = 5.0V (Note)
(all inputs/outputs)									Tamb = 25°C, fc= 1 MHz
Operating current		ICC Read		—	400	A			VCC = 5.5V, SCL = 400 kHz
		ICC Write		—	3	mA		V CC = 5.5V
Standby current		ICCS		—	1	A			SCL = SDA = VCC = 5.5V
									A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING DATA

	TF	THIGH		VHYS	TR
SCL	TSU:STA
	TLOW	THD:DAT	TSU:DAT		TSU:STO
SDA	THD:STA
IN
	TSP
			TAA			TBUF
SDA
OUT
WP			(protected)		TSU:WP	THD:WP
			(unprotected)

DS21191B-page 2

1998 Microchip Technology Inc.

24AA128/24LC128

TABLE 1-3	AC CHARACTERISTICS
All parameters apply across the spec-		Industrial (I):		VCC = +1.8V to 5.5V			Tamb = -40°C to +85°C
ified operating ranges unless other-		Automotive (E): VCC = +4.5V to 5.5V						°	°
wise noted.							Tamb = -40 C to 125 C
Parameter		Symbol		Min	Max	Units		Conditions
Clock frequency		FCLK		—	100	kHz	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				—	100		1.8V	≤ VCC ≤ 2.5V
				—	400		2.5V	≤ VCC ≤ 5.5V
Clock high time		THIGH		4000	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4000	—		1.8V	≤ VCC ≤ 2.5V
				600	—		2.5V	≤ VCC ≤ 5.5V
Clock low time		TLOW		4700	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4700	—		1.8V	≤ VCC ≤ 2.5V
				1300	—		2.5V	≤ VCC ≤ 5.5V
SDA and SCL rise time		TR		—	1000	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
(Note 1)				—	1000		1.8V	≤ VCC ≤ 2.5V
				—	300		2.5V	≤ VCC ≤ 5.5V
SDA and SCL fall time		TF		—	300	ns	(Note 1)
START condition hold time		THD:STA		4000	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4000	—		1.8V	≤ VCC ≤ 2.5V
				600	—		2.5V	≤ VCC ≤ 5.5V
START condition setup time		TSU:STA		4700	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4700	—		1.8V	≤ VCC ≤ 2.5V
				600	—		2.5V	≤ VCC ≤ 5.5V
Data input hold time		THD:DAT		0	—	ns	(Note 2)
Data input setup time		TSU:DAT		250	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				250	—		1.8V	≤ VCC ≤ 2.5V
				100	—		2.5V	≤ VCC ≤ 5.5V
STOP condition setup time		TSU:STO		4000	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4000	—		1.8V	≤ VCC ≤ 2.5V
				600	—		2.5V	≤ VCC ≤ 5.5V
WP setup time		TSU:WP		4000	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4000	—		1.8V	≤ VCC ≤ 2.5V
				600	—		2.5V	≤ VCC ≤ 5.5V
WP hold time		THD:WP		4700	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
				4700	—		1.8V	≤ VCC ≤ 2.5V
				1300	—		2.5V	≤ VCC ≤ 5.5V
Output valid from clock		TAA		—	3500	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
(Note 2)				—	3500		1.8V	≤ VCC ≤ 2.5V
				—	900		2.5V	≤ VCC ≤ 5.5V
Bus free time: Time the bus must be		TBUF		4700	—	ns	4.5V	≤ VCC ≤ 5.5V (E Temp range)
free before a new transmission can				4700	—		1.8V	≤ VCC ≤ 2.5V
start				1300	—		2.5V	≤ VCC ≤ 5.5V
Output fall time from VIH		TOF		10	250	ns	CB ≤ 100 pF (Note 1)
minimum to VIL maximum
Input filter spike suppression		TSP		—	50	ns	(Notes 1 and 3)
(SDA and SCL pins)
Write cycle time (byte or page)		TWC		—	5	ms
Endurance				1M	—	cycles	25 °C, VCC = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

1998 Microchip Technology Inc.

DS21191B-page 3

24AA128/24LC128

2.0PIN DESCRIPTIONS

2.1A0, A1, A2 Chip Address Inputs

The A0, A1, A2 inputs are used by the 24xx128 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true.

Up to eight devices may be connected to the same bus by using different chip select bit combinations. If left unconnected, these inputs will be pulled down internally to VSS.

2.2SDA Serial Data

This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz)

For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

2.3SCL Serial Clock

This input is used to synchronize the data transfer from and to the device.

2.4WP

This pin can be connected to either VSS, VCC or left floating. An internal pull-down resistor on this pin will keep the device in the unprotected state if left floating. If tied to VSS or left floating, normal memory operation is enabled (read/write the entire memory 0000-3FFF).

If tied to VCC, WRITE operations are inhibited. Read operations are not affected.

3.0FUNCTIONAL DESCRIPTION

The 24xx128 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions while the 24xx128 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated.

4.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

4.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must end with a STOP condition.

4.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.

4.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24xx128 does not generate any acknowledge bits if an internal programming cycle is in progress.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24xx128) will leave the data line HIGH to enable the master to generate the STOP condition.

DS21191B-page 4

1998 Microchip Technology Inc.