MPIC16C72 SERIES
8-Bit CMOS Microcontrollers with A/D Converter
Devices included:
•PIC16C72
•PIC16CR72
Microcontroller Core Features:
•High-performance RISC CPU
•Only 35 single word instructions to learn
•All single cycle instructions except for program branches which are two cycle
•Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
•2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
•Interrupt capability
•Eight level deep hardware stack
•Direct, indirect, and relative addressing modes
•Power-on Reset (POR)
•Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
•Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
•Programmable code-protection
•Power saving SLEEP mode
•Selectable oscillator options
•Low-power, high-speed CMOS technology
•Fully static design
•Wide operating voltage range:
-2.5V to 6.0V (PIC16C72)
-2.5V to 5.5V (PIC16CR72)
•High Sink/Source Current 25/25 mA
•Commercial, Industrial and Extended temperature ranges
•Low-power consumption:
-< 2 mA @ 5V, 4 MHz
-15 A typical @ 3V, 32 kHz
-< 1 A typical standby current
Pin Diagrams
SDIP, SOIC, SSOP,
Windowed Side Brazed Ceramic
MCLR/VPP |
• 1 |
28 |
RB7 |
RA0/AN0 |
2 |
27 |
RB6 |
RA1/AN1 |
3 |
26 |
RB5 |
RA2/AN2 |
4 |
25 |
RB4 |
RA3/AN3/VREF |
5 |
24 |
RB3 |
RA4/T0CKI |
6 |
23 |
RB2 |
RA5/SS/AN4 |
7 |
22 |
RB1 |
VSS |
8 |
21 |
RB0/INT |
OSC1/CLKIN |
9 |
20 |
VDD |
OSC2/CLKOUT |
10 |
19 |
VSS |
RC0/T1OSO/T1CKI |
11 |
18 |
RC7 |
RC1/T1OSI |
12 |
17 |
RC6 |
RC2/CCP1 |
13 |
16 |
RC5/SDO |
RC3/SCK/SCL |
14 |
15 |
RC4/SDI/SDA |
PIC16C72
PIC16CR72
Peripheral Features:
•Timer0: 8-bit timer/counter with 8-bit prescaler
•Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock
•Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
•Capture, Compare, PWM (CCP) module
-Capture is 16-bit, max. resolution is 12.5 ns
-Compare is 16-bit, max. resolution is 200 ns
-PWM max. resolution is 10-bit
•8-bit 5-channel analog-to-digital converter
•Synchronous Serial Port (SSP) with SPI and I2C
•Brown-out detection circuitry for Brown-out Reset (BOR)
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 1
PIC16C72 Series |
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Table of Contents |
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1.0 |
Device Overview .......................................................................................................................................................................... |
3 |
2.0 |
Memory Organization ................................................................................................................................................................... |
5 |
3.0 |
I/O Ports ..................................................................................................................................................................................... |
19 |
4.0 |
Timer0 Module ........................................................................................................................................................................... |
25 |
5.0 |
Timer1 Module ........................................................................................................................................................................... |
27 |
6.0 |
Timer2 Module ........................................................................................................................................................................... |
31 |
7.0 |
Capture/Compare/PWM (CCP) Module ..................................................................................................................................... |
33 |
8.0 |
Synchronous Serial Port (SSP) Module ..................................................................................................................................... |
39 |
9.0 |
Analog - to - Digital Converter (A/D) Module .................................................................................................................................. |
53 |
10.0 |
Special Features of the CPU ...................................................................................................................................................... |
59 |
11.0 |
Instruction Set Summary ............................................................................................................................................................ |
73 |
12.0 |
Development Support ................................................................................................................................................................. |
75 |
13.0 |
Electrical Characteristics - PIC16C72 Series ............................................................................................................................. |
77 |
14.0 |
DC and AC Characteristics Graphs and Tables - PIC16C72 ..................................................................................................... |
97 |
15.0 |
DC and AC Characteristics Graphs and Tables - PIC16CR72 ................................................................................................ |
107 |
16.0 |
Packaging Information .............................................................................................................................................................. |
109 |
Appendix A: What’s New in this Data Sheet .................................................................................................................................. |
115 |
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Appendix B: What’s Changed in this Data Sheet ........................................................................................................................... |
115 |
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Appendix C: Device Differences..................................................................................................................................................... |
115 |
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Index |
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117 |
On-Line .................................................................................................................................................................................Support |
121 |
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Reader ..............................................................................................................................................................................Response |
122 |
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PIC16C72 ................................................................................................................................Series Product Identification System |
125 |
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Sales ..............................................................................................................................................................................and Support |
125 |
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
Key Reference Manual Features |
PIC16C72 |
PIC16CR72 |
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Operating Frequency |
DC - 20MHz |
DC - 20MHz |
Resets |
POR, PWRT, OST, BOR |
POR, PWRT, OST, BOR |
Program Memory - (14-bit words) |
2K (EPROM) |
2K (ROM) |
Data Memory - RAM (8-bit bytes) |
128 |
128 |
Interrupts |
8 |
8 |
I/O Ports |
PortA, PortB, PortC |
PortA, PortB, PortC |
Timers |
Timer0, Timer1, Timer2 |
Timer0, Timer1, Timer2 |
Capture/Compare/PWM Modules |
1 |
1 |
Serial Communications |
Basic SSP |
SSP |
8-Bit A/D Converter |
5 channels |
5 channels |
Instruction Set (No. of Instructions) |
35 |
35 |
DS39016A-page 2 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
1.0DEVICE OVERVIEW
This document contains device-specifi information for the operation of the PIC16C72 device. Additional information may be found in the PICmicro™ Mid-Range MCU Reference Manual (DS33023) which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
The PIC16C72 belongs to the Mid-Range family of the PICmicro devices. A block diagram of the device is shown in Figure 1-1.
FIGURE 1-1: PIC16C72/CR72 BLOCK DIAGRAM
The program memory contains 2K words which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes.
There are also 22 I/O pins that are user-configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include:
•External interrupt
•Change on PORTB interrupt
•Timer0 clock input
•Timer1 clock/oscillator
•Capture/Compare/PWM
•A/D converter
•SPI/I2C
Table 1-1 details the pinout of the device with descriptions and details for each pin.
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Data Bus |
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Program Counter |
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EPROM/ |
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ROM |
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Program |
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RAM |
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Memory |
8 Level Stack |
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2K x 14 |
File |
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Registers |
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Program |
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128 x 8 |
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RAM Addr(1) |
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9 |
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Bus |
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Addr MUX |
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Instruction reg |
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Direct Addr 7 |
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Indirect |
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Addr |
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FSR reg |
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8 |
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STATUS reg |
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Power-up |
3 |
MUX |
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Timer |
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Instruction |
Oscillator |
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Decode & |
Start-up Timer |
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ALU |
Control |
Power-on |
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8 |
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Reset |
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Timing |
Watchdog |
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W reg |
Generation |
Timer |
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OSC1/CLKIN |
Brown-out |
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OSC2/CLKOUT |
Reset |
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PORTA
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
PORTB
RB0/INT
RB7:RB1
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6 RC7
MCLR VDD, VSS
Timer0 |
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Timer1 |
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Timer2 |
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A/D |
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Synchronous |
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CCP1 |
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Serial Port |
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Note 1: Higher order bits are from the STATUS register.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 3
PIC16C72 Series
TABLE 1-1 |
PIC16C72/CR72 PINOUT DESCRIPTION |
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Pin Name |
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Pin# |
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I/O/P |
Buffer |
Description |
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Type |
Type |
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OSC1/CLKIN |
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9 |
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I |
ST/CMOS(3) |
Oscillator crystal input/external clock source input. |
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OSC2/CLKOUT |
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10 |
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O |
— |
Oscillator crystal output. Connects to crystal or resonator in crystal |
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oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which |
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has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. |
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1 |
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I/P |
ST |
Master clear (reset) input or programming voltage input. This pin is an |
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MCLR/VPP |
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active low reset to the device. |
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PORTA is a bi-directional I/O port. |
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RA0/AN0 |
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2 |
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I/O |
TTL |
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RA0 can also be analog input0. |
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RA1/AN1 |
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3 |
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I/O |
TTL |
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RA1 can also be analog input1. |
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RA2/AN2 |
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4 |
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I/O |
TTL |
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RA2 can also be analog input2. |
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RA3/AN3/VREF |
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I/O |
TTL |
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RA3 can also be analog input3 or analog reference voltage |
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RA4/T0CKI |
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I/O |
ST |
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RA4 can also be the clock input to the Timer0 module. Output is |
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open drain type. |
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7 |
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I/O |
TTL |
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RA5 can also be analog input4 or the slave select for the |
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RA5/SS/AN4 |
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synchronous serial port. |
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PORTB is a bi-directional I/O port. PORTB can be software |
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programmed for internal weak pull-up on all inputs. |
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RB0/INT |
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21 |
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I/O |
TTL/ST(1) |
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RB0 can also be the external interrupt pin. |
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RB1 |
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22 |
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I/O |
TTL |
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RB2 |
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23 |
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I/O |
TTL |
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RB3 |
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24 |
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I/O |
TTL |
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RB4 |
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25 |
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I/O |
TTL |
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Interrupt on change pin. |
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RB5 |
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26 |
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I/O |
TTL |
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Interrupt on change pin. |
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RB6 |
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27 |
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I/O |
TTL/ST(2) |
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Interrupt on change pin. Serial programming clock. |
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RB7 |
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28 |
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I/O |
TTL/ST(2) |
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Interrupt on change pin. Serial programming data. |
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PORTC is a bi-directional I/O port. |
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RC0/T1OSO/T1CKI |
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11 |
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I/O |
ST |
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RC0 can also be the Timer1 oscillator output or Timer1 clock |
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input. |
RC1/T1OSI |
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I/O |
ST |
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RC1 can also be the Timer1 oscillator input. |
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RC2/CCP1 |
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I/O |
ST |
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RC2 can also be the Capture1 input/Compare1 output/PWM1 |
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output. |
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RC3/SCK/SCL |
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I/O |
ST |
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RC3 can also be the synchronous serial clock input/output for both |
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SPI and I2C modes. |
RC4/SDI/SDA |
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I/O |
ST |
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RC4 can also be the SPI Data In (SPI mode) or |
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data I/O (I2C mode). |
RC5/SDO |
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16 |
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I/O |
ST |
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RC5 can also be the SPI Data Out (SPI mode). |
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RC6 |
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I/O |
ST |
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RC7 |
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I/O |
ST |
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VSS |
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8, 19 |
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— |
Ground reference for logic and I/O pins. |
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VDD |
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P |
— |
Positive supply for logic and I/O pins. |
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Legend: |
I = input |
O |
= output |
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I/O = input/output |
P = power |
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— = Not used |
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TTL = TTL input |
ST = Schmitt Trigger input |
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Note 1: |
This buffer is a Schmitt Trigger input when configured as the external interrupt. |
2:This buffer is a Schmitt Trigger input when used in serial programming mode.
3:This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS39016A-page 4 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
2.0MEMORY ORGANIZATION
There are two memory blocks in PIC16C72 Series devices. These are the program memory and the data memory. Each block has its own bus, so that access to both blocks can occur during the same oscillator cycle.
The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core”are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.
Additional information on device memory may be found in the PICmicro™ Mid-Range Ref erence Manual, DS33023.
2.1Program Memory Organization
PIC16C72 Series devices have a 13-bit program counter capable of addressing a 2K x 14 program memory space. The address range for this program memory is 0000h - 07FFh. Accessing a location above the physically implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
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PC<12:0> |
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CALL, RETURN |
13 |
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RETFIE, RETLW |
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Stack Level 1 |
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Stack Level 8 |
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Reset Vector |
0000h |
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User Memory |
Interrupt Vector |
0004h |
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0005h |
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On-chip Program |
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Space |
Memory |
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07FFh |
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0800h |
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1FFFh |
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 5
PIC16C72 Series
2.2Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.
RP1* RP0 (STATUS<6:5>)
=00 → Bank0
=01 → Bank1
=10 → Bank2 (not implemented)
=11 → Bank3 (not implemented)
*Maintain this bit clear to ensure upward compatibility with future products.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM.
All implemented banks contain special function registers. Some “high use”special function registers from one bank may be mirrored in another bank for code reduction and quicker access (ex; the STATUS register is in Bank 0 and Bank 1).
2.2.1GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 2.5).
FIGURE 2-2: REGISTER FILE MAP
File |
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File |
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Address |
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Address |
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00h |
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INDF(1) |
INDF(1) |
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80h |
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01h |
TMR0 |
OPTION |
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81h |
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82h |
02h |
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PCL |
PCL |
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||||
03h |
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STATUS |
STATUS |
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83h |
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04h |
FSR |
FSR |
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84h |
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85h |
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05h |
PORTA |
TRISA |
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86h |
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06h |
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PORTB |
TRISB |
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07h |
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PORTC |
TRISC |
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87h |
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08h |
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88h |
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09h |
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89h |
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0Ah |
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PCLATH |
PCLATH |
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8Ah |
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0Bh |
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INTCON |
INTCON |
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8Bh |
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0Ch |
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PIR1 |
PIE1 |
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8Ch |
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0Dh |
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8Dh |
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0Eh |
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TMR1L |
PCON |
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8Eh |
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8Fh |
0Fh |
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TMR1H |
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||||
10h |
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T1CON |
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90h |
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11h |
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TMR2 |
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91h |
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12h |
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T2CON |
PR2 |
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92h |
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93h |
13h |
SSPBUF |
SSPADD |
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94h |
14h |
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SSPCON |
SSPSTAT |
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||||
15h |
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CCPR1L |
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95h |
|||
16h |
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CCPR1H |
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96h |
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17h |
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CCP1CON |
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97h |
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18h |
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98h |
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19h |
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99h |
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1Ah |
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9Ah |
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1Bh |
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9Bh |
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1Ch |
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9Ch |
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1Dh |
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9Dh |
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1Eh |
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ADRES |
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9Eh |
|||
1Fh |
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ADCON0 |
ADCON1 |
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9Fh |
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20h |
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General |
General |
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A0h |
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Purpose |
Purpose |
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Register |
Register |
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BFh |
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C0h |
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7Fh |
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FFh |
Bank 0 |
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||
|
Bank 1 |
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS39016A-page 6 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
2.2.2SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.
The special function registers can be classified into two sets (core and peripheral). Those registers associated with the “core”functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 2-1 |
SPECIAL FUNCTION REGISTER SUMMARY |
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Value on: |
Value on all |
||
Address |
Name |
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Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
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Bit 2 |
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Bit 1 |
Bit 0 |
POR, |
other resets |
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BOR |
(3) |
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Bank 0 |
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00h(1) |
INDF |
|
Addressing this location uses contents of FSR to address data memory (not a physical register) |
0000 |
0000 |
0000 |
0000 |
||||||||||||||||
01h |
TMR0 |
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Timer0 module’s register |
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xxxx xxxx |
uuuu uuuu |
|||
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02h(1) |
PCL |
|
Program Counter's (PC) Least Significant Byte |
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0000 |
0000 |
0000 |
0000 |
|||||
03h(1) |
STATUS |
|
IRP(4) |
RP1(4) |
RP0 |
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Z |
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DC |
C |
0001 |
1xxx |
000q |
quuu |
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TO |
PD |
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04h(1) |
FSR |
|
Indirect data memory address pointer |
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xxxx xxxx |
uuuu uuuu |
|||||||
05h |
PORTA |
|
— |
— |
PORTA Data Latch when written: PORTA pins when read |
|
--0x 0000 |
--0u 0000 |
|||||||||||||||
06h |
PORTB |
|
PORTB Data Latch when written: PORTB pins when read |
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xxxx xxxx |
uuuu uuuu |
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|||||||||||
07h |
PORTC |
|
PORTC Data Latch when written: PORTC pins when read |
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xxxx xxxx |
uuuu uuuu |
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08h |
— |
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Unimplemented |
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— |
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— |
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09h |
— |
|
Unimplemented |
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— |
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— |
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|
0Ah(1,2) |
PCLATH |
|
— |
— |
— |
Write Buffer for the upper 5 bits of the Program Counter |
---0 0000 |
---0 0000 |
|||||||||||||||
0Bh(1) |
INTCON |
|
GIE |
PEIE |
T0IE |
INTE |
RBIE |
|
|
T0IF |
|
INTF |
RBIF |
0000 |
000x |
0000 |
000u |
||||||
0Ch |
PIR1 |
|
— |
ADIF |
— |
|
— |
SSPIF |
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CCP1IF |
|
TMR2IF |
TMR1IF |
-0-- 0000 |
-0-- 0000 |
|||||||
0Dh |
— |
|
Unimplemented |
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— |
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— |
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0Eh |
TMR1L |
|
Holding register for the Least Significant Byte of the 16-bit TMR1 register |
|
|
|
xxxx xxxx |
uuuu uuuu |
|||||||||||||||
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|||||||||||||||
0Fh |
TMR1H |
|
Holding register for the Most Significant Byte of the 16-bit TMR1 register |
|
|
|
xxxx xxxx |
uuuu uuuu |
|||||||||||||||
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||||||
10h |
T1CON |
|
— |
— |
T1CKPS1 |
T1CKPS0 |
T1OSCEN |
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|
TMR1CS |
TMR1ON |
--00 0000 |
--uu uuuu |
||||||
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T1SYNC |
|||||||||||||||||||||
11h |
TMR2 |
|
Timer2 module’s register |
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0000 0000 |
0000 0000 |
|||
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|||||||||||
12h |
T2CON |
|
— |
TOUTPS3 |
TOUTPS2 |
TOUTPS1 |
TOUTPS0 |
TMR2ON |
T2CKPS1 |
T2CKPS0 |
-000 0000 |
-000 0000 |
|||||||||||
13h |
SSPBUF |
|
Synchronous Serial Port Receive Buffer/Transmit Register |
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|
xxxx xxxx |
uuuu uuuu |
|||||||||||
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||||||||
14h |
SSPCON |
|
WCOL |
SSPOV |
SSPEN |
CKP |
SSPM3 |
|
|
SSPM2 |
|
SSPM1 |
SSPM0 |
0000 0000 |
0000 0000 |
||||||||
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||||
15h |
CCPR1L |
|
Capture/Compare/PWM Register (LSB) |
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|
xxxx xxxx |
uuuu uuuu |
|||||||
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|||||||
16h |
CCPR1H |
|
Capture/Compare/PWM Register (MSB) |
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|
xxxx xxxx |
uuuu uuuu |
|||||||
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||||||||
17h |
CCP1CON |
|
— |
— |
CCP1X |
CCP1Y |
CCP1M3 |
|
CCP1M2 |
|
CCP1M1 |
CCP1M0 |
--00 0000 |
--00 0000 |
|||||||||
18h-1Dh |
— |
|
Unimplemented |
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— |
|
— |
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|
1Eh |
ADRES |
|
A/D Result Register |
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|
xxxx xxxx |
uuuu uuuu |
|||
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|||||||||
1Fh |
ADCON0 |
|
ADCS1 |
ADCS0 |
CHS2 |
CHS1 |
CHS0 |
|
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|
|
— |
ADON |
0000 00-0 |
0000 00-0 |
||||||||
|
GO/DONE |
||||||||||||||||||||||
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Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter.
3:Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5:SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 7
PIC16C72 Series
TABLE 2-1 |
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) |
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Value on: |
Value on all |
|
Address |
Name |
|
|
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
POR, |
other resets |
||||||||||||||
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BOR |
(3) |
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Bank 1 |
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|||||||||||||||||||
80h(1) |
INDF |
|
Addressing this location uses contents of FSR to address data memory (not a physical register) |
0000 0000 |
0000 0000 |
||||||||||||||||||||||
81h |
OPTION_REG |
|
|
|
INTEDG |
T0CS |
T0SE |
PSA |
PS2 |
|
PS1 |
|
PS0 |
1111 1111 |
1111 |
1111 |
|||||||||||
RBPU |
|||||||||||||||||||||||||||
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|||||||
82h(1) |
PCL |
|
Program Counter's (PC) Least Significant Byte |
|
|
|
|
|
|
|
|
|
|
|
|
0000 0000 |
0000 0000 |
||||||||||
83h(1) |
STATUS |
|
|
IRP(4) |
RP1(4) |
RP0 |
|
|
|
|
|
|
Z |
|
DC |
|
C |
0001 1xxx |
000q |
quuu |
|||||||
|
|
TO |
PD |
||||||||||||||||||||||||
84h(1) |
FSR |
|
Indirect data memory address pointer |
|
|
|
|
|
|
|
|
|
|
|
|
xxxx xxxx |
uuuu uuuu |
||||||||||
85h |
TRISA |
|
|
— |
— |
PORTA Data Direction Register |
|
|
|
|
|
|
|
|
|
--11 1111 |
--11 1111 |
||||||||||
86h |
TRISB |
|
PORTB Data Direction Register |
|
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|
|
|
|
1111 1111 |
1111 1111 |
|||||||
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|||||||
87h |
TRISC |
|
PORTC Data Direction Register |
|
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|
|
1111 1111 |
1111 1111 |
|||||||
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|||
88h |
— |
|
Unimplemented |
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|
— |
— |
||||
89h |
— |
|
Unimplemented |
|
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|
|
— |
— |
||||
8Ah(1,2) |
PCLATH |
|
|
— |
— |
— |
Write Buffer for the upper 5 bits of the PC |
|
|
|
---0 0000 |
---0 0000 |
|||||||||||||||
8Bh(1) |
INTCON |
|
|
GIE |
PEIE |
T0IE |
INTE |
RBIE |
T0IF |
INTF |
RBIF |
0000 000x |
0000 000u |
||||||||||||||
8Ch |
PIE1 |
|
|
— |
ADIE |
— |
|
— |
SSPIE |
CCP1IE |
TMR2IE |
TMR1IE |
-0-- 0000 |
-0-- 0000 |
|||||||||||||
8Dh |
— |
|
Unimplemented |
|
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|
|
— |
— |
||||
8Eh |
PCON |
|
|
— |
— |
— |
|
— |
|
— |
— |
|
|
|
|
|
|
---- --uu |
|||||||||
|
|
|
|
POR |
BOR |
||||||||||||||||||||||
8Fh |
— |
|
Unimplemented |
|
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|
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|
|
|
— |
— |
||||
90h |
— |
|
Unimplemented |
|
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|
|
— |
— |
||||
91h |
— |
|
Unimplemented |
|
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|
|
|
|
— |
— |
||||
92h |
PR2 |
|
Timer2 Period Register |
|
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|
|
|
|
1111 1111 |
1111 1111 |
||||
|
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|
|
|||||||||||||
93h |
SSPADD |
|
Synchronous Serial Port (I2C mode) Address Register |
|
|
|
|
|
|
|
|
|
0000 0000 |
0000 0000 |
|||||||||||||
94h |
SSPSTAT |
|
SMP(5) |
CKE(5) |
D/A |
|
|
P |
|
S |
R/W |
|
UA |
|
BF |
0000 0000 |
0000 0000 |
||||||||||
95h |
— |
|
Unimplemented |
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
— |
— |
||||
96h |
— |
|
Unimplemented |
|
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|
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|
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|
|
— |
— |
||||
97h |
— |
|
Unimplemented |
|
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— |
— |
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98h |
— |
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Unimplemented |
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— |
— |
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99h |
— |
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Unimplemented |
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— |
— |
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9Ah |
— |
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Unimplemented |
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— |
— |
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9Bh |
— |
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Unimplemented |
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— |
— |
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9Ch |
— |
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Unimplemented |
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— |
— |
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9Dh |
— |
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Unimplemented |
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— |
— |
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9Eh |
— |
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Unimplemented |
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— |
— |
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9Fh |
ADCON1 |
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— |
— |
— |
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— |
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— |
PCFG2 |
PCFG1 |
PCFG0 |
---- -000 |
---- -000 |
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Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter.
3:Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5:SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
DS39016A-page 8 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
2.2.2.1STATUS REGISTER
The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary."
Note 1: These devices do not use bits IRP and RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products.
Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 |
R/W-0 |
R/W-0 |
R-1 |
R-1 |
R/W-x |
R/W-x |
R/W-x |
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IRP |
RP1 |
RP0 |
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TO |
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PD |
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Z |
DC |
C |
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R = Readable bit |
bit7 |
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bit0 |
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W = Writable bit |
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U = Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit |
6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) |
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11 = Bank 3 (180h - 1FFh) |
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10 = Bank 2 (100h - 17Fh) |
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01 = Bank 1 (80h - FFh) |
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00 = Bank 0 (00h - 7Fh) |
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Each bank is 128 bytes. For devices with only Bank0 and Bank1, the IRP bit is reserved. Always maintain |
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this bit clear. |
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bit |
4: |
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: Time-out bit |
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TO |
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1 |
= After power-up, CLRWDT instruction, or SLEEP instruction |
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0 |
= A WDT time-out occurred |
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bit |
3: |
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: Power-down bit |
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PD |
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1 |
= After power-up or by the CLRWDT instruction |
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0 |
= By execution of the SLEEP instruction |
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bit |
2: |
Z: Zero bit |
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1 |
= The result of an arithmetic or logic operation is zero |
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0 |
= The result of an arithmetic or logic operation is not zero |
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bit |
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1: DC: Digit carry/borrow |
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) |
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1 |
= A carry-out from the 4th low order bit of the result occurred |
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0 |
= No carry-out from the 4th low order bit of the result |
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bit |
0: |
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bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) |
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C: Carry/borrow |
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1 |
= A carry-out from the most significant bit of the result occurred |
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0 |
= No carry-out from the most significant bit of the result occurred |
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 9
PIC16C72 Series
2.2.2.2OPTION_REG REGISTER
The OPTION_REG register is a readable and writable |
Note: |
To achieve a 1:1 prescaler assignment for |
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the TMR0 register, assign the prescaler to |
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register which contains various control bits to configure |
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the Watchdog Timer. |
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the TMR0 prescaler/WDT postscaler (single assign- |
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able register known also as the prescaler), the External |
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INT Interrupt, TMR0, and the weak pull-ups on PORTB. |
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FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h) |
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R/W-1 |
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R/W-1 |
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R/W-1 |
R/W-1 |
R/W-1 |
R/W-1 |
R/W-1 |
R/W-1 |
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RBPU |
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INTEDG |
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T0CS |
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T0SE |
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PSA |
PS2 |
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PS1 |
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PS0 |
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R |
= Readable bit |
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bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7: |
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: PORTB Pull-up Enable bit |
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RBPU |
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1 |
= PORTB pull-ups are disabled |
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0 |
= PORTB pull-ups are enabled by individual port latch values |
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bit |
6: |
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INTEDG: Interrupt Edge Select bit |
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1 |
= Interrupt on rising edge of RB0/INT pin |
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0 |
= Interrupt on falling edge of RB0/INT pin |
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bit |
5: |
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T0CS: TMR0 Clock Source Select bit |
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1 |
= Transition on RA4/T0CKI pin |
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0 |
= Internal instruction cycle clock (CLKOUT) |
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bit |
4: |
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T0SE: TMR0 Source Edge Select bit |
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1 |
= Increment on high-to-low transition on RA4/T0CKI pin |
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0 |
= Increment on low-to-high transition on RA4/T0CKI pin |
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bit |
3: |
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PSA: Prescaler Assignment bit |
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1 |
= Prescaler is assigned to the WDT |
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0 |
= Prescaler is assigned to the Timer0 module |
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bit |
2-0: |
PS2:PS0: Prescaler Rate Select bits |
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Bit Value |
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TMR0 Rate WDT Rate |
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000 |
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1 : 2 |
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1 : 1 |
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001 |
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1 : 4 |
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1 : 2 |
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010 |
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1 : 8 |
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1 : 4 |
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011 |
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1 : 16 |
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1 : 8 |
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100 |
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1 : 32 |
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1 : 16 |
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101 |
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1 : 64 |
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1 : 32 |
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110 |
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1 : 128 |
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1 : 64 |
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111 |
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1 : 256 |
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1 : 128 |
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DS39016A-page 10 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
2.2.2.3INTCON REGISTER
The INTCON Register is a readable and writable regis- |
Note: |
Interrupt flag bits get set when an interrupt |
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|
condition occurs regardless of the state of |
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ter which contains various enable and flag bits for the |
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its corresponding enable bit or the global |
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TMR0 register overflow, RB Port change and External |
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enable bit, GIE (INTCON<7>). User soft- |
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RB0/INT pin interrupts. |
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ware should ensure the appropriate inter- |
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rupt flag bits are clear prior to enabling an |
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interrupt. |
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FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh) |
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R/W-0 |
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R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-x |
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GIE |
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PEIE |
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T0IE |
INTE |
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RBIE |
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T0IF |
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INTF |
RBIF |
|
R |
= Readable bit |
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bit7 |
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bit0 |
W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7: |
GIE: Global Interrupt Enable bit |
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1 |
= Enables all un-masked interrupts |
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0 |
= Disables all interrupts |
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bit |
6: |
PEIE: Peripheral Interrupt Enable bit |
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1 |
= Enables all un-masked peripheral interrupts |
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0 |
= Disables all peripheral interrupts |
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bit |
5: |
T0IE: TMR0 Overflow Interrupt Enable bit |
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1 |
= Enables the TMR0 interrupt |
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0 |
= Disables the TMR0 interrupt |
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bit |
4: |
INTE: RB0/INT External Interrupt Enable bit |
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1 |
= Enables the RB0/INT external interrupt |
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0 |
= Disables the RB0/INT external interrupt |
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bit |
3: |
RBIE: RB Port Change Interrupt Enable bit |
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1 |
= Enables the RB port change interrupt |
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0 |
= Disables the RB port change interrupt |
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bit |
2: |
T0IF: TMR0 Overflow Interrupt Flag bit |
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1 |
= TMR0 register has overflowed (must be cleared in software) |
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0 |
= TMR0 register did not overflow |
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bit |
1: |
INTF: RB0/INT External Interrupt Flag bit |
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1 |
= The RB0/INT external interrupt occurred (must be cleared in software) |
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0 |
= The RB0/INT external interrupt did not occur |
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bit |
0: |
RBIF: RB Port Change Interrupt Flag bit |
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1 |
= At least one of the RB7:RB4 pins changed state (must be cleared in software) |
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0 |
= None of the RB7:RB4 pins have changed state |
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1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 11
PIC16C72 Series
2.2.2.4PIE1 REGISTER
This register contains the individual enable bits for the |
Note: |
Bit PEIE (INTCON<6>) must be set to |
|||||||||||||||
peripheral interrupts. |
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enable any peripheral interrupt. |
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FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch) |
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U-0 |
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R/W-0 |
U-0 |
U-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
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|||
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— |
|
ADIE |
— |
— |
|
SSPIE |
|
CCP1IE |
|
TMR2IE |
TMR1IE |
|
R |
= Readable bit |
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bit7 |
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bit0 |
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W |
= Writable bit |
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= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7: |
Unimplemented: Read as '0' |
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bit |
6: |
ADIE: A/D Converter Interrupt Enable bit |
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= Enables the A/D interrupt |
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= Disables the A/D interrupt |
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bit |
5-4: Unimplemented: Read as '0' |
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bit |
3: |
SSPIE: Synchronous Serial Port Interrupt Enable bit |
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= Enables the SSP interrupt |
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0 |
= Disables the SSP interrupt |
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bit |
2: |
CCP1IE: CCP1 Interrupt Enable bit |
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= Enables the CCP1 interrupt |
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= Disables the CCP1 interrupt |
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bit |
1: |
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit |
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= Enables the TMR2 to PR2 match interrupt |
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0 |
= Disables the TMR2 to PR2 match interrupt |
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bit |
0: |
TMR1IE: TMR1 Overflow Interrupt Enable bit |
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1 |
= Enables the TMR1 overflow interrupt |
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0 |
= Disables the TMR1 overflow interrupt |
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DS39016A-page 12 |
Preliminary |
1998 Microchip Technology Inc. |
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PIC16C72 Series |
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2.2.2.5 |
PIR1 REGISTER |
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Note: |
Interrupt flag bits get set when an interrupt |
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This register contains the individual flag bits for the |
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condition occurs regardless of the state of |
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Peripheral interrupts. |
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its corresponding enable bit or the global |
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enable bit, GIE (INTCON<7>). User soft- |
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ware should ensure the appropriate inter- |
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rupt flag bits are clear prior to enabling an |
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interrupt. |
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FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch) |
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U-0 |
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R/W-0 |
U-0 |
U-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
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— |
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ADIF |
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— |
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— |
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SSPIF |
CCP1IF |
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TMR2IF |
TMR1IF |
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R |
= Readable bit |
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bit7 |
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bit0 |
W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7: |
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Unimplemented: Read as '0' |
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bit |
6: |
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ADIF: A/D Converter Interrupt Flag bit |
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1 |
= An A/D conversion completed (must be cleared in software) |
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0 |
= The A/D conversion is not complete |
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bit |
5-4: Unimplemented: Read as '0' |
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bit |
3: |
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SSPIF: Synchronous Serial Port Interrupt Flag bit |
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1 |
= The transmission/reception is complete (must be cleared in software) |
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0 |
= Waiting to transmit/receive |
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bit |
2: |
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CCP1IF: CCP1 Interrupt Flag bit |
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Capture Mode |
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1 |
= A TMR1 register capture occurred (must be cleared in software) |
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0 |
= No TMR1 register capture occurred |
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Compare Mode |
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1 |
= A TMR1 register compare match occurred (must be cleared in software) |
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0 |
= No TMR1 register compare match occurred |
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PWM Mode |
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Unused in this mode |
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bit |
1: |
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TMR2IF: TMR2 to PR2 Match Interrupt Flag bit |
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1 |
= TMR2 to PR2 match occurred (must be cleared in software) |
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0 |
= No TMR2 to PR2 match occurred |
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bit |
0: |
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TMR1IF: TMR1 Overflow Interrupt Flag bit |
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1 |
= TMR1 register overflowed (must be cleared in software) |
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0 |
= TMR1 register did not overflow |
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1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 13
PIC16C72 Series
2.2.2.6 |
PCON REGISTER |
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Note: BOR is unknown on Power-on Reset. It |
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The Power Control (PCON) register contains a flag bit |
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must then be set by the user and checked |
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on subsequent resets to see if BOR is |
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to allow differentiation |
between |
a Power-on |
Reset |
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clear, indicating a brown-out has occurred. |
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(POR) to an external MCLR Reset or WDT Reset. |
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The BOR status bit is a don't care and is |
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Those devices with brown-out detection circuitry con- |
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not necessarily predictable if the brown-out |
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tain an additional bit to differentiate a Brown-out Reset |
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circuit is disabled (by clearing the BODEN |
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condition from a Power-on Reset condition. |
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bit in the Configuration word). |
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FIGURE 2-8: PCON REGISTER (ADDRESS 8Eh) |
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U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
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U-0 |
R/W-0 |
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R/W-q |
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— |
— |
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— |
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— |
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— |
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— |
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R |
= Readable bit |
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POR |
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BOR |
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bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7-2: |
Unimplemented: Read as '0' |
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bit |
1: |
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: Power-on Reset Status bit |
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POR |
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1 = No Power-on Reset occurred |
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0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) |
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bit |
0: |
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: Brown-out Reset Status bit |
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BOR |
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1 = No Brown-out Reset occurred |
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0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) |
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DS39016A-page 14 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
2.3PCL and PCLATH
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register.
Figure 2-9 shows the four situations for the loading of the PC. Example 1 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). Example 2 shows how the PC is loaded during a GOTO instruction (PCLATH<4:3> → PCH). Example 3 shows how the PC is loaded during a CALL instruction (PCLATH<4:3> → PCH), with the PC loaded (PUSHed) onto the Top of Stack. Finally, example 4 shows how the PC is loaded during one of the return instructions where the PC is loaded (POPed) from the Top of Stack.
FIGURE 2-9: LOADING OF PC IN DIFFERENT SITUATIONS
Situation 1 - Instruction with PCL as destination
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PCH |
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PCL |
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12 |
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8 |
7 |
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0 |
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PC |
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5 |
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PCLATH<4:0> |
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8 |
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ALU result |
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PCLATH |
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Situation 2 - GOTO Instruction
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PCH |
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PCL |
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12 |
11 |
10 |
8 |
7 |
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0 |
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PC |
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11 |
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2 |
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PCLATH<4:3> |
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Opcode <10:0> |
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PCLATH |
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Situation 3 - CALL Instruction |
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13 |
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PCH |
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PCL |
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12 |
11 |
10 |
8 |
7 |
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0 |
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PC |
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11 |
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2 |
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PCLATH<4:3> |
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Opcode <10:0> |
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PCLATH |
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Situation 4 - RETURN, RETFIE, or RETLW Instruction |
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13 |
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PCH |
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PCL |
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11 |
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PC |
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11
Opcode <10:0>
STACK (13-bits x 8)
Top of STACK
STACK (13-bits x 8)
Top of STACK
STACK (13-bits x 8)
Top of STACK
STACK (13-bits x 8)
Top of STACK
PCLATH
Note: PCLATH is not updated with the contents of PCH.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 15
PIC16C72 Series
2.3.1STACK
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution.
Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed.
After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). An example of the overwriting of the stack is shown in Figure 2-10.
FIGURE 2-10: STACK MODIFICATION
STACK
Push1 Push9
Push2 Push10 Top of STACK
Push3
Push4
Push5
Push6
Push7
Push8
2.4Program Memory Paging
The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack).
Note: PIC16C72 Series devices ignore paging bit PCLATH<4>. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.
DS39016A-page 16 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
2.5Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-1: INDIRECT ADDRESSING
•Register file 05 contains the value 10h
•Register file 06 contains the value 0Ah
•Load the value 05 into the FSR register
•A read of the INDF register will return the value of 10h
•Increment the value of the FSR register by one (FSR = 06)
•A read of the INDR register now will return the value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
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movlw |
0x20 |
;initialize pointer |
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movwf |
FSR |
; to RAM |
NEXT |
clrf |
INDF |
;clear INDF register |
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incf |
FSR |
;inc pointer |
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btfss |
FSR,4 |
;all done? |
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goto |
NEXT |
;NO, clear next |
CONTINUE |
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;YES, continue |
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-11. However, IRP is not used in the PIC16C72 Series.
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RP1:RP0 |
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from opcode |
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bank select |
location select |
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bank select |
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location select |
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00h |
80h |
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180h |
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Data |
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7Fh |
FFh |
17Fh |
1FFh |
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Bank 0 |
Bank 1 |
Bank 2 |
Bank 3 |
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Note 1: For register file map detail see Figure 2-2.
2:Maintain RP1 and IRP as clear for upward compatibility with future products.
3:Not implemented.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 17
PIC16C72 Series
NOTES:
DS39016A-page 18 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
3.0I/O PORTS
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the PICmicro™ Mid-Range MCU Ref erence Manual, DS33023.
3.1PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin.
Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch.
Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).
Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
BCF |
STATUS, RP0 |
; |
CLRF |
PORTA |
; Initialize PORTA by |
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; clearing output |
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; data latches |
BSF |
STATUS, RP0 |
; Select Bank 1 |
MOVLW |
0xCF |
; Value used to |
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; initialize data |
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; direction |
MOVWF |
TRISA |
; Set RA<3:0> as inputs |
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; RA<5:4> as outputs |
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; TRISA<7:6> are always |
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; read as '0'. |
FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Data |
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bus |
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Q |
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WR |
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Data Latch |
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N |
I/O pin(1) |
WR |
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TRIS |
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VSS |
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input |
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buffer |
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EN |
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Note |
1: |
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VSS. |
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FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Data |
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bus |
D |
Q |
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CK |
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CK |
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input |
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buffer |
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RD TRIS |
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ENEN |
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RD PORT |
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TMR0 clock input |
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Note 1: I/O pin has protection diodes to VSS only.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 19
PIC16C72 Series
TABLE 3-1 |
PORTA FUNCTIONS |
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Function |
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RA0/AN0 |
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bit0 |
TTL |
Input/output or analog input |
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RA1/AN1 |
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bit1 |
TTL |
Input/output or analog input |
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RA2/AN2 |
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TTL |
Input/output or analog input |
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RA3/AN3/VREF |
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bit3 |
TTL |
Input/output or analog input or VREF |
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RA4/T0CKI |
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bit4 |
ST |
Input/output or external clock input for Timer0 |
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Output is open drain type |
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bit5 |
TTL |
Input/output or slave select input for synchronous serial port or analog input |
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RA5/SS/AN4 |
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Legend: TTL = TTL input, ST = Schmitt Trigger input |
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TABLE 3-2 |
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA |
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Value on: |
Value on all |
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Bit 7 |
Bit 6 |
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Bit 5 |
Bit 4 |
Bit 3 |
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Bit 0 |
POR, |
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05h |
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PORTA |
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— |
— |
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RA5 |
RA4 |
RA3 |
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RA2 |
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RA1 |
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RA0 |
--0x 0000 |
--0u 0000 |
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85h |
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TRISA |
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— |
— |
PORTA Data Direction Register |
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--11 1111 |
--11 1111 |
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9Fh |
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ADCON1 |
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---- -000 |
---- -000 |
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Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'Shaded. cells are not used by PORTA.
DS39016A-page 20 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
3.2PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin.
EXAMPLE 3-1: INITIALIZING PORTB
BCF |
STATUS, RP0 |
; |
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CLRF |
PORTB |
; Initialize PORTB by |
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; clearing output |
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; data latches |
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BSF |
STATUS, RP0 |
; Select Bank 1 |
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MOVLW |
0xCF |
; Value used |
to |
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; initialize |
data |
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; direction |
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MOVWF |
TRISB |
; Set RB<3:0> as inputs |
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; RB<5:4> as |
outputs |
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; RB<7:6> as |
inputs |
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF RB3:RB0 PINS
VDD
RBPU(2)
Data bus
WR Port
WR TRIS
RB0/INT
weak
P pull-up
Data Latch |
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D |
Q |
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CK |
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pin(1) |
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TRIS Latch |
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D |
Q |
TTL |
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CK |
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D |
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RD Port |
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Buffer |
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Note 1: I/O pins have diode protection to VDD and VSS.
2:To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>).
Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch”outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:
a)Any read or write of PORTB. This will end the mismatch condition.
b)Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 3-4: BLOCK DIAGRAM OF RB7:RB4 PINS
VDD
RBPU(2) |
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weak |
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pull-up |
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Data bus |
Data Latch |
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D |
Q |
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WR Port |
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CK |
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pin(1) |
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D |
Q |
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WR TRIS |
CK |
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Buffer |
ST |
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Latch |
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Q |
D |
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Set RBIF |
RD Port |
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EN |
Q1 |
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From other |
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D |
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RD Port |
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EN |
Q3 |
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Note 1: I/O pins have diode protection to VDD and VSS.
2:To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>).
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 21
PIC16C72 Series
TABLE 3-3 |
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PORTB FUNCTIONS |
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RB0/INT |
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bit0 |
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TTL/ST(1) |
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Input/output pin or external interrupt input. Internal software |
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programmable weak pull-up. |
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RB1 |
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bit1 |
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TTL |
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Input/output pin. Internal software programmable weak pull-up. |
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RB2 |
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bit2 |
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TTL |
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Input/output pin. Internal software programmable weak pull-up. |
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RB3 |
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bit3 |
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TTL |
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Input/output pin. Internal software programmable weak pull-up. |
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RB4 |
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bit4 |
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TTL |
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Input/output pin (with interrupt on change). Internal software programmable |
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weak pull-up. |
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RB5 |
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bit5 |
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TTL |
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Input/output pin (with interrupt on change). Internal software programmable |
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weak pull-up. |
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RB6 |
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bit6 |
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TTL/ST(2) |
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Input/output pin (with interrupt on change). Internal software programmable |
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weak pull-up. Serial programming clock. |
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RB7 |
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bit7 |
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TTL/ST(2) |
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Input/output pin (with interrupt on change). Internal software programmable |
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weak pull-up. Serial programming data. |
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Legend: TTL = TTL input, ST = Schmitt Trigger input |
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Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. |
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2: This buffer is a Schmitt Trigger input when used in serial programming mode. |
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TABLE 3-4 |
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SUMMARY OF REGISTERS ASSOCIATED WITH PORTB |
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Value on: |
Value on all |
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Address |
Name |
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Bit 7 |
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Bit 6 |
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Bit 5 |
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Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
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Bit 0 |
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POR, |
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other resets |
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BOR |
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06h, 106h |
PORTB |
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RB7 |
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RB6 |
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RB5 |
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RB4 |
RB3 |
RB2 |
RB1 |
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RB0 |
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xxxx xxxx |
uuuu uuuu |
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86h, 186h |
TRISB |
PORTB Data Direction Register |
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1111 1111 |
1111 1111 |
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81h, 181h |
OPTION |
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INTEDG |
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T0CS |
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T0SE |
PSA |
PS2 |
PS1 |
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PS0 |
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1111 1111 |
1111 1111 |
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RBPU |
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Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39016A-page 22 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
3.3PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin.
PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers.
When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify- write instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
EXAMPLE 3-1: INITIALIZING PORTC
BCF |
STATUS, RP0 |
; Select Bank 0 |
CLRF |
PORTC |
; Initialize PORTC by |
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; clearing output |
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; data latches |
BSF |
STATUS, RP0 |
; Select Bank 1 |
MOVLW |
0xCF |
; Value used to |
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; initialize data |
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; direction |
MOVWF |
TRISC |
; Set RC<3:0> as inputs |
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; RC<5:4> as outputs |
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; RC<7:6> as inputs |
FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORT/PERIPHERAL Select(2) |
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|||
Peripheral Data Out |
0 |
VDD |
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Data bus |
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D |
Q |
P |
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WR |
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1 |
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PORT |
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CK |
Q |
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Data Latch |
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WR |
D |
Q |
I/O |
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pin(1) |
||
TRIS |
CK |
Q |
N |
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TRIS Latch |
VSS |
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RD TRIS |
Schmitt |
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Trigger |
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Peripheral |
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OE(3) |
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Q |
D |
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RD |
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EN |
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PORT |
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Peripheral input |
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Note 1: I/O pins have diode protection to VDD and VSS.
2:Port/Peripheral select signal selects between port data and peripheral output.
3:Peripheral OE (output enable) is only activated if peripheral select is active.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 23
PIC16C72 Series
TABLE 3-5 |
PORTC FUNCTIONS |
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Name |
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Bit# |
Buffer Type |
Function |
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RC0/T1OSO/T1CKI |
bit0 |
ST |
Input/output port pin or Timer1 oscillator output/Timer1 clock input |
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RC1/T1OSI |
|
bit1 |
ST |
Input/output port pin or Timer1 oscillator input |
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RC2/CCP1 |
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bit2 |
ST |
Input/output port pin or Capture1 input/Compare1 output/PWM1 |
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output |
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RC3/SCK/SCL |
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bit3 |
ST |
RC3 can also be the synchronous serial clock for both SPI and I2C |
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modes. |
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RC4/SDI/SDA |
|
bit4 |
ST |
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). |
RC5/SDO |
|
bit5 |
ST |
Input/output port pin or Synchronous Serial Port data output |
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RC6 |
|
bit6 |
ST |
Input/output port pin |
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RC7 |
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bit7 |
ST |
Input/output port pin |
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Legend: ST = Schmitt Trigger input |
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||||
TABLE 3-6 |
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC |
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Value on: |
Value on all |
Address |
Name |
|
Bit 7 |
Bit 6 |
Bit 5 |
|
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
|
Bit 0 |
POR, |
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other resets |
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BOR |
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07h |
PORTC |
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RC7 |
RC6 |
RC5 |
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RC4 |
RC3 |
RC2 |
RC1 |
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RC0 |
xxxx xxxx |
uuuu uuuu |
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87h |
TRISC |
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PORTC Data Direction Register |
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1111 1111 |
1111 1111 |
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Legend: |
x = unknown, u = unchanged. |
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DS39016A-page 24 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
4.0TIMER0 MODULE
The Timer0 module timer/counter has the following features:
•8-bit timer/counter
•Readable and writable
•Internal or external clock select
•Edge select for external clock
•8-bit software programmable prescaler
•Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0 module.
Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Ref erence Manual, DS33023.
4.1Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in below.
When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
Additional information on external clock requirements is available in the PICmicro™ Mid-Range MCU Ref erence Manual, DS33023.
4.2Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler”throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable.
Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.
When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.
Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
FIGURE 4-1: |
|
TIMER0 BLOCK DIAGRAM |
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Data bus |
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FOSC/4 |
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0 |
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1 |
PSout |
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8 |
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Sync with |
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1 |
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TMR0 |
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Internal |
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RA4/T0CKI |
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Programmable |
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0 |
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clocks |
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PSout |
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pin |
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Prescaler |
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T0SE |
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(2 cycle delay) |
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3 |
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Set interrupt |
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PSA |
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PS2, PS1, PS0 |
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flag bit T0IF |
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T0CS |
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on overflow |
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 25
PIC16C72 Series
4.2.1SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control, i.e., it can be changed “on the y”fl during program execution.
Note: To avoid an unintended device RESET, a specifi instruction sequence (shown in the PICmicro™ Mid-Range MCU Ref erence Manual, DS3023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
4.3Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT (=Fosc/4) |
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Data Bus |
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0 |
M |
1 |
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8 |
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|||
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U |
M |
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RA4/T0CKI |
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SYNC |
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||
pin |
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X |
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U |
TMR0 reg |
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1 |
0 |
2 |
||||
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X |
Cycles |
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T0SE |
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T0CS |
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PSA |
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Set flag bit T0IF |
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on Overflow |
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0 |
M |
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8-bit Prescaler |
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1 |
U |
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Watchdog |
X |
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8 |
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Timer |
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8 - to - 1MUX |
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PS2:PS0 |
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PSA |
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WDT Enable bit |
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0 |
1 |
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M U X |
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PSA |
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WDT |
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Time-out |
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Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). |
|
|
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
|
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|
|
|
Value on: |
Value on all |
|||
Address |
Name |
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
POR, |
|||||
other resets |
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BOR |
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||||||
01h,101h |
TMR0 |
Timer0 module’s register |
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|
|
xxxx xxxx |
uuuu uuuu |
||||||
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|
0Bh,8Bh, |
INTCON |
GIE |
PEIE |
T0IE |
INTE |
RBIE |
T0IF |
INTF |
RBIF |
0000 |
000x |
0000 |
000u |
||
10Bh,18Bh |
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81h,181h |
OPTION_REG |
|
|
INTEDG |
T0CS |
T0SE |
PSA |
PS2 |
PS1 |
PS0 |
1111 |
1111 |
1111 |
1111 |
|
RBPU |
|||||||||||||||
85h |
TRISA |
— |
— |
PORTA Data Direction Register |
|
|
--11 |
1111 |
--11 |
1111 |
|||||
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|
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'Shaded. cells are not used by Timer0.
DS39016A-page 26 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
5.0TIMER1 MODULE
The Timer1 module timer/counter has the following features:
•16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
•Readable and writable (Both registers)
•Internal or external clock select
•Interrupt on overflow from FFFFh to 0000h
•Reset from CCP module trigger
Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).
Figure 5-2 is a simplified block diagram of the Timer1 module.
Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Ref erence Manual, DS33023.
5.1Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
•As a synchronous counter
•As an asynchronous counter
The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.
Timer1 also has an internal “reset input”This. reset can be generated by the CCP module (Section 7.0).
FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
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U-0 |
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U-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
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— |
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— |
T1CKPS1 |
T1CKPS0 |
T1OSCEN |
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TMR1CS |
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TMR1ON |
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R |
= Readable bit |
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T1SYNC |
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bit7 |
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bit0 |
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W |
= Writable bit |
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U |
= Unimplemented bit, |
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read as ‘0’ |
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- n = Value at POR reset |
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bit 7-6: |
Unimplemented: Read as '0' |
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5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits |
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11 = 1:8 Prescale value |
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10 = 1:4 Prescale value |
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01 = 1:2 Prescale value |
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00 = 1:1 Prescale value |
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3: |
T1OSCEN: Timer1 Oscillator Enable Control bit |
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1 |
= Oscillator is enabled |
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0 |
= Oscillator is shut off |
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Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain |
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2: |
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: Timer1 External Clock Input Synchronization Control bit |
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T1SYNC |
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TMR1CS = 1 |
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1 |
= Do not synchronize external clock input |
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0 |
= Synchronize external clock input |
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TMR1CS = 0 |
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This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. |
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1: |
TMR1CS: Timer1 Clock Source Select bit |
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1 |
= External clock from pin RC0/T1OSO/T1CKI (on the rising edge) |
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0 |
= Internal clock (FOSC/4) |
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0: |
TMR1ON: Timer1 On bit |
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1 |
= Enables Timer1 |
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0 |
= Stops Timer1 |
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1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 27
PIC16C72 Series
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit |
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TMR1IF on |
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Synchronized |
Overflow |
TMR1 |
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0 |
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clock input |
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TMR1H |
TMR1L |
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1 |
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TMR1ON |
T1SYNC |
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T1OSC |
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on/off |
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RC0/T1OSO/T1CKI |
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1 |
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Synchronize |
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Prescaler |
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T1OSCEN |
FOSC/4 |
1, 2, 4, 8 |
det |
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Enable |
Internal |
0 |
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RC1/T1OSI |
Oscillator(1) |
Clock |
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2 |
SLEEP input |
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T1CKPS1:T1CKPS0 |
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TMR1CS |
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Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39016A-page 28 |
Preliminary |
1998 Microchip Technology Inc. |
PIC16C72 Series
5.2Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.
TABLE 5-1 |
CAPACITOR SELECTION |
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FOR THE TIMER1 |
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OSCILLATOR |
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Osc Type |
Freq |
C1 |
C2 |
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LP |
32 kHz |
33 pF |
33 pF |
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100 kHz |
15 pF |
15 pF |
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200 kHz |
15 pF |
15 pF |
These values are for design guidance only.
Crystals Tested:
32.768 kHz |
Epson C-001R32.768K-A |
± 20 PPM |
100 kHz |
Epson C-2 100.00 KC-P |
± 20 PPM |
200 kHz |
STD XTL 200.000 kHz |
± 20 PPM |
Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time.
2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
5.3Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4Resetting Timer1 using a CCP Trigger Output
If the CCP module is configured in compare mode to generate a “special vente trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled).
Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
TABLE 5-2 |
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER |
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Value on: |
Value on |
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Name |
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Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
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Bit 2 |
Bit 1 |
Bit 0 |
POR, |
all other |
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BOR |
resets |
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0Bh,8Bh |
INTCON |
GIE |
PEIE |
T0IE |
INTE |
RBIE |
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T0IF |
INTF |
RBIF |
0000 |
000x |
0000 |
000u |
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0Ch |
PIR1 |
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(1) |
ADIF |
(1) |
(1) |
SSPIF |
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CCP1IF |
TMR2IF |
TMR1IF |
0000 |
0000 |
0000 |
0000 |
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8Ch |
PIE1 |
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(1) |
ADIE |
(1) |
(1) |
SSPIE |
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CCP1IE |
TMR2IE |
TMR1IE |
0000 |
0000 |
0000 |
0000 |
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0Eh |
TMR1L |
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Holding register for the Least Significant Byte of the 16-bit TMR1 register |
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xxxx xxxx |
uuuu uuuu |
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0Fh |
TMR1H |
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Holding register for the Most Significant Byte of the 16-bit TMR1 register |
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xxxx xxxx |
uuuu uuuu |
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10h |
T1CON |
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— |
— |
T1CKPS1 |
T1CKPS0 |
T1OSCEN |
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TMR1CS |
TMR1ON |
--00 |
0000 |
--uu uuuu |
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T1SYNC |
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'Shaded. cells are not used by the Timer1 module. Note 1: These bits are unimplemented, read as '0'.
1998 Microchip Technology Inc. |
Preliminary |
DS39016A-page 29
PIC16C72 Series
NOTES:
DS39016A-page 30 |
Preliminary |
1998 Microchip Technology Inc. |