Microchip Technology Inc 24AA08T-I-SM, 24AA08T-I-SL, 24AA08T-SN, 24AA08T-SM, 24AA08T-SL Datasheet

24AA04/08

4K/8K 1.8V I2C Serial EEPROMs

FEATURES

•Single supply with operation down to 1.8V

•Low power CMOS technology

-1 mA active current typical

-10 A standby current typical at 5.5V

-3 A standby current typical at 1.8V

•Organized as 2 or 4 blocks of 256 bytes (2 x 256 x 8) or (4 x 256 x 8)

•2-wire serial interface bus, I2C compatible

•Schmitt trigger, filtered inputs for noise suppression

•Output slope control to eliminate ground bounce

•100 kHz (1.8V) and 400 kHz (5V) compatibility

•Self-timed write cycle (including auto-erase)

•Page-write buffer for up to 16 bytes

•2 ms typical write cycle time for page-write

•Hardware write protect for entire memory

•Can be operated as a serial ROM

•ESD protection > 4,000V

•1,000,000 ERASE/WRITE cycles guaranteed

•Data retention > 200 years

•8-pin DIP, 8-lead or 14-lead SOIC packages

•Available for extended temperature ranges

-	Commercial (C):	0°C	to	+70°C
-	Industrial (I):	-40°C	to	+85°C

DESCRIPTION

The Microchip Technology Inc. 24AA04/08 is a 4K bit or 8K bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x 8-bit memory with a two wire serial interface. Low voltage design permits operation down to 1.8 volts with standby and active currents of only 3 A and 1 mA respectively. The 24AA04/ 08 also has a page-write capability for up to 16 bytes of data. The 24AA04/08 is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC packages.

I2C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

PACKAGE TYPES

DIP	A0							1	24AA04/08	8				VCC
	A1							2		7				WP
	A2							3		6				SCL
8-lead	VSS							4		5				SDA
	A0						1			8					VCC
SOIC	A1						2		24AA04/08	7					WP
							3			6
	A2														SCL
							4			5
14-Lead	VSS														SDA
							1			14
SOIC	NC														NC
	A0						2		24AA04/08	13					VCC
	A1						3			12					WP
	NC						4			11					NC
	A2						5			10					SCL
	VSS									9					SDA
							6
	NC						7			8					NC

BLOCK DIAGRAM

			WP
					HV GENERATOR
	I/O		MEMORY		EEPROM
	CONTROL		CONTROL
				XDEC	ARRAY
	LOGIC		LOGIC
					PAGE LATCHES
	SDA	SCL
					YDEC
	VCC				SENSE AMP
	VSS				R/W CONTROL

DS21053E-page 1

24AA04/08

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. VSS ..............	-0.6V to VCC +1.0V
Storage temperature .....................................		-65˚C to +150˚C
Ambient temp. with power applied ................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins ..................................................		≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1:	PIN FUNCTION TABLE
Name	Function
VSS	Ground
SDA	Serial Address/Data I/O
SCL	Serial Clock
WP	Write Protect Input
Vcc	+1.8V to 5.5V Power Supply
A0, A1, A2	No Internal Connection

TABLE 1-2:	DC CHARACTERISTICS
					VCC = +1.8V to +5.5V
					Commercial (C): Tamb = 0˚C to +70˚C
					Industrial (I):		Tamb = -40°C to +85°C
Parameter		Sym	Min	Typ	Max	Units		Conditions
WP, SCL and SDA pins:
High level input voltage		VIH	.7 Vcc	—	—	V
Low Level input voltage		VIL	—	—	.3 V CC	V
Hysteresis of Schmitt trigger		VHYS	.05 VCC	—	—	V		(Note)
inputs
Low level output voltage		VOL	—	—	.40	V	I	OL = 3.0 mA, VCC = 1.8V
Input leakage current		ILI	-10	—	10	A		VIN = .1V to VCC
Output leakage current		ILO	-10	—	10	A		VOUT = .1V to VCC
Pin capacitance		CIN, COUT	—	—	10	pF	V	CC = 5.0V (Note 1)
(all inputs/outputs)								Tamb = 25˚C, FCLK = 1 MHz
Operating current		ICC WRITE	—	—	3	mA		VCC = 5.5V, SCL = 400 kHz
			—	0.5	—	mA		VCC = 1.8V, SCL = 100 kHz
		ICC READ	—	—	1	mA		VCC = 5.5V, SCL = 400 kHz
			—	0.05	—	mA		VCC = 1.8V, SCL = 100 kHz
Standby current		ICCS	—		100	A		VCC = 5.5V, SDA=SCL=VCC
			—		30	A		VCC = 3.0V, SDA=SCL=VCC
			—	3	—	A		VCC = 1.8V, SDA=SCL=VCC

Note:This parameter is periodically sampled and not 100% tested.

FIGURE 1-1:	BUS TIMING START/STOP
		VHYS
SCL
	THD:STA
TSU:STA		TSU:STO
SDA
	START	STOP

DS21053E-page 2

1996 Microchip Technology Inc.

									24AA04/08
TABLE 1-3:	AC CHARACTERISTICS
			Standard Mode		VCC = 4.5-5.5V
Parameter		Symbol			Fast Mode		Units		Remarks
			Min	Max	Min	Max
Clock frequency		Fclk	—	100	—	400	kHz
Clock high time		Thigh	4000	—	600	—	ns
Clock low time		Tlow	4700	—	1300	—	ns
SDA and SCL rise time		Tr	—	1000	—	300	ns		(Note 1)
SDA and SCL fall time		Tf	—	300	—	300	ns		(Note 1)
START condition hold time		THD:STA	4000	—	600	—	ns	After this period the first clock
									pulse is generated
START condition setup		TSU:STA	4700	—	600	—	ns	Only relevant for repeated
time									START condition
Data input hold time		THD:DAT	0	—	0	—	ns
Data input setup time		TSU:DAT	250	—	100	—	ns
STOP condition setup time		TSU:STO	4000	—	600	—	ns
Output valid from clock		TAA	—	3500	—	900	ns	(Note 2)
Bus free time		TBUF	4700	—	1300	—	ns	Time the bus must be free before
									a new transmission can start
Output fall time from VIH		TOF	—	250	20 + 0.1	250	ns		(Note 1), CB ≤ 100 pF
min to VIL max					CB
Input filter spike suppres-		TSP	—	50	—	50	ns	(Note 3)
sion (SDA and SCL pins)
Write cycle time		TWR	—	10	—	10	ms	Byte or Page mode
Endurance	24AA04	—	10M	—	10M	—	cycles	25 °C, Vcc = 5.0V, Block Mode
	24AA08		1M		1M				(Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

		TF			TR
			THIGH
		TLOW
SCL
	TSU:STA		THD:DAT	TSU:DAT	TSU:STO
SCL		THD:STA
	TSP
IN
	TAA	THD:STA	TAA		TBUF
SCL
OUT

1996 Microchip Technology Inc.

DS21053E-page 3

24AA04/08

2.0FUNCTIONAL DESCRIPTION

The 24AA04/08 supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA04/08 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.

3.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24AA04/08 does not generate any acknowledge bits if an internal programming cycle is in progress.

The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL	(A)	(B)	(D)	(D)	(C)	(A)
SDA
		START	ADDRESS OR	DATA	STOP
	CONDITION		ACKNOWLEDGE	ALLOWED	CONDITION
			VALID	TO CHANGE

DS21053E-page 4

1996 Microchip Technology Inc.