Microchip Technology Inc PIC16C71-04-P, PIC16C71-04I-P, PIC16C71-04I-SO, PIC16C710-20-SO, PIC16C710-20I-P Datasheet

PIC16C71X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet:

•PIC16C710

•PIC16C71

•PIC16C711

•PIC16C715

PIC16C71X Microcontroller Core Features:

•High-performance RISC CPU

•Only 35 single word instructions to learn

•All single cycle instructions except for program branches which are two cycle

•Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

•Up to 2K x 14 words of Program Memory, up to 128 x 8 bytes of Data Memory (RAM)

•Interrupt capability

•Eight level deep hardware stack

•Direct, indirect, and relative addressing modes

•Power-on Reset (POR)

•Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

•Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

•Programmable code-protection

•Power saving SLEEP mode

•Selectable oscillator options

•Low-power, high-speed CMOS EPROM technology

•Fully static design

•Wide operating voltage range: 2.5V to 6.0V

•High Sink/Source Current 25/25 mA

•Commercial, Industrial and Extended temperature ranges

•Program Memory Parity Error Checking Circuitry with Parity Error Reset (PER) (PIC16C715)

•Low-power consumption:

-< 2 mA @ 5V, 4 MHz

-15 A typical @ 3V, 32 kHz

-< 1 A typical standby current

PIC16C71X Peripheral Features:

•Timer0: 8-bit timer/counter with 8-bit prescaler

•8-bit multichannel analog-to-digital converter

•Brown-out detection circuitry for Brown-out Reset (BOR)

•13 I/O Pins with Individual Direction Control

PIC16C7X Features																	710				71		711	715
Program Memory (EPROM)																	512					1K	1K	2K
x 14
Data Memory (Bytes) x 8																	36				36		68	128
I/O Pins																	13				13		13	13
Timer Modules																	1				1		1	1
A/D Channels																	4				4		4	4
In-Circuit Serial Programming																	Yes					Yes	Yes	Yes
Brown-out Reset																	Yes					—	Yes	Yes
Interrupt Sources																	4				4		4	4
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
	RA2/AN2																					RA1/AN1
													• 1			18
RA3/AN3/VREF													2	PIC16C71 PIC16C711 PIC16C715	PIC16C710	17						RA0/AN0
RA4/T0CKI													3			16						OSC1/CLKIN
MCLR/VPP													4			15						OSC2/CLKOUT
		VSS											5			14						VDD
	RB0/INT												6			13						RB7
		RB1											7			12						RB6
		RB2											8			11						RB5
		RB3											9			10						RB4
	SSOP
	RA2/AN2												• 1			20						RA1/AN1
RA3/AN3/VREF													2			19						RA0/AN0
RA4/T0CKI													3	PIC16C710 PIC16C711 PIC16C715		18						OSC1/CLKIN
		RB1											8			13						RB6
	MCLR/VPP												4			17						OSC2/CLKOUT
		VSS											5			16						VDD
		VSS											6			15						VDD
	RB0/INT												7			14						RB7
		RB2														12						RB5
													9
		RB3											10			11						RB4

1997 Microchip Technology Inc.

DS30272A-page 1

PIC16C71X
Table of Contents
1.0	General Description ....................................................................................................................................................................	3
2.0	PIC16C71X Device Varieties ......................................................................................................................................................	5
3.0	Architectural Overview ................................................................................................................................................................	7
4.0	Memory Organization ...............................................................................................................................................................	11
5.0	I/O Ports ....................................................................................................................................................................................	25
6.0	Timer0 Module ..........................................................................................................................................................................	31
7.0	Analog - to - Digital Converter (A/D) Module ................................................................................................................................	37
8.0	Special Features of the CPU ....................................................................................................................................................	47
9.0	Instruction Set Summary ..........................................................................................................................................................	69
10.0	Development Support ...............................................................................................................................................................	85
11.0	Electrical Characteristics for PIC16C710 and PIC16C711 .......................................................................................................	89
12.0	DC and AC Characteristics Graphs and Tables for PIC16C710 and PIC16C711 ..................................................................	101
13.0	Electrical Characteristics for PIC16C715 ................................................................................................................................	111
14.0	DC and AC Characteristics Graphs and Tables for PIC16C715 ............................................................................................	125
15.0	Electrical Characteristics for PIC16C71 ..................................................................................................................................	135
16.0	DC and AC Characteristics Graphs and Tables for PIC16C71 ..............................................................................................	147
17.0	Packaging Information ............................................................................................................................................................	155
Appendix A: ......................................................................................................................................................................................		161
Appendix B: Compatibility.................................................................................................................................................................		161
Appendix C: What’s New ..................................................................................................................................................................		162
Appendix D: What’s Changed ..........................................................................................................................................................		162
Index	..................................................................................................................................................................................................	163
PIC16C71X .........................................................................................................................................Product Identification System		173

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.

DS30272A-page 2

1997 Microchip Technology Inc.

PIC16C71X

1.0GENERAL DESCRIPTION

The PIC16C71X is a family of low-cost, high-perfor- mance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family.

All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.

PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC16C710/71 devices have 36 bytes of RAM, the PIC16C711 has 68 bytes of RAM and the PIC16C715 has 128 bytes of RAM. Each device has 13 I/O pins. In addition a timer/counter is available. Also a 4-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.

The PIC16C71X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.

A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-Time- Programmable (OTP) version is suitable for production in any volume.

The PIC16C71X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C71X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor applications).

1.1Family and Upward Compatibility

Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).

1.2Development Support

PIC16C71X devices are supported by the complete line of Microchip Development tools.

Please refer to Section 10.0 for more details about Microchip’s development tools.

1997 Microchip Technology Inc.

DS30272A-page 3

PIC16C71X

TABLE 1-1:

PIC16C71X FAMILY OF DEVICES

PIC16C710

PIC16C71

PIC16C711

PIC16C715

PIC16C72

PIC16CR72(1)

Clock

Maximum Frequency

20

20

20

20

20

20

of Operation (MHz)

EPROM Program Memory

512

1K

1K

2K

2K

—

(x14 words)

Memory

ROM Program Memory

—

—

—

—

—

2K

(14K words)

Data Memory (bytes)

36

36

68

128

128

128

Timer Module(s)

TMR0

TMR0

TMR0

TMR0

TMR0,

TMR0,

TMR1,

TMR1,

TMR2

TMR2

Peripherals

Capture/Compare/PWM

—

—

—

—

1

1

Module(s)

Serial Port(s)

—

—

—

—

SPI/I2C

SPI/I2C

(SPI/I2C, USART)

Parallel Slave Port

—

—

—

—

—

—

A/D Converter (8-bit) Channels

4

4

4

4

5

5

Interrupt Sources

4

4

4

4

8

8

I/O Pins

13

13

13

13

22

22

Voltage Range (Volts)

2.5-6.0

3.0-6.0

2.5-6.0

2.5-5.5

2.5-6.0

3.0-5.5

Features

In-Circuit Serial Programming

Yes

Yes

Yes

Yes

Yes

Yes

Brown-out Reset

Yes

—

Yes

Yes

Yes

Yes

Packages

18-pin DIP,

18-pin DIP,

18-pin DIP,

18-pin DIP,

28-pin SDIP,

28-pin SDIP,

SOIC;

SOIC

SOIC;

SOIC;

SOIC, SSOP

SOIC, SSOP

20-pin SSOP

20-pin SSOP

20-pin SSOP

PIC16C73A

PIC16C74A

PIC16C76

PIC16C77

Clock

Maximum Frequency

20

20

20

20

of Operation (MHz)

EPROM Program Memory

4K

4K

8K

8K

Memory

(x14 words)

Data Memory (bytes)

192

192

376

376

Timer Module(s)

TMR0,

TMR0,

TMR0,

TMR0,

TMR1,

TMR1,

TMR1,

TMR1,

TMR2

TMR2

TMR2

TMR2

Peripherals

Capture/Compare/PWM

2

2

2

2

Module(s)

Serial Port(s)

SPI/I2C, USART

SPI/I2C, USART

SPI/I2C, USART

SPI/I2C, USART

(SPI/I2C, USART)

Parallel Slave Port

—

Yes

—

Yes

A/D Converter (8-bit) Channels

5

8

5

8

Interrupt Sources

11

12

11

12

I/O Pins

22

33

22

33

Voltage Range (Volts)

2.5-6.0

2.5-6.0

2.5-6.0

2.5-6.0

Features

In-Circuit Serial Programming

Yes

Yes

Yes

Yes

Brown-out Reset

Yes

Yes

Yes

Yes

Packages

28-pin SDIP,

40-pin DIP;

28-pin SDIP,

40-pin DIP;

SOIC

44-pin PLCC,

SOIC

44-pin PLCC,

MQFP, TQFP

MQFP, TQFP

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.

Note 1: Please contact your local Microchip sales office for availability of these devices.

DS30272A-page 4

1997 Microchip Technology Inc.

PIC16C71X

2.0PIC16C71X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C71X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

For the PIC16C71X family, there are two device “types” as indicated in the device number:

1.C, as in PIC16C71. These devices have EPROM type memory and operate over the standard voltage range.

2.LC, as in PIC16LC71. These devices have EPROM type memory and operate over an extended voltage range.

2.1UV Erasable Devices

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.

Microchip's PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C71X.

2.2One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.

2.3Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.

2.4Serialized Quick-Turnaround Production (SQTPSM) Devices

Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.

1997 Microchip Technology Inc.

DS30272A-page 5

PIC16C71X

NOTES:

DS30272A-page 6

1997 Microchip Technology Inc.

PIC16C71X

3.0ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches.

The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C71X device.

	Device	Program	Data Memory
		Memory
	PIC16C710	512 x 14	36 x 8
	PIC16C71	1K x 14	36 x 8
	PIC16C711	1K x 14	68 x 8
	PIC16C715	2K x 14	128 x 8

The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly.

PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

1997 Microchip Technology Inc.

DS30272A-page 7

PIC16C71X

FIGURE 3-1: PIC16C71X BLOCK DIAGRAM

Device	Program Memory	Data Memory (RAM)
PIC16C710	512 x 14	36 x 8
PIC16C71	1K x 14	36 x 8
PIC16C711	1K x 14	68 x 8
PIC16C715	2K x 14	128 x 8

	13	Data Bus	8
	Program Counter
EPROM
Program	8 Level Stack	RAM
Memory
	(13-bit)	File
		Registers

Program

14

RAM Addr (1)

9

Bus

Addr MUX

Instruction reg

Direct Addr 7

8

Indirect

Addr

FSR reg

8

STATUS reg

		3	MUX
	Power-up
	Timer
Instruction	Oscillator
Decode &			ALU
	Start-up Timer
Control
	Power-on	8
Timing	Reset		W reg
Generation	Watchdog
OSC1/CLKIN
	Timer
OSC2/CLKOUT	Brown-out
	Reset(2)		Timer0

PORTA

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

PORTB

RB0/INT

RB7:RB1

MCLR VDD, VSS

A/D

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C71.

DS30272A-page 8

1997 Microchip Technology Inc.

									PIC16C71X
	TABLE 3-1:			PIC16C710/71/711/715 PINOUT DESCRIPTION
	Pin Name			DIP	SSOP	SOIC	I/O/P	Buffer	Description
				Pin#	Pin#(4)	Pin#	Type	Type
	OSC1/CLKIN			16	18	16	I	ST/CMOS(3)	Oscillator crystal input/external clock source input.
	OSC2/CLKOUT			15	17	15	O	—	Oscillator crystal output. Connects to crystal or resonator in crystal
									oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
									1/4 the frequency of OSC1, and denotes the instruction cycle rate.
				4	4	4	I/P	ST	Master clear (reset) input or programming voltage input. This pin is
		MCLR/VPP
									an active low reset to the device.
									PORTA is a bi-directional I/O port.
		RA0/AN0		17	19	17	I/O	TTL	RA0 can also be analog input0
	RA1/AN1			18	20	18	I/O	TTL	RA1 can also be analog input1
	RA2/AN2			1	1	1	I/O	TTL	RA2 can also be analog input2
	RA3/AN3/VREF			2	2	2	I/O	TTL	RA3 can also be analog input3 or analog reference voltage
	RA4/T0CKI			3	3	3	I/O	ST	RA4 can also be the clock input to the Timer0 module. Output is
									open drain type.
									PORTB is a bi-directional I/O port. PORTB can be software pro-
									grammed for internal weak pull-up on all inputs.
	RB0/INT			6	7	6	I/O	TTL/ST(1)	RB0 can also be the external interrupt pin.
	RB1			7	8	7	I/O	TTL
	RB2			8	9	8	I/O	TTL
	RB3			9	10	9	I/O	TTL
	RB4			10	11	10	I/O	TTL	Interrupt on change pin.
	RB5			11	12	11	I/O	TTL	Interrupt on change pin.
	RB6			12	13	12	I/O	TTL/ST(2)	Interrupt on change pin. Serial programming clock.
	RB7			13	14	13	I/O	TTL/ST(2)	Interrupt on change pin. Serial programming data.
	VSS			5	4, 6	5	P	—	Ground reference for logic and I/O pins.
	VDD			14	15, 16	14	P	—	Positive supply for logic and I/O pins.

Legend:	I = input	O = output	I/O = input/output	P = power
		— = Not used	TTL = TTL input	ST = Schmitt Trigger input
Note 1:	This buffer is a Schmitt Trigger input when configured as the external interrupt.

2:This buffer is a Schmitt Trigger input when used in serial programming mode.

3:This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

4:The PIC16C71 is not available in SSOP package.

1997 Microchip Technology Inc.

DS30272A-page 9

PIC16C71X

3.1Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.

3.2Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q1	Q2	Q3	Q4	Q1	Q2	Q3	Q4	Q1	Q2	Q3	Q4
OSC1
Q1
Q2											Internal
Q3											phase
											clock
Q4
PC		PC			PC+1					PC+2
OSC2/CLKOUT
(RC mode)	Fetch INST (PC)
	Execute INST (PC-1)				Fetch INST (PC+1)
					Execute INST (PC)				Fetch INST (PC+2)
									Execute INST (PC+1)

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

Tcy0

Tcy1

Tcy2

Tcy3

Tcy4

Tcy5

1.

MOVLW 55h

Fetch 1

Execute 1

2.

MOVWF PORTB

Fetch 2

Execute 2

3.

CALL SUB_1

Fetch 3

Execute 3

4.

BSF PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5.

Instruction @ address SUB_1

Fetch SUB_1

Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS30272A-page 10

1997 Microchip Technology Inc.

PIC16C71X

4.0 MEMORY ORGANIZATION	FIGURE 4-2: PIC16C71/711 PROGRAM
	MEMORY MAP AND STACK

4.1	Program Memory Organization
The PIC16C71X family has a 13-bit program counter										PC<12:0>
capable of addressing an 8K x 14 program memory						CALL, RETURN				13
space. The amount of program memory available to						RETFIE, RETLW
each device is listed below:
			Program					Stack Level 1
	Device			Address Range
			Memory
PIC16C710			512 x 14	0000h-01FFh				Stack Level 8
PIC16C71			1K x 14	0000h-03FFh
PIC16C711			1K x 14	0000h-03FFh				Reset Vector			0000h
PIC16C715			2K x 14	0000h-07FFh
					MemoryUser	Space
The reset vector is at 0000h and the interrupt vector is										Memory
For those devices with less than 8K program memory,
accessing a location above the physically implemented								Interrupt Vector			0004h
address will cause a wraparound.
							On-chip Program				0005h
at 0004h.											03FFh
FIGURE 4-1:		PIC16C710 PROGRAM
											0400h
		MEMORY MAP AND STACK
			PC<12:0>								1FFFh
	CALL, RETURN		13
	RETFIE, RETLW				FIGURE 4-3:		PIC16C715 PROGRAM
		Stack Level 1					MEMORY MAP AND STACK
										PC<12:0>
		Stack Level 8				CALL, RETURN				13
						RETFIE, RETLW
		Reset Vector		0000h			Stack Level 1
MemoryUser
	Space		Memory				Stack Level 8
		Interrupt Vector		0004h
		On-chip Program		0005h			Reset Vector				0000h
				01FFh
				0200h			Interrupt Vector				0004h
											0005h
				1FFFh
							On-chip Program
									Memory
											07FFh
											0800h
											1FFFh
1997 Microchip Technology Inc.											DS30272A-page 11

PIC16C71X

4.2Data Memory Organization

The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1 → Bank 1

RP0 (STATUS<5>) = 0 → Bank 0

Each Bank extends up to 7Fh (128 bytes). The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. Both Bank 0 and Bank 1 contain special function registers. Some "high use" special function registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access.

4.2.1GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5).

FIGURE 4-4: PIC16C710/71 REGISTER FILE MAP

File									File
Address							Address
00h					INDF(1)	INDF(1)			80h
01h					TMR0	OPTION			81h
02h					PCL	PCL			82h
03h									83h
					STATUS	STATUS
04h									84h
					FSR	FSR
05h					PORTA	TRISA			85h
06h					PORTB	TRISB			86h
07h						PCON(2)			87h
08h					ADCON0	ADCON1			88h
09h					ADRES	ADRES			89h
0Ah					PCLATH	PCLATH			8Ah
0Bh					INTCON	INTCON			8Bh
0Ch						General			8Ch
					General	Purpose
						Register
					Purpose
					Register	Mapped
						in Bank 0(3)
2Fh									AFh
30h									B0h

7Fh			FFh
	Bank 0	Bank 1

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2:The PCON register is not implemented on the PIC16C71.

3:These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register.

DS30272A-page 12

1997 Microchip Technology Inc.

PIC16C71X

FIGURE 4-5: PIC16C711 REGISTER FILE MAP

File							File
Address					Address
00h			INDF(1)	INDF(1)			80h
01h			TMR0	OPTION			81h
02h			PCL	PCL			82h
03h							83h
			STATUS	STATUS
04h							84h
			FSR	FSR
05h			PORTA	TRISA			85h
06h			PORTB	TRISB			86h
07h				PCON			87h
08h			ADCON0	ADCON1			88h
09h			ADRES	ADRES			89h
0Ah			PCLATH	PCLATH			8Ah
0Bh			INTCON	INTCON			8Bh
0Ch				General			8Ch
			General	Purpose
				Register
			Purpose
			Register	Mapped
				in Bank 0(2)
4Fh							CFh
							D0h
50h

7Fh			FFh
	Bank 0	Bank 1

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2:These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register.

FIGURE 4-6: PIC16C715 REGISTER FILE MAP

File										File
Address								Address
00h				INDF(1)			INDF(1)			80h
01h				TMR0			OPTION			81h
02h				PCL			PCL			82h
03h				STATUS			STATUS			83h
										84h
04h				FSR			FSR
05h				PORTA			TRISA			85h
06h				PORTB			TRISB			86h
07h										87h
08h										88h
09h										89h
0Ah				PCLATH			PCLATH			8Ah
0Bh				INTCON			INTCON			8Bh
0Ch				PIR1			PIE1			8Ch
0Dh										8Dh
0Eh							PCON			8Eh
0Fh										8Fh
10h										90h
11h										91h
12h										92h
13h										93h
14h										94h
15h										95h
16h										96h
17h										97h
18h										98h
19h										99h
1Ah										9Ah
1Bh										9Bh
1Ch										9Ch
1Dh										9Dh
1Eh				ADRES						9Eh
1Fh				ADCON0			ADCON1			9Fh
20h				General			General			A0h
				Purpose			Purpose
				Register			Register			BFh
										C0h

7Fh			FFh
	Bank 0	Bank 1

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

1997 Microchip Technology Inc.

DS30272A-page 13

PIC16C71X

4.2.2SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The special function registers can be classified into two sets (core and peripheral). Those registers associated with the “core”functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.

TABLE 4-1:

PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY

Value on:

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

(1)

Bank 0

00h(3)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000

0000

0000

0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h(3)

PCL

Program Counter's (PC) Least Significant Byte

0000

0000

0000

0000

03h(3)

STATUS

IRP(5)

RP1(5)

RP0

Z

DC

C

TO

PD

0001

1xxx

000q

quuu

04h(3)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

—

—

—

PORTA Data Latch when written: PORTA pins when read

---x 0000

---u 0000

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

—

Unimplemented

—

—

08h

ADCON0

ADCS1

ADCS0

(6)

CHS1

CHS0

ADIF

ADON

00-0 0000

00-0 0000

GO/DONE

09h(3)

ADRES

A/D Result Register

xxxx xxxx

uuuu uuuu

0Ah(2,3)

PCLATH

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh(3)

INTCON

GIE

ADIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000

000x

0000

000u

Bank 1

80h(3)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000

0000

0000

0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111

1111

1111

1111

82h(3)

PCL

Program Counter's (PC) Least Significant Byte

0000

0000

0000

0000

83h(3)

STATUS

IRP(5)

RP1(5)

RP0

Z

DC

C

TO

PD

0001

1xxx

000q

quuu

84h(3)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

—

—

—

PORTA Data Direction Register

---1 1111

---1 1111

86h

TRISB

PORTB Data Direction Control Register

1111

1111

1111

1111

87h(4)

PCON

—

—

—

—

—

—

---- --qq

---- --uu

POR

BOR

88h

ADCON1

—

—

—

—

—

—

PCFG1

PCFG0

---- --00

---- --00

89h(3)

ADRES

A/D Result Register

xxxx xxxx

uuuu uuuu

8Ah(2,3)

PCLATH

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh(3)

INTCON

GIE

ADIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000

000u

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’.

Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter.

3:These registers can be addressed from either bank.

4:The PCON register is not physically implemented in the PIC16C71, read as ’0’.

5:The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear.

6:Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented, read as '0'.

DS30272A-page 14

1997 Microchip Technology Inc.

PIC16C71X

TABLE 4-2:

PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY

Value on:

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR, PER

(3)

Bank 0

00h(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h(1)

STATUS

IRP(4)

RP1(4)

RP0

Z

DC

C

0001 1xxx

000q quuu

TO

PD

04h(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

—

—

—

PORTA Data Latch when written: PORTA pins when read

---x 0000

---u 0000

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

—

Unimplemented

—

—

08h

—

Unimplemented

—

—

09h

—

Unimplemented

—

—

0Ah(1,2)

PCLATH

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF

—

—

—

—

—

—

-0-- ----

-0-- ----

0Dh

—

Unimplemented

—

—

0Eh

—

Unimplemented

—

—

0Fh

—

Unimplemented

—

—

10h

—

Unimplemented

—

—

11h

—

Unimplemented

—

—

12h

—

Unimplemented

—

—

13h

—

Unimplemented

—

—

14h

—

Unimplemented

—

—

15h

—

Unimplemented

—

—

16h

—

Unimplemented

—

—

17h

—

Unimplemented

—

—

18h

—

Unimplemented

—

—

19h

—

Unimplemented

—

—

1Ah

—

Unimplemented

—

—

1Bh

—

Unimplemented

—

—

1Ch

—

Unimplemented

—

—

1Dh

—

Unimplemented

—

—

1Eh

ADRES

A/D Result Register

xxxx xxxx

uuuu uuuu

1Fh

ADCON0

ADCS1

ADCS0

CHS2

CHS1

CHS0

—

ADON

0000 00-0

0000 00-0

GO/DONE

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter.

3:Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4:The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.

1997 Microchip Technology Inc.

DS30272A-page 15

PIC16C71X

TABLE 4-2:		PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
																						Value on:	Value on all
Address	Name		Bit 7		Bit 6	Bit 5	Bit 4			Bit 3			Bit 2				Bit 1			Bit 0		POR,	other resets
																						BOR, PER	(3)
Bank 1
80h(1)	INDF	Addressing this location uses contents of FSR to address data memory (not a physical register)																				0000 0000	0000 0000
81h	OPTION				INTEDG	T0CS	T0SE			PSA				PS2			PS1			PS0		1111 1111	1111 1111
			RBPU
82h(1)	PCL	Program Counter's (PC) Least Significant Byte																				0000 0000	0000 0000
83h(1)	STATUS		IRP(4)		RP1(4)	RP0		TO			PD			Z			DC			C		0001 1xxx	000q quuu
84h(1)	FSR	Indirect data memory address pointer																				xxxx xxxx	uuuu uuuu
85h	TRISA		—		—	PORTA Data Direction Register																--11 1111	--11 1111
86h	TRISB	PORTB Data Direction Register																				1111 1111	1111 1111
87h	—	Unimplemented																				—	—
88h	—	Unimplemented																				—	—
89h	—	Unimplemented																				—	—
8Ah(1,2)	PCLATH		—		—	—	Write Buffer for the upper 5 bits of the PC															---0 0000	---0 0000
8Bh(1)	INTCON		GIE		PEIE	T0IE	INTE			RBIE				T0IF		INTF			RBIF			0000 000x	0000 000u
8Ch	PIE1		—		ADIE	—		—			—			—			—			—		-0-- ----	-0-- ----
8Dh	—	Unimplemented																				—	—
8Eh	PCON	MPEEN			—	—		—			—											u--- -1qq	u--- -1uu
														PER			POR			BOR
8Fh	—	Unimplemented																				—	—
90h	—	Unimplemented																				—	—
91h	—	Unimplemented																				—	—
92h	—	Unimplemented																				—	—
93h	—	Unimplemented																				—	—
94h	—	Unimplemented																				—	—
95h	—	Unimplemented																				—	—
96h	—	Unimplemented																				—	—
97h	—	Unimplemented																				—	—
98h	—	Unimplemented																				—	—
99h	—	Unimplemented																				—	—
9Ah	—	Unimplemented																				—	—
9Bh	—	Unimplemented																				—	—
9Ch	—	Unimplemented																				—	—
9Dh	—	Unimplemented																				—	—
9Eh	—	Unimplemented																				—	—
9Fh	ADCON1		—		—	—		—			—			—		PCFG1			PCFG0			---- --00	---- --00

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter.

3:Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4:The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.

DS30272A-page 16

1997 Microchip Technology Inc.

PIC16C71X

4.2.2.1STATUS REGISTER

Applicable Devices 710 71 711 715

The STATUS register, shown in Figure 4-7, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary."

Note 1: For those devices that do not use bits IRP and RP1 (STATUS<7:6>), maintain these bits clear to ensure upward compatibility with future products.

Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0	R/W-0 R/W-0		R-1			R-1			R/W-x	R/W-x	R/W-x
IRP	RP1	RP0		TO			PD		Z	DC	C
bit7											bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

bit

3:

PD: Power-down bit

1

= After power-up or by the CLRWDT instruction

0

= By execution of the SLEEP instruction

bit

2:

Z: Zero bit

1

= The result of an arithmetic or logic operation is zero

0

= The result of an arithmetic or logic operation is not zero

bit

1:

DC: Digit carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)

1

= A carry-out from the 4th low order bit of the result occurred

0

= No carry-out from the 4th low order bit of the result

bit

0:

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

C: Carry/borrow

1

= A carry-out from the most significant bit of the result occurred

0

= No carry-out from the most significant bit of the result occurred

Note: For

the polarity is reversed. A subtraction is executed by adding the two’s complement of

borrow

the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order

bit of the source register.

1997 Microchip Technology Inc.

DS30272A-page 17

PIC16C71X

4.2.2.2

OPTION REGISTER

Note:

To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

Applicable Devices

710

71

711

715

the Watchdog Timer by setting bit PSA

The OPTION register is a readable and writable regis-

(OPTION<3>).

ter which contains various control bits to configure the

TMR0/WDT prescaler, the External INT Interrupt,

TMR0, and the weak pull-ups on PORTB.

FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

PORTB Pull-up Enable bit

RBPU:

1

= PORTB pull-ups are disabled

0

= PORTB pull-ups are enabled by individual port latch values

bit

6:

INTEDG: Interrupt Edge Select bit

1

= Interrupt on rising edge of RB0/INT pin

0

= Interrupt on falling edge of RB0/INT pin

bit

5:

T0CS: TMR0 Clock Source Select bit

1

= Transition on RA4/T0CKI pin

0

= Internal instruction cycle clock (CLKOUT)

bit

4:

T0SE: TMR0 Source Edge Select bit

1

= Increment on high-to-low transition on RA4/T0CKI pin

0

= Increment on low-to-high transition on RA4/T0CKI pin

bit

3:

PSA: Prescaler Assignment bit

1

= Prescaler is assigned to the WDT

0

= Prescaler is assigned to the Timer0 module

bit

2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

1 : 2

1 : 1

001

1 : 4

1 : 2

010

1 : 8

1 : 4

011

1 : 16

1 : 8

100

1 : 32

1 : 16

101

1 : 64

1 : 32

110

1 : 128

1 : 64

111

1 : 256

1 : 128

DS30272A-page 18

1997 Microchip Technology Inc.

PIC16C71X

4.2.2.3

INTCON REGISTER

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

Applicable Devices

710

71

711

715

its corresponding enable bit or the global

The INTCON Register is a readable and writable regis-

enable bit, GIE (INTCON<7>).

ter which contains various enable and flag bits for the

TMR0 register overflow, RB Port change and External

RB0/INT pin interrupts.

FIGURE 4-9: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-x

GIE

ADIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

GIE:(1) Global Interrupt Enable bit

1

= Enables all un-masked interrupts

0

= Disables all interrupts

bit

6:

ADIE: A/D Converter Interrupt Enable bit

1

= Enables A/D interrupt

0

= Disables A/D interrupt

bit

5:

T0IE: TMR0 Overflow Interrupt Enable bit

1

= Enables the TMR0 interrupt

0

= Disables the TMR0 interrupt

bit

4:

INTE: RB0/INT External Interrupt Enable bit

1

= Enables the RB0/INT external interrupt

0

= Disables the RB0/INT external interrupt

bit

3:

RBIE: RB Port Change Interrupt Enable bit

1

= Enables the RB port change interrupt

0

= Disables the RB port change interrupt

bit

2:

T0IF: TMR0 Overflow Interrupt Flag bit

1

= TMR0 register has overflowed (must be cleared in software)

0

= TMR0 register did not overflow

bit

1:

INTF: RB0/INT External Interrupt Flag bit

1

= The RB0/INT external interrupt occurred (must be cleared in software)

0

= The RB0/INT external interrupt did not occur

bit

0:

RBIF: RB Port Change Interrupt Flag bit

1

= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0

= None of the RB7:RB4 pins have changed state

Note 1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 8.5 for a detailed description.

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

1997 Microchip Technology Inc.

DS30272A-page 19

PIC16C71X

4.2.2.4

PIE1 REGISTER

Note: Bit PEIE

(INTCON<6>) must be set to

enable any peripheral interrupt.

Applicable Devices

710

71

711

715

This register contains the individual enable bits for the

Peripheral interrupts.

FIGURE 4-10: PIE1 REGISTER (ADDRESS 8Ch)

U-0

R/W-0

U-0

U-0

U-0

U-0

U-0

U-0

—

ADIE

—

—

—

—

—

—

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit 6:

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5-0: Unimplemented: Read as '0'

DS30272A-page 20

1997 Microchip Technology Inc.

PIC16C71X

4.2.2.5

PIR1 REGISTER

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

Applicable Devices

710

71

711

715

its corresponding enable bit or the global

This register contains the individual flag bits for the

enable bit, GIE (INTCON<7>). User soft-

Peripheral interrupts.

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch)

U-0

R/W-0

U-0

U-0

U-0

U-0

U-0

U-0

—

ADIF

—

—

—

—

—

—

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit 6:

ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed

0 = The A/D conversion is not complete

bit 5-0: Unimplemented: Read as '0'

1997 Microchip Technology Inc.

DS30272A-page 21

PIC16C71X

4.2.2.6

PCON REGISTER

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

Applicable Devices

710

71

711

715

on subsequent resets to see if BOR is

The Power Control (PCON) register contains a flag bit

clear, indicating a brown-out has occurred.

The

status bit is a don't care and is

to allow differentiation

between a Power-on

Reset

BOR

not necessarily predictable if the brown-out

(POR) to an external MCLR

Reset or WDT Reset.

circuit is disabled (by clearing the BODEN

Those devices with brown-out detection circuitry con-

bit in the Configuration word).

tain an additional bit to differentiate a Brown-out Reset

(BOR) condition from a Power-on Reset condition. For

the PIC16C715 the PCON register also contains status

bits MPEEN and PER. MPEEN reflects the value of the

MPEEN bit in the configuration word. PER indicates a

parity error reset has occurred.

FIGURE 4-12: PCON REGISTER (ADDRESS 8Eh), PIC16C710/711

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-q

—

—

—

—

—

—

R

= Readable bit

POR

BOR

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-2:

Unimplemented: Read as '0'

bit

1:

Power-on Reset Status bit

POR:

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit

0:

Brown-out Reset Status bit

BOR:

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh), PIC16C715

R-U

U-0

U-0

U-0

U-0

R/W-1

R/W-0

R/W-q

MPEEN

—

—

—

—

(1)

R

= Readable bit

PER

POR

BOR

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7: MPEEN: Memory Parity Error Circuitry Status bit

Reflects the value of configuration word bit, MPEEN

bit 6-3:

Unimplemented: Read as '0'

bit

2:

Memory Parity Error Reset Status bit

PER:

1 = No Error occurred

0 = Program Memory Fetch Parity Error occurred (must be set in software after a Parity Error Reset)

bit

1:

Power-on Reset Status bit

POR:

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit

0:

Brown-out Reset Status bit

BOR:

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS30272A-page 22

1997 Microchip Technology Inc.

PIC16C71X

4.3PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-14: LOADING OF PC IN DIFFERENT SITUATIONS

				PCH											PCL
12							8			7								0		Instruction with
PC																				PCL as
		5					PCLATH<4:0>												8	Destination
																				ALU
								PCLATH
			PCH												PCL
12		11			10		8			7								0
PC																				GOTO, CALL
2			PCLATH<4:3>															11		Opcode <10:0>
							PCLATH

4.3.1COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note “Implementing aTable Read" (AN556).

4.3.2STACK

The PIC16CXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Note 1: There are no status bits to indicate stack overflow or stack underflow conditions.

Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

4.4Program Memory Paging

The PIC16C71X devices ignore both paging bits (PCLATH<4:3>, which are used to access program memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC16C71X is not recommended since this may affect upward compatibility with future products.

1997 Microchip Technology Inc.

DS30272A-page 23

PIC16C71X

Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

		PAGE 1 FROM PAGE 0
ORG 0x500
BSF	PCLATH,3	;Select page 1 (800h-FFFh)
BCF	PCLATH,4	;Only on >4K devices
CALL	SUB1_P1	;Call subroutine in
	:	;page 1 (800h-FFFh)
	:
	:
ORG 0x900
SUB1_P1:		;called subroutine
	:	;page 1 (800h-FFFh)
	:
RETURN		;return to Call subroutine
		;in page 0 (000h-7FFh)

4.5Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00hWriting. to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-15. However, IRP is not used in the PIC16C71X devices.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: INDIRECT ADDRESSING

	movlw	0x20	;initialize pointer
	movwf	FSR	;to RAM
NEXT	clrf	INDF	;clear INDF register
	incf	FSR,F	;inc pointer
	btfss	FSR,4	;all done?
	goto	NEXT	;no clear next
CONTINUE
	:		;yes continue

FIGURE 4-15:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

RP1:RP0

6

from opcode

0

IRP(1) 7

FSR register

0

bank select

location select

00

01

10

11

bank select

location select

00h

80h

100h

180h

Data

Not

Used

Memory

7Fh

FFh

17Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

For register file map detail see Figure 4-4.

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

DS30272A-page 24

1997 Microchip Technology Inc.

PIC16C71X

5.0I/O PORTS

Applicable Devices 710 71 711 715

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1PORTA and TRISA Registers

PORTA is a 5-bit latch.

The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input.

Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin.

Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 5-1: INITIALIZING PORTA

BCF	STATUS, RP0	;
CLRF	PORTA	; Initialize PORTA by
		; clearing output
		; data latches
BSF	STATUS, RP0	; Select Bank 1
MOVLW	0xCF	; Value used to
		; initialize data
		; direction
MOVWF	TRISA	; Set RA<3:0> as inputs
		; RA<4> as outputs
		; TRISA<7:5> are always
		; read as '0'.

FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0 PINS

Data
bus		D	Q
WR				VDD
Port		CK	Q
				P
		Data Latch
		D	Q	N	I/O pin(1)
WR
TRIS		CK	Q	VSS
				Analog
		TRIS Latch		input
				mode
			RD TRIS		TTL
					input
			Q	D	buffer
				EN
RD PORT
To A/D Converter
Note	1:	I/O pins have protection diodes to VDD and
		VSS.

FIGURE 5-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Data
bus	D	Q
WR
PORT	CK	Q		I/O pin(1)
			N
	Data Latch
	D	Q	VSS
WR
TRIS	CK	Q	Schmitt
			Trigger
	TRIS Latch		input
			buffer
	RD TRIS
		Q	D
			ENEN
RD PORT
TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

1997 Microchip Technology Inc.

DS30272A-page 25

PIC16C71X

TABLE 5-1:

PORTA FUNCTIONS

Name

Bit#

Buffer

Function

RA0/AN0

bit0

TTL

Input/output or analog input

RA1/AN1

bit1

TTL

Input/output or analog input

RA2/AN2

bit2

TTL

Input/output or analog input

RA3/AN3/VREF

bit3

TTL

Input/output or analog input/VREF

RA4/T0CKI

bit4

ST

Input/output or external clock input for Timer0

Output is open drain type

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on:

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

05h

PORTA

—

—

—

RA4

RA3

RA2

RA1

RA0

---x 0000

---u 0000

85h

TRISA

—

—

—

PORTA Data Direction Register

---1 1111

---1 1111

9Fh

ADCON1

—

—

—

—

—

—

PCFG1

PCFG0

---- --00

---- --00

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'Shaded. cells are not used by PORTA.

DS30272A-page 26

1997 Microchip Technology Inc.

PIC16C71X

5.2PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

BCF	STATUS, RP0	;
CLRF	PORTB	; Initialize PORTB by
		; clearing output
		; data latches
BSF	STATUS, RP0	; Select Bank 1
MOVLW	0xCF	; Value used to
		; initialize data
		; direction
MOVWF	TRISB	; Set RB<3:0> as inputs
		; RB<5:4> as outputs
		; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

FIGURE 5-3: BLOCK DIAGRAM OF RB3:RB0 PINS

VDD

RBPU(2)

Data bus

WR Port

WR TRIS

RB0/INT

			P	weak
				pull-up
	Data Latch
	D	Q
	CK			I/O
				pin(1)
	TRIS Latch
	D	Q	TTL
	CK		Input
			Buffer
	RD TRIS
		Q	D
	RD Port		EN
	Schmitt Trigger		RD Port
	Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2:TRISB = ’1’ enables weak pull-up if RBPU = ’0’ (OPTION<7>).

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch”outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a)Any read or write of PORTB. This will end the mismatch condition.

b)Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552).

Note: For the PIC16C71

if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then interrupt flag bit RBIF may not get set.

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

1997 Microchip Technology Inc.

DS30272A-page 27

PIC16C71X

FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C71)

VDD

RBPU(2)			P	weak
				pull-up
Data bus	Data Latch
	D	Q
WR Port				I/O
	CK			pin(1)
	TRIS Latch
	D	Q
WR TRIS	CK		TTL
			Input
			Buffer	ST
				Buffer
	RD TRIS		Latch
		Q	D
Set RBIF	RD Port		EN
From other		Q	D
RB7:RB4 pins
			EN
			RD Port
RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2:TRISB = ’1’ enables weak pull-up if RBPU = ’0’ (OPTION<7>).

FIGURE 5-5: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C710/711/715)

VDD

RBPU(2)			P	weak
				pull-up
Data bus	Data Latch
	D	Q
WR Port				I/O
	CK			pin(1)
	TRIS Latch
	D	Q
WR TRIS	CK		TTL
			Input
			Buffer	ST
				Buffer
	RD TRIS		Latch
		Q	D
Set RBIF	RD Port		EN	Q1
From other		Q	D
				RD Port
RB7:RB4 pins
			EN	Q3
RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2:TRISB = ’1’ enables weak pull-up if RBPU = ’0’ (OPTION<7>).

TABLE 5-3:	PORTB FUNCTIONS
Name	Bit#	Buffer	Function
RB0/INT	bit0	TTL/ST(1)	Input/output pin or external interrupt input. Internal software
			programmable weak pull-up.
RB1	bit1	TTL	Input/output pin. Internal software programmable weak pull-up.
RB2	bit2	TTL	Input/output pin. Internal software programmable weak pull-up.
RB3	bit3	TTL	Input/output pin. Internal software programmable weak pull-up.
RB4	bit4	TTL	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up.
RB5	bit5	TTL	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up.
RB6	bit6	TTL/ST(2)	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up. Serial programming clock.
RB7	bit7	TTL/ST(2)	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

DS30272A-page 28

1997 Microchip Technology Inc.

PIC16C71X

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on:

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

06h, 106h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

86h, 186h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

81h, 181h

OPTION

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

RBPU

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

1997 Microchip Technology Inc.

DS30272A-page 29

PIC16C71X

5.3I/O Programming Considerations

5.3.1BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-3 shows the effect of two sequential read- modify-write instructions on an I/O port.

FIGURE 5-6: SUCCESSIVE I/O OPERATION

EXAMPLE 5-3: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry
;
;	PORT latch	PORT pins
;	----------	---------
BCF PORTB, 7	; 01pp pppp	11pp pppp
BCF PORTB, 6	; 10pp pppp	11pp pppp
BSF STATUS, RP0	;
BCF TRISB, 7	; 10pp pppp	11pp pppp
BCF TRISB, 6	; 10pp pppp	10pp pppp

;

;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”,“wired-and”). The resulting high output currents may damage the chip.

5.3.2SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-6). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

PC

PC

PC + 1

PC + 2

PC + 3

Instruction

MOVWF PORTB

MOVF PORTB,W

fetched

NOP

NOP

write to

PORTB

RB7:RB0

Port pin

Instruction

TPD

sampled here

NOP

executed

MOVWF PORTB

MOVF PORTB,W

write to

PORTB

Note:

This example shows a write to PORTB followed by a read from PORTB.

Note that:

data setup time = (0.25TCY - TPD)

where TCY = instruction cycle TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

DS30272A-page 30

1997 Microchip Technology Inc.