Microchip Technology Inc 28LV64A-T-20-P, 28LV64A-T-20-L, 28LV64A-FT-30I-VS, 28LV64A-FT-30I-TS, 28LV64A-FT-30I-SO Datasheet

28LV64A

64K (8K x 8) Low Voltage CMOS EEPROM

FEATURES

•2.7V to 3.6V Supply

•Read Access Time—300 ns

•CMOS Technology for Low Power Dissipation

-8 mA Active

-50 A CMOS Standby Current

•Byte Write Time—3 ms

•Data Retention >200 years

•High Endurance - Minimum 100,000 Erase/Write Cycles

•Automatic Write Operation

-Internal Control Timer

-Auto-Clear Before Write Operation

-On-Chip Address and Data Latches

•Data Polling

•Ready/Busy

•Chip Clear Operation

•Enhanced Data Protection

-VCC Detector

-Pulse Filter

-Write Inhibit

•Electronic Signature for Device Identification

•Organized 8Kx8 JEDEC Standard Pinout

-28-pin Dual-In-Line Package

-32-pin Chip Carrier (Leadless or Plastic)

-28-pin Thin Small Outline Package (TSOP) 8x20mm

-28-pin Very Small Outline Package (VSOP) 8x13.4mm

•Available for Extended Temperature Ranges:

-Commercial: 0˚C to +70˚C

-Industrial: -40˚C to +85˚C

PACKAGE TYPES

RDY/BSY	• 1		28	Vcc			3 A12	RDY/BSY2		32 Vcc	31 WE
A12	2		27	WE		4 A7			1 NU			30 NC
A7	3		26	NC
A6	4	DIP/SOIC	25	A8	A6	5						29	A8
A5	5		24	A9
					A5	6			PLCC/LCC			28	A9
A4	6		23	A11	A4	7						27	A11
A3	7		22	OE	A3 8							26	NC
A2	8		21	A10	A2	9						25	OE
A1	9		20	CE	A1	10						24	A10
					A0	11						23	CE
A0	10		19	I/O7
					NC 12							22	I/O7
I/O0	11		18	I/O6
					I/O0	13						21	I/O6
I/O1	12		17	I/O5		14	15	16	17	18	19	20
I/O2	13		16	I/O4
						I/O1	I/O2	Vss	NU	I/O3	I/O4	I/O5
VSS	14		15	I/O3
	• Pin 1 indicator on PLCC on top of package
OE	1										28	A10
A11	2										27	CE
A9	3										26	I/07
A8	4										25	I/06
NC	5				TSOP						24	I/05
WE	6										23	I/04
Vcc	7										22	I/03
RDY/BSY	8										21	Vss
A12	9										20	I/02
A7	10										19	I/01
A6	11										18	I/00
A5	12										17	A0
A4	13										16	A1
A3	14										15	A2
OE	22									21		A10
A11	23									20		CE
A9	24									19		I/O7
A8	25									18		I/O6
NC	26				VSOP					17		I/O5
WE	27									16		I/O4
VCC	28									15		I/O3
RDY/BSY	1									14		VSS
A12	2									13		I/O2
A7	3									12		I/O1
A6	4									11		I/O0
A5	5									10		A0
A4	6										9	A1
A3	7										8	A2

DESCRIPTION		BLOCK DIAGRAM
						I/O0...................I/O7
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-		VSS
atile electrically Erasable PROM organized as 8K words by 8 bits.			Data Protection
		VCC
The 28LV64A is accessed like a static RAM for the read or write				Circuitry
				Chip Enable/
cycles without the need of external components. During a “byte		CE
write”, the address and data are latched internally, freeing the		OE		Output Enable
				Control Logic
microprocessor address and data bus for other operations. Fol-		WE	Auto Erase/Write		Data	Input/Output
lowing the initiation of write cycle, the device will go to a busy state				Timing	Poll	Buffers
		Rdy/
and automatically clear and write the latched data using an inter-			Program Voltage
		Busy
nal control timer. To determine when the write cycle is complete,				Generation
the user has a choice of monitoring the Ready/Busy output or		A0		Y
using Data polling. The Ready/Busy pin is an open drain output,		I				Y Gating
		I	L	Decoder
which allows easy configuration in ‘wired-or’ systems.	Alterna-	I
		I	a
			t
tively, Data polling allows the user to read the location last written		I
			c
		I
to when the write operation is complete. CMOS design and pro-			h
		I		X		64K bit
			e
		I
cessing enables this part to be used in systems where reduced			s	Decoder		Cell Matrix
		I
power consumption and reliability are required. A complete family		I
		I
of packages is offered to provide the utmost flexibility in applica-		A12
tions.
1996 Microchip Technology Inc.	Preliminary					DS21113B-page 1

28LV64A

1.0ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS*

VCC and input voltages w.r.t. VSS ......			-0.6V to + 6.25V
Voltage on		w.r.t. VSS	-0.6V to +13.5V
	OE
Voltage on A9 w.r.t. VSS.......................			-0.6V to +13.5V
Output Voltage w.r.t. VSS ...............			-0.6V to VCC+0.6V
Storage temperature ..........................			-65˚C to +150˚C
Ambient temp. with power applied .....			-55°C to +125°C

*Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUCTION TABLE

	Name								Function
	A0 - A12						Address Inputs
							Chip Enable
	CE
							Output Enable
	OE
							Write Enable
	WE
	I/O0 - I/O7						Data Inputs/Outputs
	RDY/Busy						Ready/Busy
	VCC						+ Power Supply
	VSS						Ground
	NC						No Connect; No Internal Connection
	NU						Not Used; No External Connection is
							Allowed

TABLE 1-2:	READ/WRITE OPERATION DC CHARACTERISTICS
		VCC = 2.7 to 3.6V		0°C to 70°C
		Commercial (C): Tamb =
		Industrial	(I): Tamb =	-40°C to 85°C
Parameter		Status	Symbol	Min	Max	Units			Conditions
Input Voltages		Logic “1”	VIH	2.0		V
		Logic “2”	VIL		0.6	V
Input Leakage		—	I LI	—	5	A	VIN = 0V to VCC+1
Input Capacitance		—	C IN	—	6	pF	Vin = 0V; Tamb = 25 °C;
							f = 1 MHz (Note 1)
Output Voltages		Logic “1”	VOH	2.0		V	IOH = -100 A
		Logic “0”	VOL		0.3	V		IOL = 1.0 mA
								I0L = 2.0 mA for RDY/Busy
Output Leakage		—	I LO	—	5	A	VOUT = 0V to VCC+0.1V
Output Capacitance		—	C OUT	—	12	pF	V OUT = 0V; Tamb = 25°C;
							f = 1 MHz (Note 1)
Power Supply Current, Activity		TTL input	ICC	—	8	mA	f = 5 MHz (Note 2)
								IO = OmA
								VCC = 3.3
									= VIL
								CE
Power Supply Current, Standby		TTL input	ICC(S)TTL	—	2	mA			= VIH (0°C to 70°C°)
								CE
		TTL input	ICC(S)TTL		3	mA			= VIH (-40°C to 85°C°)
								CE
		CMOS input	ICC(S)CMOS		100	A			= VCC -3.0 to VCC+1
								CE
Note 1: Not 100% tested.
2: AC power supply current above 5 MHz: 2 mA/Mhz.

DS21113B-page 2

Preliminary

1996 Microchip Technology Inc.

28LV64A

TABLE 1-3: READ OPERATION AC CHARACTERISTICS

AC Testing Waveform:

VIH = 2.0V;

VIL = 0.6V; VOH = VOL = VCC/2

Output Load:

1 TTL Load + 100 pF

Input Rise and Fall Times:

20 ns

Ambient Temperature:

Commercial (C): Tamb = 0°C to +70°C

Industrial

(I) : Tamb = -40°C to +85°C

Parameter

Sym

28LV64-30

Units

Conditions

Min

Max

Address to Output Delay

tACC

—

300

ns

=

= VIL

OE

CE

to Output Delay

tCE

—

300

ns

= VIL

CE

OE

to Output Delay

tOE

—

150

ns

= VIL

OE

CE

or

High to Output Float

tOFF

0

60

ns

(Note 1)

CE

OE

Output Hold from Address,

or

tOH

0

—

ns

(Note 1)

CE

OE,

whichever occurs first.

Endurance

—

10M

—

cycles

25 °C, Vcc = 5.0V,

Block Mode (Note 2)

Note 1: Not 100% tested.

2:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: READ WAVEFORMS

Address	VIH	Address Valid
	VIL
	VIH
CE	VIL
		tCE(2)
	VIH
OE			tOFF(1,3)
	VIL	tOE(2)
			tOH
	VOH		High Z
Data	High Z
	VOL		Valid Output
		tACC
WE	VIH
	VIL

Notes: (1) tOFF is specified for OE or CE, whichever occurs first

(2)OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE

(3)This parameter is sampled and is not 100% tested

1996 Microchip Technology Inc.

Preliminary

DS21113B-page 3