Microchip Technology Inc 24C32AT-E-SM, 24C32AT-E-P, 24C32AT-SN, 24C32AT-SM, 24C32AT-P Datasheet

24C32A

32K 5.0V I2C Serial EEPROM

FEATURES

•Voltage operating range: 4.5V to 5.5V

-Maximum write current 3 mA at 5.5V

-Standby current 1 A typical at 5.0V

•2-wire serial interface bus, I2C compatible

•100 kHz and 400 kHz compatibility

•Self-timed ERASE and WRITE cycles

•Power on/off data protection circuitry

•Hardware write protect

•1,000,000 Erase/Write cycles guaranteed

•32-byte page or byte write modes available

•Schmitt trigger filtered inputs for noise suppression

•Output slope control to eliminate ground bounce

•2 ms typical write cycle time, byte or page

•Up to eight devices may be connected to the same bus for up to 256K bits total memory

•Electrostatic discharge protection > 4000V

•Data retention > 200 years

•8-pin PDIP and SOIC packages

•Temperature ranges

-	Commercial (C):	0˚C	to	70˚C
-	Industrial (I):	-40˚C	to	+85˚C
-	Automotive (E):	-40˚C	to	+125˚C

DESCRIPTION

The Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24C32A also has a page-write capability of up to 32 bytes of data. The 24C32A is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24C32A devices on the same bus, for up to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/low-voltage, nonvolatile code and data applications. The 24C32A is available in the standard 8-pin plastic DIP and both 150 mil and 200 mil SOIC packaging.

I2C is a trademark of Philips Corporation.

PACKAGE TYPES

PDIP

A0	1	24C32A	8	Vcc
A2	3		6	SCL
A1	2		7	WP
Vss	4		5	SDA

SOIC

A0			1	24C32A	8			Vcc
			3		6
A1			2		7			WP
A2			4		5			SCL
Vss								SDA

BLOCK DIAGRAM

		A0..WPA2	WP		HV GENERATOR
	I/O	MEMORY			EEPROM
	CONTROL	CONTROL		XDEC
					ARRAY
	LOGIC	LOGIC
					PAGE LATCHES
	I/O
	SCL
					YDEC
	SDA
	VCC
	VSS				SENSE AMP
					R/W CONTROL

1996 Microchip Technology Inc.

Preliminary

DS21163B-page 1

24C32A

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. VSS ...............	-0.6V to VCC +1.0V
Storage temperature .....................................		-65˚C to +150˚C
Ambient temp. with power applied ................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins ..................................................		≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name	Function
A0..A2	User Configurable Chip Selects
VSS	Ground
SDA	Serial Address/Data I/O
SCL	Serial Clock
WP	Write Protect Input
VCC	+4.5V to 5.5V Power Supply

TABLE 1-2:	DC CHARACTERISTICS
Vcc = +4.5V to 5.5V		0°C to	+70°C
Commercial (C): Tamb =
Industrial (I):	Tamb =	-40°C to	+85°C
Automotive(E):	Tamb = -40°C to +125°C
Parameter			Symbol	Min	Typ	Max	Units	Conditions
A0, A1, A2, SCL , SDA and WP
pins:
High level input voltage			VIH	.7 VCC		—	V
Low level input voltage			VIL	—		.3 Vcc	V
Hysteresis of Schmitt Trigger			VHYS	.05		—	V	(Note)
inputs				VCC
Low level output voltage			VOL	—		.40	V	I OL = 3.0 mA
Input leakage current			ILI	-10		10	A VIN = .1V to VCC
Output leakage current			ILO	-10		10	A VOUT = .1V to VCC
Pin capacitance			CIN, COUT	—		10	pF	V CC = 5.0V (Note)
(all inputs/outputs)								Tamb = 25˚C, Fc = 1 MHz
Operating current			ICC Write	—		3	mA	V CC = 5.5V, SCL = 400 kHz
			ICC Read	—		0.5	mA	V CC = 5.5V, SCL = 400 kHz
Standby current			ICCS	—	1	5	A SCL = SDA = VCC = 5.5V

Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1:	BUS TIMING START/STOP
		VHYS
SCL	THD:STA
		TSU:STO
TSU:STA
SDA
	START	STOP

DS21163B-page 2

Preliminary

1996 Microchip Technology Inc.

							24C32A
TABLE 1-3:	AC CHARACTERISTICS
Parameter		Symbol	Vcc = 4.5-5.5		Units		Remarks
			Min	Max
Clock frequency		FCLK	—	100	kHz
Clock high time		THIGH	4000	—	ns
Clock low time		TLOW	4700	—	ns
SDA and SCL rise time		TR	—	1000	ns		(Note 1)
SDA and SCL fall time		TF	—	300	ns		(Note 1)
START condition hold time		THD:STA	4000	—	ns		After this period the first clock
							pulse is generated
START condition setup time		TSU:STA	4700	—	ns		Only relevant for repeated
							START condition
Data input hold time		THD:DAT	0	—	ns
Data input setup time		TSU:DAT	250	—	ns
STOP condition setup time		TSU:STO	4000	—	ns
Output valid from clock		TAA	—	3500	ns		(Note 2)
Bus free time		TBUF	4700	—	ns		Time the bus must be free before
							a new transmission can start
Output fall time from VIH min to		TOF	—	250	ns		(Note 1), C B ≤ 100 pF
VIL max
Input filter spike suppression		TSP	—	50	ns		(Note 3)
(SDA and SCL pins)
Write cycle time		TWR	—	5	ms
Endurance		—	1M	—	cycles	25 °C, Vcc = 5.0V, Block Mode
							(Note 4)

Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

		TF		TR
		THIGH
		TLOW
SCL
	TSU:STA	THD:DAT	TSU:DAT	TSU:STO
SDA		THD:STA
	TSP
IN
	TAA	THD:STA		TBUF
		TAA
SDA
OUT

1996 Microchip Technology Inc.

Preliminary

DS21163B-page 3

24C32A

2.0FUNCTIONAL DESCRIPTION

The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C32A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.

3.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24C32A does not generate any acknowledge bits if an internal programming cycle is in progress.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24C32A) will leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)	(B)	(D)	(D)	(C)	(A)
SCL
SDA
	START	ADDRESS OR	DATA	STOP
CONDITION		ACKNOWLEDGE	ALLOWED	CONDITION
		VALID	TO CHANGE

DS21163B-page 4

Preliminary

1996 Microchip Technology Inc.