Microchip Technology Inc 24LCS52T-I-ST, 24LCS52T-I-SN, 24LCS52T-I-P, 24LCS52T-ST, 24LCS52T-SN Datasheet

24LCS52

2K 2.5V I2C Serial EEPROM with Software Write Protect

FEATURES

•Single supply with operation down to 2.5V

•Low power CMOS technology

-1 mA active current typical

-10 A standby current typical at 5.5V

-5 A standby current typical at 3.0V

•Organized as a single block of 256 bytes (256 x 8)

•Software write protection for lower 128 bytes

•Hardware write protection for entire array

•2-wire serial interface bus, I2C compatible

•100kHz (2.5V) and 400kHz (5V) compatibility

•Self-timed write cycle (including auto-erase)

•Page-write buffer for up to 16 bytes

•3.5 ms typical write cycle time for page-write

•10,000,000 erase/write cycles guaranteed

•ESD protection >4,000V

•Data retention > 200 years

•8-pin DIP, SOIC or TSSOP packages

•Available for extended temperature ranges

-	Commercial (C):	0°C	to	+70°C
-	Industrial (I):	-40°C	to	+85°C

DESCRIPTION

The Microchip Technology Inc. 24LCS52 is a 2K bit Electrically Erasable PROM capable of operation across a broad voltage range (2.5V to 5.5V). This device has a software write protect feature for the lower half of the array, as well as an external pin that can be used to write protect the entire array. The software write protect feature is enabled by sending the device a special command, and once this feature has been enabled, it cannot be reversed. In addition to the software protect feature, there is a WP pin that can be used to write protect the entire array, regardless of whether the software write protect register has been written or not. This allows the system designer to protect none, half or all of the array, depending on the application. The device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with typical standby and active currents of only 5 A and 1 mA respectively. The device has a page-write capability for up to 16 bytes of data. The device is available in the standard 8-pin DIP, 8-pin SOIC and TSSOP packages.

PACKAGE TYPES

PDIP/SOIC

A0

1

8

Vcc

				24LCS52	7		WP
A1			2
					6		SCL
A2			3
					5		SDA
Vss			4

TSSOP

A0					1	24LCS52	8					Vcc
A1					2		7					WP
A2					3		6					SCL
Vss					4		5					SDA

BLOCK DIAGRAM

	A0 A1 A2	WP	HV Generator
	I/O	Memory	Software write
	Control	Control	protected area
	Logic		(00h-7Fh)
		Logic
			XDEC
			Standard
	SDA SCL		Array
	Vcc		Write Protect
	Vss		Circuitry
			YDEC
			SENSE AMP
			R/W CONTROL

I2C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

DS21166B-page 1

24LCS52

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. VSS ...............	-0.6V to VCC +1.0V
Storage temperature .....................................		-65˚C to +150˚C
Ambient temp. with power applied ................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins.............................................		≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name	Function
VSS	Ground
SDA	Serial Address/Data I/O
SCL	Serial Clock
VCC	+2.5V to 5.5V Power Supply
A0, A1, A2	Chip Selects
WP	Hardware Write Protect

TABLE 1-2:	DC CHARACTERISTICS
		VCC = +2.5V to +5.5V		Commercial (C): Tamb = 0˚C to +70˚C
				Industrial		(I): Tamb = -40˚C to +85˚C
	Parameter	Symbol	Min.	Max.	Units		Conditions
SCL and SDA pins:		VIH	.7 VCC		V
High level input voltage
Low level input voltage		VIL		.3 VCC	V
Hysteresis of Schmitt trigger inputs		VHYS	.05 VCC	—	V		(Note)
Low level output voltage		VOL		.40	V		IOL = 3.0 mA, VCC = 2.5V
Input leakage current
All I/O pins		ILI	-10	10	A		VIN = 0.1V to 5.5V, WP = Vss
WP pin		ILI	-10	50	A		WP = VCC
Output leakage current		ILO	-10	10	A		VOUT = 0.1V to 5.5V
Pin capacitance (all inputs/outputs)		CIN,	—	10	pF		V CC = 5.0V (Note)
		COUT					Tamb = 25˚C, FCLK = 1 MHz
Operating current		ICC Write	—	3	mA		V CC = 5.5V, SCL = 400 kHz
		ICC Read	—	1	mA		V CC = 5.5V, SCL = 400 kHz
Standby current		ICCS	—	30	A		VCC = 3.0V, SDA = SCL = VCC
				100	A		VCC = 5.5V, SDA = SCL = VCC

Note:	This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:		BUS TIMING START/STOP
		VHYS
SCL
		THD:STA
	TSU:STA		TSU:STO
SDA
		START	STOP

DS21166B-page 2

Preliminary

1996 Microchip Technology Inc.

								24LCS52
TABLE 1-3:	AC CHARACTERISTICS
			Vcc = 2.5-5.5V		Vcc = 4.5 - 5.5V
Parameter		Symbol	STD MODE		FAST MODE		Units	Remarks
			Min.	Max.	Min.	Max.
Clock frequency		FCLK	—	100	—	400	kHz
Clock high time		THIGH	4000	—	600	—	ns
Clock low time		TLOW	4700	—	1300	—	ns
SDA and SCL rise time		TR	—	1000	—	300	ns	(Note 1)
SDA and SCL fall time		TF	—	300	—	300	ns	(Note 1)
START condition hold time		THD:STA	4000	—	600	—	ns	After this period the first
								clock pulse is generated
START condition setup time		TSU:STA	4700	—	600	—	ns	Only relevant for repeated
								START condition
Data input hold time		THD:DAT	0	—	0	—	ns	(Note 2)
Data input setup time		TSU:DAT	250	—	100	—	ns
STOP condition setup time		TSU:STO	4000	—	600	—	ns
Output valid from clock		TAA	—	3500	—	900	ns	(Note 2)
Bus free time		TBUF	4700	—	1300	—	ns	Time the bus must be free
								before a new transmission
								can start
Output fall time from VIH		TOF	—	250	20 +0.1	250	ns	(Note 1), CB ≤ 100 pF
minimum to VIL maximum					CB
Input filter spike suppression		TSP	—	50	—	50	ns	(Note 3)
(SDA and SCL pins)
Write cycle time		TWR	—	10	—	10	ms	Byte or Page mode
Endurance			10M	—	10M	—	cycles	25 °C, VCC = 5.0V, Block
								Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

		TF		TR
		THIGH
		TLOW
SCL
	TSU:STA	THD:DAT	TSU:DAT	TSU:STO
SDA		THD:STA
	TSP
IN
	TAA	THD:STA	TAA	TBUF
SDA
OUT

1996 Microchip Technology Inc.

Preliminary

DS21166B-page 3

24LCS52

2.0FUNCTIONAL DESCRIPTION

The 24LCS52 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LCS52 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.

3.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24LCS52 does not generate any acknowledge bits if an internal programming cycle is in progress.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

3.6Device Addressing

A control byte is the first byte received following the START condition from the master device. The first part of the control byte consists of a 4-bit control code which is set to 1010 for normal read and write operations and 0110 for writing to the write protect register. The control byte is followed by three chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24LCS52 devices on the same bus and are used to determine which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. The device will not acknowledge if you attempt a read command with the control code set to 0110.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

SCL	(A)	(B)	(C)	(D)	(C)	(A)
SDA
		START	ADDRESS OR	DATA	STOP
		CONDITION	ACKNOWLEDGE	ALLOWED	CONDITION
			VALID	TO CHANGE

DS21166B-page 4

Preliminary

1996 Microchip Technology Inc.