Microchip Technology Inc 93LC66XT-I-SN, 93LC66XT-SN, 93LC66X-I-SN, 93LC66X-SN, 93LC66T-I-SM Datasheet

M 93LC46/56/66

1K/2K/4K 2.0V Microwire® Serial EEPROM

FEATURES

•Single supply with programming operation down to 2.0V (Commercial only)

•Low power CMOS technology

-1 mA active current typical

-5 A standby current (typical) at 3.0V

•ORG pin selectable memory configuration

-128 x 8 or 64 x 16-bit organization (93LC46)

-256 x 8 or 128 x 16-bit organization(93LC56)

-512 x 8 or 256 x 16-bit organization(93LC66)

•Self-timed ERASE and WRITE cycles (including auto-erase)

•Automatic ERAL before WRAL

•Power on/off data protection circuitry

•Industry standard 3-wire serial I/O

•Device status signal during ERASE/WRITE cycles

•Sequential READ function

•10,000,000 ERASE/WRITE cycles guaranteed on 93LC56 and 93LC66

•1,000,000 E/W cycles guaranteed on 93LC46

•Data retention > 200 years

•8-pin PDIP/SOIC and 14-pin SOIC package (SOIC in JEDEC and EIAJ standards)

•Temperature ranges supported

-	Commercial (C):	0°C	to	+70°C
-	Industrial (I):	-40°C	to	+85°C

BLOCK DIAGRAM

	VCC	VSS
	MEMORY		ADDRESS
	ARRAY		DECODER
			ADDRESS
			COUNTER
	DATA REGISTER		OUTPUT	DO
			BUFFER
DI
	MODE
	DECODE
CS	LOGIC
CLK	CLOCK
	GENERATOR
DESCRIPTION

The Microchip Technology Inc. 93LC46/56/66 are 1K, 2K, and 4K low-voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits, depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low-power, nonvolatile memory applications. The 93LC46/56/66 is available in standard 8-pin DIP and 8/ 14-pin surface mount SOIC packages. The 93LC46X/ 56X/66X are only offered in an “SN” package.

PACKAGE TYPES

DIP

CS	1	93LC46 93LC56 93LC66	8		VCC	CS
DI	3		6		ORG
						DI
CLK	2		7		NU	CLK
DO	4		5		VSS
						DO

SOIC

1	93LC66	93LC56	93LC46
3
2
4

8	VCC	NU									1
7	NU	VCC									2
6	ORG	CS									3
5											4
	VSS	CLK

										SOIC
								NC	1			14	NC
SOIC								CS	2			13	Vcc
										93LC66	93LC56
93LC66X	93LC56X	93LC46X						CLK	3			12	NU
			8				ORG	NC	4			11	NC
			7				VSS	DI	5			10	ORG
			6				DO	DO	6			9	VSS
			5				DI	NC	7			8	NC

1997 Microchip Technology Inc.

DS11168L-page 1

93LC46/56/66

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

Vcc ...................................................................................		7.0V
All inputs and outputs w.r.t. VSS ...............	-0.6V to Vcc +1.0V
Storage temperature .....................................		-65˚C to +150˚C
Ambient temp. with power applied.................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins................................................		4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

PIN function Table

Name	Function
CS	Chip Select
CLK	Serial Data Clock
DI	Serial Data Input
DO	Serial Data Output
VSS	Ground
ORG	Memory Configuration
NU	Not Utilized
NC	No Connect
VCC	Power Supply

TABLE 1-1	DC AND AC ELECTRICAL CHARACTERISTICS
		Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0˚C to +70˚C
		Industrial (I):		Vcc = +2.5V to +6.0V (I): Tamb = -40˚C to +85˚C
Parameter		Symbol		Min.	Max.	Units	Conditions
High level input voltage		VIH1		2.0	Vcc +1	V	VCC ≥ 2.7V
		VIH2		0.7 Vcc	Vcc +1	V	VCC < 2.7V
Low level input voltage		VIL1		-0.3	0.8	V	VCC ≥ 2.7V
		VIL2		-0.3	0.2 Vcc	V	VCC < 2.7V
Low level output voltage		VOL1		—	0.4	V	IOL = 2.1 mA; Vcc = 4.5V
		VOL2		—	0.2	V	IOL =100 A; Vcc = Vcc Min.
High level output voltage		VOH1		2.4	—	V	IOH = -400 A; Vcc = 4.5V
		VOH2		Vcc-0.2	—	V	IOH = -100 A; Vcc = Vcc Min.
Input leakage current		ILI		-10	10	A	VIN = 0.1V to Vcc
Output leakage current		ILO		-10	10	A	VOUT = 0.1V to Vcc
Pin capacitance		CIN, COUT		—	7	pF	VIN/VOUT = 0 V (Notes 1 & 3)
(all inputs/outputs)							Tamb = +25°C, FCLK = 1 MHz
		ICC read		—	1	mA	FCLK = 2 MHz; Vcc = 6.0V
Operating current					500	A	FCLK = 1 MHz; Vcc = 3.0V
		ICC write		—	3	mA	FCLK = 2 MHz; Vcc = 6.0V (Note 3)
Standby current		ICCS		—	100	A	CLK = CS = 0V; Vcc = 6.0V
					30	A	CLK = CS = 0V; Vcc = 3.0V
Clock frequency		FCLK		—	2	MHz	Vcc ≥ 4.5V
					1	MHz	Vcc < 4.5V
Clock high time		TCKH		250	—	ns
Clock low time		TCKL		250	—	ns
Chip select setup time		TCSS		50	—	ns	Relative to CLK
Chip select hold time		TCSH		0	—	ns	Relative to CLK
Chip select low time		TCSL		250	—	ns
Data input setup time		TDIS		100	—	ns	Relative to CLK
Data input hold time		TDIH		100	—	ns	Relative to CLK
Data output delay time		TPD		—	400	ns	CL = 100 pF
Data output disable time		TCZ		—	100	ns	CL = 100 pF (Note 3)
Status valid time		TSV		—	500	ns	CL = 100 pF
		TWC		—	10	ms	ERASE/WRITE mode (Note 2)
Program cycle time		TEC		—	15	ms	ERAL mode
		TWL		—	30	ms	WRAL mode
Endurance							25°C, Vcc = 5.0V, Block Mode (Note 4)
93LC46		—		1M	—	cycles
93LC56/66		—		10M	—

Note 1: This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz.

2:Typical program cycle time is 4 ms per word.

3:This parameter is periodically sampled and not 100% tested.

4:This application is not tested but guaranteed by characterization. For endurance estimates in a specifi application, please consult the Total Endurance Model which can be obtained on our BBS or website.

DS11168L-page 2

1997 Microchip Technology Inc.

93LC46/56/66

2.0PIN DESCRIPTION

2.1Chip Select (CS)

A high level selects the device. A low level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed.

CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status.

2.2Serial Clock (CLK)

The Serial Clock (CLK) is used to synchronize the communication between a master device and the 93LCXX. Opcodes, addresses, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing the opcode, address, and data.

CLK is a “Don't Care”if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition).

CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.

After detecting a START condition, the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (Table 2-1 to Table 2-6). CLK and DI then become don't care inputs waiting for a new START condition to be detected.

Note: CS must go low between consecutive instructions.

2.3Data In (DI)

Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.

2.4Data Out (DO)

Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK).

This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated.

The status signal is not available on DO, if CS is held low or high during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, a pull-up resistor on DO is required to read the READY signal.

2.5Organization (ORG)

When ORG is tied to VSS, the (x8) memory organization is selected. When ORG is connected to Vcc or floated, the (x16) memory organization is selected. ORG can only be floated for clock speeds of 1 MHz or less for the (X16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to Vcc or VSS.

1997 Microchip Technology Inc.

DS11168L-page 3

93LC46/56/66

TABLE 2-1	INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
Instruction	SB	Opcode				Address						Data In	Data Out										Req. CLK Cycles
ERASE	1	11	A6 A5 A4 A3 A2 A1 A0									—	(RDY/BSY)										10
ERAL	1	00		1	0	X	X	X	X	X		—											10
													(RDY/BSY)
EWDS	1	00		0	0	X	X	X	X	X		—	HIGH-Z										10
EWEN	1	00		1 1 X X X X X								—	HIGH-Z										10
READ	1	10	A6 A5 A4 A3 A2 A1 A0									—	D7 - D0										18
WRITE	1	01	A6 A5 A4 A3 A2 A1 A0									D7 - D0											18
													(RDY/BSY)
WRAL	1	00		0 1 X X X X X								D7 - D0											18
													(RDY/BSY)
TABLE 2-2	INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
Instruction	SB	Opcode				Address						Data In	Data Out										Req. CLK Cycles
ERASE	1	11		A5 A4 A3 A2 A1 A0								—	(RDY/BSY)										9
ERAL	1	00		1	0	X	X	X	X			—											9
													(RDY/BSY)
EWDS	1	00		0	0	X	X	X	X			—	HIGH-Z										9
EWEN	1	00		1 1 X X X X								—	HIGH-Z										9
READ	1	10		A5 A4 A3 A2 A1 A0								—	D15 - D0										25
WRITE	1	01		A5 A4 A3 A2 A1 A0								D15 - D0											25
													(RDY/BSY)
WRAL	1	00		0 1 X X X X								D15 - D0											25
													(RDY/BSY)
TABLE 2-3	INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
Instruction	SB	Opcode				Address						Data In	Data Out										Req. CLK Cycles
ERASE	1	11	X A7 A6 A5 A4 A3 A2 A1 A0									—	(RDY/BSY)										12
ERAL	1	00	1	0	X	X	X	X	X	X	X	—											12
													(RDY/BSY)
EWDS	1	00	0	0	X	X	X	X	X	X	X	—	HIGH-Z										12
EWEN	1	00	1	1	X	X	X	X	X	X	X	—	HIGH-Z										12
READ	1	10	X A7 A6 A5 A4 A3 A2 A1 A0									—	D7 - D0										20
WRITE	1	01	X A7 A6 A5 A4 A3 A2 A1 A0									D7 - D0											20
													(RDY/BSY)
WRAL	1	00	0 1 X X X X X X X									D7 - D0											20
													(RDY/BSY)
TABLE 2-4	INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
Instruction	SB	Opcode				Address						Data In	Data Out										Req. CLK Cycles
ERASE	1	11	X A6 A5 A4 A3 A2 A1 A0									—	(RDY/BSY)										11
ERAL	1	00	1	0	X	X	X	X	X	X		—											11
													(RDY/BSY)
EWDS	1	00	0	0	X	X	X	X	X	X		—	HIGH-Z										11
EWEN	1	00	1	1	X	X	X	X	X	X		—	HIGH-Z										11
READ	1	10	X A6 A5 A4 A3 A2 A1 A0									—	D15 - D0										27
WRITE	1	01	X A6 A5 A4 A3 A2 A1 A0									D15 - D0											27
													(RDY/BSY)
WRAL	1	00	0 1 X X X X X X									D15 - D0											27
													(RDY/BSY)
TABLE 2-5	INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
Instruction	SB	Opcode				Address						Data In	Data Out										Req. CLK Cycles
ERASE	1	11	A8 A7 A6 A5 A4 A3 A2 A1 A0									—	(RDY/BSY)										12
ERAL	1	00	1	0	X	X	X	X	X	X	X	—											12
													(RDY/BSY)
EWDS	1	00	0	0	X	X	X	X	X	X	X	—	HIGH-Z										12
EWEN	1	00	1 1 X X X X						X	X	X	—	HIGH-Z										12
READ	1	10	A8 A7 A6 A5 A4 A3 A2 A1 A0									—	D7 - D0										20
WRITE	1	01	A8 A7 A6 A5 A4 A3 A2 A1 A0									D7 - D0											20
													(RDY/BSY)
WRAL	1	00	0 1 X X X X X X X									D7 - D0											20
													(RDY/BSY)
TABLE 2-6	INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
Instruction	SB	Opcode			Address							Data In	Data Out										Req. CLK Cycles
READ	1	10	A7 A6 A5 A4 A3 A2 A1 A0									—	D15 - D0										27
EWEN	1	00	1 1 X X X X						X	X		—	High-Z										11
ERASE	1	11	A7 A6 A5 A4 A3 A2 A1 A0									—											11
													(RDY/BSY)
ERAL	1	00	1 0 X X X X						X	X		—											11
													(RDY/BSY)
WRITE	1	01	A7 A6 A5 A4 A3 A2 A1 A0									D15 - D0											27
													(RDY/BSY)
WRAL	1	00	0	1	X	X	X	X	X	X		D15 - D0											27
													(RDY/BSY)
EWDS	1	00	0	0	X	X	X	X	X	X		—	High-Z										11
DS11168L-page 4													1997 Microchip Technology Inc.