Microchip Technology Inc PIC16C73B-04-SO, PIC16C73B-04-SP, PIC16C73B-04-SS, PIC16C73B-04I-SO, PIC16C73B-04I-SP Datasheet

MPIC16C63A/65B/73B/74B

28/40-Pin 8-Bit CMOS Microcontrollers

Device	Pins	A/D	PSP
PIC16C63A	28	NO	NO
PIC16C73B	28	YES	NO
PIC16C65B	40	NO	YES
PIC16C74B	40	YES	YES

Microcontroller Core Features:

•High-performance RISC CPU

•Only 35 single word instructions to learn

•All single cycle instructions except for program branches which are two cycle

•Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

•4K x 14 words of Program Memory,

192 x 8 bytes of Data Memory (RAM)

•Interrupt capability (up to 12 internal/external interrupt sources)

•Eight level deep hardware stack

•Direct, indirect, and relative addressing modes

•Power-on Reset (POR)

•Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

•Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

•Programmable code-protection

•Power saving SLEEP mode

•Selectable oscillator options

•Low-power, high-speed CMOS EPROM technology

•Fully static design

•In-Circuit Serial Programming™ (ICSP)

•Wide operating voltage range: 2.5V to 5.5V

•High Sink/Source Current 25/25 mA

•Commercial, Industrial and Extended temperature ranges

•Low-power consumption:

-< 2 mA @ 5V, 4 MHz

-22.5 A typical @ 3V, 32 kHz

-< 1 A typical standby current

Pin Diagram

PDIP, Windowed CERDIP

MCLR/VPP	1		40	RB7
RA0/AN0	2		39	RB6
RA1/AN1	3		38	RB5
RA2/AN2	4		37	RB4
RA3/AN3/VREF	5		36	RB3
RA4/T0CKI	6	PIC16C74B	35	RB2
OSC2/CLKOUT	14		27	RD4/PSP4
RA5/SS/AN4	7		34	RB1
RE0/RD/AN5	8		33	RB0/INT
RE1/WR/AN6	9		32	VDD
RE2/CS/AN7	10		31	VSS
VDD	11		30	RD7/PSP7
VSS	12		29	RD6/PSP6
OSC1/CLKIN	13		28	RD5/PSP5
RC0/T1OSO/T1CKI	15		26	RC7/RX/DT
RC1/T1OSI/CCP2	16		25	RC6/TX/CK
RC2/CCP1	17		24	RC5/SDO
RC3/SCK/SCL	18		23	RC4/SDI/SDA
RD0/PSP0	19		22	RD3/PSP3
RD1/PSP1	20		21	RD2/PSP2

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Two Capture, Compare, PWM modules

• Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit

• 8-bit multi-channel Analog-to-Digital converter

• Synchronous Serial Port (SSP) with Enhanced SPI and I2C

• Universal Synchronous Asynchronous Receiver

Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls

• Brown-out detection circuitry for Brown-out Reset (BOR)

1998 Microchip Technology Inc.

DS30605A-page 1

PIC16C63A/65B/73B/74B

Pin Diagrams

SDIP, SOIC, SSOP, Windowed CERDIP

MCLR/VPP	• 1	28	RB7
RA0/AN0	2	27	RB6
RA1/AN1	3	26	RB5
RA2/AN2	4	25	RB4
RA3/AN3/VREF	5	24	RB3
RA4/T0CKI	6	23	RB2
RA5/SS/AN4	7	22	RB1
VSS	8	21	RB0/INT
OSC1/CLKIN	9	20	VDD
OSC2/CLKOUT	10	19	VSS
RC0/T1OSO/T1CKI	11	18	RC7/RX/DT
RC1/T1OSI/CCP2	12	17	RC6/TX/CK
RC2/CCP1	13	16	RC5/SDO
RC3/SCK/SCL	14	15	RC4/SDI/SDA

PIC16C73B

PDIP, Windowed CERDIP

MCLR/VPP	1	40	RB7
RA0	2	39	RB6
RA1	3	38	RB5
RA2	4	37	RB4
RA3	5	36	RB3
RA4/T0CKI	6	35	RB2
RA5/SS	7	34	RB1
RE0/RD	8	33	RB0/INT
RE1/WR	9	32	VDD
RE2/CS	10	31	VSS
VDD	11	30	RD7/PSP7
VSS	12	29	RD6/PSP6
OSC1/CLKIN	13	28	RD5/PSP5
OSC2/CLKOUT	14	27	RD4/PSP4
RC0/T1OSO/T1CKI	15	26	RC7/RX/DT
RC1/T1OSI/CCP2	16	25	RC6/TX/CK
RC2/CCP1	17	24	RC5/SDO
RC3/SCK/SCL	18	23	RC4/SDI/SDA
RD0/PSP0	19	22	RD3/PSP3
RD1/PSP1	20	21	RD2/PSP2

PIC16C65B

PLCC					MCLR/VPP
	RA3	RA2	RA1	RA0		NC	RB7	RB6	RB5	RB4	NC
	6 5 4 3				2 1		44 43		42 41		40
RA4/T0CKI	7										39	RB3
RA5/SS	8										38	RB2
RE0/RD	9										37	RB1
RE1/WR	10										36	RB0/INT
RE2/CS	11										35	VDD
VDD	12	PIC16C65B									34	VSS
VSS	13										33	RD7/PSP7
OSC1/CLKIN	14										32	RD6/PSP6
OSC2/CLKOUT	15										31	RD5/PSP5
RC0/T1OSO/T1CKI	16										30	RD4/PSP4
NC	17										29	RC7/RX/DT
	18	19	20	21	22	23	24	25	26	27	28
	RC1/T1OSI/CCP2	RC2/CCP1	RC3/SCK/SCL	RD0/PSP0	RD1/PSP1	RD2/PSP2	RD3/PSP3	RC4/SDI/SDA	RC5/SDO	RC6/TX/CK	NC

SDIP, SOIC, SSOP, Windowed CERDIP

MCLR/VPP	• 1	28	RB7
RA0	2	27	RB6
RA1	3	26	RB5
RA2	4	25	RB4
RA3	5	24	RB3
RA4/T0CKI	6	23	RB2
RA5/SS	7	22	RB1
VSS	8	21	RB0/INT
OSC1/CLKIN	9	20	VDD
OSC2/CLKOUT	10	19	VSS
RC0/T1OSO/T1CKI	11	18	RC7/RX/DT
RC1/T1OSI/CCP2	12	17	RC6/TX/CK
RC2/CCP1	13	16	RC5/SDO
RC3/SCK/SCL	14	15	RC4/SDI/SDA

PIC16C63A

MQFP		RC6/TX/CK	RC5/SDO	RC4/SDI/SDA	RD3/PSP3	RD2/PSP2	RD1/PSP1	RD0/PSP0	RC3/SCK/SCL	RC2/CCP1	RC1/T1OSI/CCP2	NC
TQFP
RC7/RX/DT	1	44	43	42	41	40	39	38 37		36	35	34	33	NC
RD4/PSP4	2												32	RC0/T1OSO/T1CKI
RD5/PSP5	3												31	OSC2/CLKOUT
RD6/PSP6	4												30	OSC1/CLKIN
RD7/PSP7	5		PIC16C65B										29	VSS
VSS	6												28	VDD
VDD	7												27	RE2/CS
RB0/INT	8												26	RE1/WR
RB1	9												25	RE0/RD
RB2	10												24	RA5/SS
RB3	11												23	RA4/T0CKI
		12	13	14	15	16	17	18	19	20	21	22
		NC NC		RB4	RB5	RB6	RB7	MCLR/VPP	RA0	RA1	RA2	RA3

DS30605A-page 2

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

Pin Diagrams (Cont.’d)

	REF	RA2/AN2	RA1/AN1	RA0/AN0	MCLR/VPP	NC	RB7	RB6	RB5	RB4	NC
PLCC	RA3/AN3/V
	6 5 4 3				2 1		44 43		42 41		40
RA4/T0CKI	7										39	RB3
RA5/SS/AN4	8										38	RB2
RE0/RD/AN5	9										37	RB1
RE1/WR/AN6	10										36	RB0/INT
RE2/CS/AN7	11										35	VDD
VDD	12	PIC16C74B									34	VSS
VSS	13										33	RD7/PSP7
OSC1/CLKIN	14										32	RD6/PSP6
OSC2/CLKOUT	15										31	RD5/PSP5
RC0/T1OSO/T1CKI	16										30	RD4/PSP4
NC	17										29	RC7/RX/DT
	18	19	20	21	22	23	24	25	26	27	28
	RC1/T1OSI/CCP2	RC2/CCP1	RC3/SCK/SCL	RD0/PSP0	RD1/PSP1	RD2/PSP2	RD3/PSP3	RC4/SDI/SDA	RC5/SDO	RC6/TX/CK	NC

MQFP TQFP

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7 VSS VDD

RB0/INT

RB1

RB2

RB3

	RC6/TX/CK
1	44
2
3
4

5

6

7

8

9

10

11 12

NC

RC5/SDO	RC4/SDI/SDA	RD3/PSP3	RD2/PSP2	RD1/PSP1	RD0/PSP0 RC3/SCK/SCL	RC2/CCP1	RC1/T1OSI/CCP2	NC
43	42	41	40	39	38 37	36	35	34

PIC16C74B

13	14	15	16	17	18	19	20	21	22
NC	RB4	RB5	RB6	RB7	MCLR/VPP	RA0/AN0	RA1/AN1	RA2/AN2	RA3/AN3/VREF

33	NC
32	RC0/T1OSO/T1CKI
31	OSC2/CLKOUT
30	OSC1/CLKIN
29	VSS
28	VDD
27	RE2/CS/AN7
26	RE1/WR/AN6
25	RE0/RD/AN5
24	RA5/SS/AN4
23	RA4/T0CKI

Key Features
PICmicro Mid-Range Reference Manual	PIC16C63A	PIC16C65B		PIC16C73B	PIC16C74B
(DS33023)
Operating Frequency	DC - 20 MHz	DC - 20 MHz		DC - 20 MHz	DC - 20 MHz
Resets (and Delays)	POR, BOR	POR, BOR		POR, BOR	POR, BOR
	(PWRT, OST)	(PWRT, OST)		(PWRT, OST)	(PWRT, OST)
Program Memory (14-bit words)	4K	4K		4K	4K
Data Memory (bytes)	192	192		192	192
Interrupts	10	11		11	12
I/O Ports	Ports A,B,C	Ports A,B,C,D,E		Ports A,B,C	Ports A,B,C,D,E
Timers	3	3		3	3
Capture/Compare/PWM modules	2	2		2	2
Serial Communications	SSP, USART	SSP, USART		SSP, USART	SSP, USART
Parallel Communications	—	PSP		—	PSP
8-bit Analog-to-Digital Module	—	—	5	input channels	8 input channels
Instruction Set	35 Instructions	35 Instructions		35 Instructions	35 Instructions

1998 Microchip Technology Inc.

DS30605A-page 3

PIC16C63A/65B/73B/74B
Table of Contents
1.0	Device Overview ..........................................................................................................................................................................	5
2.0	Memory Organization .................................................................................................................................................................	11
3.0	I/O Ports .....................................................................................................................................................................................	25
4.0	Timer0 Module ...........................................................................................................................................................................	37
5.0	Timer1 Module ...........................................................................................................................................................................	39
6.0	Timer2 Module ...........................................................................................................................................................................	43
7.0	Capture/Compare/PWM (CCP) Module(s) .................................................................................................................................	45
8.0	Synchronous Serial Port (SSP) Module .....................................................................................................................................	51
9.0	Universal Synchronous Asynchronous Receiver Transmitter (USART) ....................................................................................	61
10.0	Analog - to - Digital Converter (A/D) Module ..................................................................................................................................	75
11.0	Special Features of the CPU ......................................................................................................................................................	81
12.0	Instruction Set Summary ............................................................................................................................................................	95
13.0	Development Support ................................................................................................................................................................	97
14.0	Electrical Characteristics ..........................................................................................................................................................	101
15.0	DC and AC Characteristics Graphs and Tables .......................................................................................................................	123
16.0	Packaging Information .............................................................................................................................................................	125
Appendix A: Revision History ...........................................................................................................................................................		137
Appendix B: Device Differences .......................................................................................................................................................		137
Appendix C: Conversion Considerations ..........................................................................................................................................		137
Appendix D: Migration from Baseline to Midrange Devices..............................................................................................................		138
Appendix E: Bit/Register Cross-Reference List ................................................................................................................................		139
Index	..................................................................................................................................................................................................	141
On-Line .................................................................................................................................................................................Support		147
Reader ..............................................................................................................................................................................Response		148
PIC16C63A/65B/73B/74B ..................................................................................................................Product Identification System		149

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our worldwide web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number, found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•Microchip’s worldwide web site at http://www.microchip.com

•Your local Microchip sales office (see last page)

•The Microchip Corporate Literature Center; U.S. FAX: [phone]

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please:

•Fill out and mail in the reader response form in the back of this data sheet, or

•E-mail us at [e-mail].

We appreciate your assistance in making this a better document.

DS30605A-page 4

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

1.0DEVICE OVERVIEW

This document contains device-specific information. Additional information may be found in the PICmicro Mid-Range Reference Manual (DS33023) which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

There are four devices (PIC16C63A, PIC16C65B, PIC16C73B, PIC16C74B) covered by this data sheet. These devices come in 28and 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented. The PIC16C6X devices do not have the A/D module implemented.

The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2 respectively.

FIGURE 1-1: PIC16C63A/PIC16C73B BLOCK DIAGRAM

13		Data Bus	8
	Program Counter
EPROM
4K x 14		RAM
Program	8 Level Stack
		192 x 8
Memory	(13-bit)
		File
		Registers

Program

14

RAM Addr(1)

9

Bus

Addr MUX

Instruction reg

Direct Addr 7

8

Indirect

Addr

FSR reg

		8	STATUS reg
			3
		Power-up	MUX
		Timer
	Instruction	Oscillator
	Decode &	Start-up Timer	ALU
	Control	Power-on
			8
		Reset
	Timing	Watchdog	W reg
	Generation	Timer
	OSC1/CLKIN	Brown-out
	OSC2/CLKOUT	Reset

PORTA

RA0/AN0(2)

RA1/AN1(2)

RA2/AN2(2)

RA3/AN3/VREF(2)

RA4/T0CKI

RA5/SS/AN4(2)

PORTB

RB0/INT

RB7:RB1

PORTC

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK RC7/RX/DT

MCLR VDD, VSS

Timer0

Timer1

Timer2

A/D(2)

CCP1		CCP2		Synchronous		USART
				Serial Port

Note 1: Higher order bits are from the STATUS register.

2: The A/D module is not available on the PIC16C63A.

1998 Microchip Technology Inc.

DS30605A-page 5

PIC16C63A/65B/73B/74B

FIGURE 1-2: PIC16C65B/PIC16C74B BLOCK DIAGRAM

13		Data Bus	8
	Program Counter
EPROM
4K x 14		RAM
Program	8 Level Stack
		192 x 8
	(13-bit)
Memory
		File
		Registers

Program

14

RAM Addr (1)

9

Bus

Addr MUX

Instruction reg

Direct Addr 7

8

Indirect

Addr

FSR reg

		8		STATUS reg
		Power-up	3	MUX
		Timer
	Instruction	Oscillator
	Decode &	Start-up Timer		ALU
	Control	Power-on
			8
		Reset
	Timing	Watchdog		W reg
	Generation	Timer
OSC1/CLKIN		Brown-out
OSC2/CLKOUT		Reset
				Parallel Slave Port
		MCLR VDD, VSS
Timer0	Timer1	Timer2		A/D(2)

PORTA

RA0/AN0(2)

RA1/AN1(2)

RA2/AN2(2)

RA3/AN3/VREF(2)

RA4/T0CKI

RA5/SS/AN4(2)

PORTB

RB0/INT

RB7:RB1

PORTC

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO RC6/TX/CK

RC7/RX/DT

PORTD

RD7/PSP7:RD0/PSP0

PORTE

RE0/RD/AN5(2)

RE1/WR/AN6(2)

RE2/CS/AN7(2)

CCP1			CCP2		Synchronous			USART
					Serial Port
Note 1:	Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C65B.

DS30605A-page 6

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

TABLE 1-1:			PIC16C63A/PIC16C73B PINOUT DESCRIPTION
Pin Name				DIP	SOIC	I/O/P	Buffer		Description
				Pin#	Pin#	Type	Type
OSC1/CLKIN				9	9	I	ST/CMOS(3)		Oscillator crystal input/external clock source input.
	OSC2/CLKOUT			10	10	O	—		Oscillator crystal output. Connects to crystal or resonator in
									crystal oscillator mode. In RC mode, the OSC2 pin outputs
									CLKOUT which has 1/4 the frequency of OSC1, and denotes
									the instruction cycle rate.
				1	1	I/P	ST		Master clear (reset) input or programming voltage input. This
	MCLR/VPP
									pin is an active low reset to the device.
									PORTA is a bi-directional I/O port.
RA0/AN0(4)				2	2	I/O	TTL		RA0 can also be analog input0
RA1/AN1(4)				3	3	I/O	TTL		RA1 can also be analog input1
RA2/AN2(4)				4	4	I/O	TTL		RA2 can also be analog input2
RA3/AN3/VREF(4)				5	5	I/O	TTL		RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI				6	6	I/O	ST		RA4 can also be the clock input to the Timer0 module.
									Output is open drain type.
RA5/SS/AN4(4)				7	7	I/O	TTL		RA5 can also be analog input4 or the slave select for the
									synchronous serial port.
									PORTB is a bi-directional I/O port. PORTB can be software
									programmed for internal weak pull-up on all inputs.
RB0/INT				21	21	I/O	TTL/ST(1)		RB0 can also be the external interrupt pin.
RB1				22	22	I/O	TTL
RB2				23	23	I/O	TTL
RB3				24	24	I/O	TTL
RB4				25	25	I/O	TTL		Interrupt on change pin.
RB5				26	26	I/O	TTL		Interrupt on change pin.
RB6				27	27	I/O	TTL/ST(2)		Interrupt on change pin. Serial programming clock.
RB7				28	28	I/O	TTL/ST(2)		Interrupt on change pin. Serial programming data.
									PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI				11	11	I/O	ST		RC0 can also be the Timer1 oscillator output or Timer1
									clock input.
RC1/T1OSI/CCP2				12	12	I/O	ST		RC1 can also be the Timer1 oscillator input or Capture2
									input/Compare2 output/PWM2 output.
RC2/CCP1				13	13	I/O	ST		RC2 can also be the Capture1 input/Compare1 output/
									PWM1 output.
RC3/SCK/SCL				14	14	I/O	ST		RC3 can also be the synchronous serial clock input/output
									for both SPI and I2C modes.
RC4/SDI/SDA				15	15	I/O	ST		RC4 can also be the SPI Data In (SPI mode) or
									data I/O (I2C mode).
RC5/SDO				16	16	I/O	ST		RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK				17	17	I/O	ST		RC6 can also be the USART Asynchronous Transmit or
									Synchronous Clock.
RC7/RX/DT				18	18	I/O	ST		RC7 can also be the USART Asynchronous Receive or
									Synchronous Data.
VSS				8, 19	8, 19	P	—		Ground reference for logic and I/O pins.
VDD				20	20	P	—		Positive supply for logic and I/O pins.

Legend:	I = input	O = output	I/O = input/output	P = power
		— = Not used	TTL = TTL input	ST = Schmitt Trigger input
Note 1:	This buffer is a Schmitt Trigger input when configured as the external interrupt.

2:This buffer is a Schmitt Trigger input when used in serial programming mode.

3:This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

4:The A/D module is not available on the PIC16C63A.

1998 Microchip Technology Inc.

DS30605A-page 7

PIC16C63A/65B/73B/74B

TABLE 1-2:			PIC16C65B/PIC16C74B PINOUT DESCRIPTION
Pin Name				DIP	PLCC	QFP	I/O/P	Buffer		Description
				Pin#	Pin#	Pin#	Type	Type
OSC1/CLKIN				13	14	30	I	ST/CMOS(4)		Oscillator crystal input/external clock source input.
OSC2/CLKOUT				14	15	31	O	—		Oscillator crystal output. Connects to crystal or resonator in
										crystal oscillator mode. In RC mode, OSC2 pin outputs
										CLKOUT which has 1/4 the frequency of OSC1, and
										denotes the instruction cycle rate.
				1	2	18	I/P	ST		Master clear (reset) input or programming voltage input.
	MCLR/VPP
										This pin is an active low reset to the device.
										PORTA is a bi-directional I/O port.
RA0/AN0(5)				2	3	19	I/O	TTL		RA0 can also be analog input0
RA1/AN1(5)				3	4	20	I/O	TTL		RA1 can also be analog input1
RA2/AN2(5)				4	5	21	I/O	TTL		RA2 can also be analog input2
RA3/AN3/VREF(5)				5	6	22	I/O	TTL		RA3 can also be analog input3 or analog reference
										voltage
RA4/T0CKI				6	7	23	I/O	ST		RA4 can also be the clock input to the Timer0 timer/
										counter. Output is open drain type.
RA5/SS/AN4(5)				7	8	24	I/O	TTL		RA5 can also be analog input4 or the slave select for
										the synchronous serial port.
										PORTB is a bi-directional I/O port. PORTB can be software
										programmed for internal weak pull-up on all inputs.
RB0/INT				33	36	8	I/O	TTL/ST(1)		RB0 can also be the external interrupt pin.
RB1				34	37	9	I/O	TTL
RB2				35	38	10	I/O	TTL
RB3				36	39	11	I/O	TTL
RB4				37	41	14	I/O	TTL		Interrupt on change pin.
RB5				38	42	15	I/O	TTL		Interrupt on change pin.
RB6				39	43	16	I/O	TTL/ST(2)		Interrupt on change pin. Serial programming clock.
RB7				40	44	17	I/O	TTL/ST(2)		Interrupt on change pin. Serial programming data.

Legend:	I = input	O = output	I/O = input/output	P = power
		— = Not used	TTL = TTL input	ST = Schmitt Trigger input
Note 1:	This buffer is a Schmitt Trigger input when configured as an external interrupt.

2:This buffer is a Schmitt Trigger input when used in serial programming mode.

3:This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus).

4:This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

5:The A/D module is not available on the PIC16C65B.

DS30605A-page 8

1998 Microchip Technology Inc.

								PIC16C63A/65B/73B/74B
TABLE 1-2:		PIC16C65B/PIC16C74B PINOUT DESCRIPTION (Cont.’d)
Pin Name			DIP	PLCC	QFP		I/O/P	Buffer		Description
			Pin#	Pin#	Pin#		Type	Type
										PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI			15	16	32		I/O	ST		RC0 can also be the Timer1 oscillator output or a
										Timer1 clock input.
RC1/T1OSI/CCP2			16	18	35		I/O	ST		RC1 can also be the Timer1 oscillator input or
										Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1			17	19	36		I/O	ST		RC2 can also be the Capture1 input/Compare1 output/
										PWM1 output.
RC3/SCK/SCL			18	20	37		I/O	ST		RC3 can also be the synchronous serial clock input/
										output for both SPI and I2C modes.
RC4/SDI/SDA			23	25	42		I/O	ST		RC4 can also be the SPI Data In (SPI mode) or
										data I/O (I2C mode).
RC5/SDO			24	26	43		I/O	ST		RC5 can also be the SPI Data Out
										(SPI mode).
RC6/TX/CK			25	27	44		I/O	ST		RC6 can also be the USART Asynchronous Transmit or
										Synchronous Clock.
RC7/RX/DT			26	29	1		I/O	ST		RC7 can also be the USART Asynchronous Receive or
										Synchronous Data.
										PORTD is a bi-directional I/O port or parallel slave port
										when interfacing to a microprocessor bus.
RD0/PSP0			19	21	38		I/O	ST/TTL(3)
RD1/PSP1			20	22	39		I/O	ST/TTL(3)
RD2/PSP2			21	23	40		I/O	ST/TTL(3)
RD3/PSP3			22	24	41		I/O	ST/TTL(3)
RD4/PSP4			27	30	2		I/O	ST/TTL(3)
RD5/PSP5			28	31	3		I/O	ST/TTL(3)
RD6/PSP6			29	32	4		I/O	ST/TTL(3)
RD7/PSP7			30	33	5		I/O	ST/TTL(3)
										PORTE is a bi-directional I/O port.
RE0/RD/AN5(5)			8	9	25		I/O	ST/TTL(3)		RE0 can also be read control for the parallel slave port,
										or analog input5.
RE1/WR/AN6(5)			9	10	26		I/O	ST/TTL(3)		RE1 can also be write control for the parallel slave port,
										or analog input6.
RE2/CS/AN7(5)			10	11	27		I/O	ST/TTL(3)		RE2 can also be select control for the parallel slave
										port, or analog input7.
VSS			12,31	13,34	6,29		P	—		Ground reference for logic and I/O pins.
VDD			11,32	12,35	7,28		P	—		Positive supply for logic and I/O pins.
NC			—	1,17,28,	12,13,			—		These pins are not internally connected. These pins should
				40	33,34					be left unconnected.
Legend:	I = input		O = output				I/O = input/output			P = power
			— = Not used			TTL = TTL input				ST = Schmitt Trigger input
Note 1:	This buffer is a Schmitt Trigger input when configured as an external interrupt.

2:This buffer is a Schmitt Trigger input when used in serial programming mode.

3:This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus).

4:This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

5:The A/D module is not available on the PIC16C65B.

1998 Microchip Technology Inc.

DS30605A-page 9

PIC16C63A/65B/73B/74B

NOTES:

DS30605A-page 10

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

2.0MEMORY ORGANIZATION

There are two memory blocks in each of these PICmicro microcontrollers. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur.

Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual (DS33023).

2.1Program Memory Organization

The PIC16C63A/65B/73B/74B microcontrollers have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Each device has 4K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK

				PC<12:0>
		CALL, RETURN		13
		RETFIE, RETLW
			Stack Level 1
			Stack Level 8
			Reset Vector		0000h
	User Memory		Interrupt Vector		0004h
		Space	On-chip Program		0005h
			Memory (Page 0)		07FFh
			On-chip Program		0800h
			Memory (Page 1)
					0FFFh
					1000h
					1FFFh

2.2Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.

RP1(1)

RP0

(STATUS<6:5>)

=00 → Bank0

=01 → Bank1

=10 → Bank2 (not implemented)

=11 → Bank3 (not implemented)

Note 1: Maintain this bit clear to ensure upward compatibility with future products.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access.

2.2.1GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 2.5).

1998 Microchip Technology Inc.

DS30605A-page 11

PIC16C63A/65B/73B/74B

FIGURE 2-2: REGISTER FILE MAP

File			File
Address		Address
00h	INDF(1)	INDF(1)	80h
01h	TMR0	OPTION_REG	81h
02h	PCL	PCL	82h
03h	STATUS	STATUS	83h
04h	FSR	FSR	84h
05h	PORTA	TRISA	85h
06h	PORTB	TRISB	86h
07h	PORTC	TRISC	87h
08h	PORTD(2)	TRISD(2)	88h
09h	PORTE(2)	TRISE(2)	89h
0Ah	PCLATH	PCLATH	8Ah
0Bh	INTCON	INTCON	8Bh
0Ch	PIR1	PIE1	8Ch
0Dh	PIR2	PIE2	8Dh
0Eh			8Eh
	TMR1L	PCON
0Fh			8Fh
	TMR1H
10h	T1CON		90h
11h	TMR2		91h
12h	T2CON	PR2	92h
13h			93h
	SSPBUF	SSPADD
14h	SSPCON	SSPSTAT	94h
15h			95h
	CCPR1L
16h	CCPR1H		96h
17h	CCP1CON		97h
18h	RCSTA	TXSTA	98h
19h	TXREG	SPBRG	99h
1Ah			9Ah
	RCREG
1Bh	CCPR2L		9Bh
1Ch	CCPR2H		9Ch
1Dh	CCP2CON		9Dh
1Eh	ADRES(3)		9Eh
1Fh	ADCON0(3)	ADCON1(3)	9Fh
20h	General	General	A0h
	Purpose	Purpose
	Register	Register
7Fh			FFh
	Bank 0	Bank 1

Unimplemented data memory locations, read

as ’0’.

Note 1: Not a physical register.

2:These registers are not implemented on the PIC16C63A/73B, read as '0'.

3:These registers are not implemented on the PIC16C63A/65B, read as '0'.

2.2.2SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1.

The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.

DS30605A-page 12

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

TABLE 2-1

SPECIAL FUNCTION REGISTER SUMMARY

Value on

Value on all

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

(5)

Bank 0

00h

INDF(1)

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000

0000

0000

0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

PCL(1)

Program Counter's (PC) Least Significant Byte

0000

0000

0000

0000

03h

STATUS(1)

IRP(6)

RP1(6)

RP0

Z

DC

C

rr01 1xxx

rr0q quuu

TO

PD

04h

FSR(1)

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA(7)

—

—

PORTA Data Latch when written: PORTA pins when read

--0x 0000

--0u 0000

06h

PORTB(8)

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC(8)

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

PORTD(3,8)

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx

uuuu uuuu

09h

PORTE(3,8)

—

—

—

—

—

RE2

RE1

RE0

---- -xxx

---- -uuu

0Ah

PCLATH(1,2)

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

INTCON(1)

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000

000x

0000

000u

0Ch

PIR1

PSPIF(3)

ADIF(4)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000

0000

0000 0000

0Dh

PIR2

—

—

—

–

—

—

—

CCP2IF

---- ---0

---- ---0

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

—

—

T1CKPS1

T1CKPS0

T1OSCEN

TMR1CS

TMR1ON

--00 0000

--uu uuuu

T1SYNC

11h

TMR2

Timer2 module’s register

0000

0000

0000 0000

12h

T2CON

—

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000

0000

0000 0000

15h

CCPR1L

Capture/Compare/PWM Register1 (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

—

—

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

--00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000

-00x

0000 -00x

19h

TXREG

USART Transmit Data Register

0000

0000

0000 0000

1Ah

RCREG

USART Receive Data Register

0000

0000

0000 0000

1Bh

CCPR2L

Capture/Compare/PWM Register2 (LSB)

xxxx xxxx

uuuu uuuu

1Ch

CCPR2H

Capture/Compare/PWM Register2 (MSB)

xxxx xxxx

uuuu uuuu

1Dh

CCP2CON

—

—

CCP2X

CCP2Y

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

--00 0000

1Eh

ADRES(4)

A/D Result Register

xxxx xxxx

uuuu uuuu

1Fh

ADCON0(4)

ADCS1

ADCS0

CHS2

CHS1

CHS0

—

ADON

0000

00-0

0000 00-0

GO/DONE

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',

Shaded locations are unimplemented, read as '0'.

Note 1:

These registers can be addressed from either bank.

2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter.

3:PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.

4:A/D not implemented on the PIC16C63A/65B, maintain as ’0’.

5:Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

6:The IRP and RP1 bits are reserved. Always maintain these bits clear.

7:On any device reset, these pins are configured as inputs.

8:This is the value that will be in the port output latch.

1998 Microchip Technology Inc.

DS30605A-page 13

PIC16C63A/65B/73B/74B

TABLE 2-1

SPECIAL FUNCTION REGISTER SUMMARY

(Cont.’d)

Value on

Value on all

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

(5)

Bank 1

80h

INDF(1)

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000

0000

81h

OPTION_REG

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111

1111

RBPU

82h

PCL(1)

Program Counter's (PC) Least Significant Byte

0000 0000

0000

0000

83h

STATUS(1)

IRP(6)

RP1(6)

RP0

Z

DC

C

rr01 1xxx

rr0q quuu

TO

PD

84h

FSR(1)

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

—

—

PORTA Data Direction Register

--11 1111

--11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111

1111

1111

87h

TRISC

PORTC Data Direction Register

1111 1111

1111

1111

88h

TRISD(3)

PORTD Data Direction Register

1111 1111

1111

1111

89h

TRISE(3)

IBF

OBF

IBOV

PSPMODE

—

PORTE Data Direction Bits

0000 -111

0000

-111

8Ah

PCLATH(1,2)

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

INTCON(1)

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000

000u

8Ch

PIE1

PSPIE(3)

ADIE(4)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

0000

0000

8Dh

PIE2

—

—

—

—

—

—

—

CCP2IE

---- ---0

---- ---0

8Eh

PCON

—

—

—

—

—

—

---- --qq

---- --uu

POR

BOR

8Fh

—

Unimplemented

—

—

90h

—

Unimplemented

—

—

91h

—

Unimplemented

—

—

92h

PR2

Timer2 Period Register

1111 1111

1111

1111

93h

SSPADD

Synchronous Serial Port (I2C mode) Address Register

0000 0000

0000

0000

94h

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000

0000

0000

95h

—

Unimplemented

—

—

96h

—

Unimplemented

—

—

97h

—

Unimplemented

—

—

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

0000

-010

99h

SPBRG

Baud Rate Generator Register

0000 0000

0000

0000

9Ah

—

Unimplemented

—

—

9Bh

—

Unimplemented

—

—

9Ch

—

Unimplemented

—

—

9Dh

—

Unimplemented

—

—

9Eh

—

Unimplemented

—

—

9Fh

ADCON1(4)

—

—

—

—

—

PCFG2

PCFG1

PCFG0

---- -000

---- -000

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',

Shaded locations are unimplemented, read as '0'.

Note 1:

These registers can be addressed from either bank.

2:The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter.

3:PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.

4:A/D not implemented on the PIC16C63A/65B, maintain as ’0’.

5:Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

6:The IRP and RP1 bits are reserved. Always maintain these bits clear.

7:On any device reset, these pins are configured as inputs.

8:This is the value that will be in the port output latch.

DS30605A-page 14

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

2.2.2.1STATUS REGISTER

The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary."

Note 1: These devices do not use bits IRP and RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products.

Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0

R/W-0

R/W-0

R-1

R-1

R/W-x

R/W-x

R/W-x

IRP

RP1

RP0

TO

PD

Z

DC

C

R = Readable bit

bit7

bit0

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear 0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear

bit	6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
		11 = Bank 3 (180h - 1FFh) - not implemented, maintain clear
		10 = Bank 2 (100h - 17Fh) - not implemented, maintain clear
		01 = Bank 1 (80h - FFh)
		00 = Bank 0 (00h - 7Fh)
		Each bank is 128 bytes
bit	4:			: Time-out bit
		TO
		1	= After power-up, CLRWDT instruction, or SLEEP instruction
		0	= A WDT time-out occurred
bit	3:				: Power-down bit
		PD
		1	= After power-up or by the CLRWDT instruction
		0	= By execution of the SLEEP instruction
bit	2:	Z: Zero bit
		1	= The result of an arithmetic or logic operation is zero
		0	= The result of an arithmetic or logic operation is not zero
bit
	1: DC: Digit carry/borrow								bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
		1	= A carry-out from the 4th low order bit of the result occurred
		0	= No carry-out from the 4th low order bit of the result
bit	0:							bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
		C: Carry/borrow
		1	= A carry-out from the most significant bit of the result occurred
		0	= No carry-out from the most significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

1998 Microchip Technology Inc.

DS30605A-page 15

PIC16C63A/65B/73B/74B

2.2.2.2OPTION_REG REGISTER

The OPTION_REG register is a readable and writable

Note:

To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

register which contains various control bits to configure

the Watchdog Timer.

the TMR0 prescaler/WDT postscaler (single assign-

able register known also as the prescaler), the External

INT Interrupt, TMR0, and the weak pull-ups on PORTB.

FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

R

= Readable bit

RBPU

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

: PORTB Pull-up Enable bit

RBPU

1

= PORTB pull-ups are disabled

0

= PORTB pull-ups are enabled by individual port latch values

bit

6:

INTEDG: Interrupt Edge Select bit

1

= Interrupt on rising edge of RB0/INT pin

0

= Interrupt on falling edge of RB0/INT pin

bit

5:

T0CS: TMR0 Clock Source Select bit

1

= Transition on RA4/T0CKI pin

0

= Internal instruction cycle clock (CLKOUT)

bit

4:

T0SE: TMR0 Source Edge Select bit

1

= Increment on high-to-low transition on RA4/T0CKI pin

0

= Increment on low-to-high transition on RA4/T0CKI pin

bit

3:

PSA: Prescaler Assignment bit

1

= Prescaler is assigned to the WDT

0

= Prescaler is assigned to the Timer0 module

bit

2-0:

PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

1 : 2

1 : 1

001

1 : 4

1 : 2

010

1 : 8

1 : 4

011

1 : 16

1 : 8

100

1 : 32

1 : 16

101

1 : 64

1 : 32

110

1 : 128

1 : 64

111

1 : 256

1 : 128

DS30605A-page 16

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

2.2.2.3INTCON REGISTER

The INTCON Register is a readable and writable regis-

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

ter which contains various enable and flag bits for the

its corresponding enable bit or the global

TMR0 register overflow, RB Port change and External

enable bit, GIE (INTCON<7>). User soft-

RB0/INT pin interrupts.

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

GIE: Global Interrupt Enable bit

1

= Enables all un-masked interrupts

0

= Disables all interrupts

bit

6:

PEIE: Peripheral Interrupt Enable bit

1

= Enables all un-masked peripheral interrupts

0

= Disables all peripheral interrupts

bit

5:

T0IE: TMR0 Overflow Interrupt Enable bit

1

= Enables the TMR0 interrupt

0

= Disables the TMR0 interrupt

bit

4:

IINTE: RB0/INT External Interrupt Enable bit

1

= Enables the RB0/INT external interrupt

0

= Disables the RB0/INT external interrupt

bit

3:

RBIE: RB Port Change Interrupt Enable bit

1

= Enables the RB port change interrupt

0

= Disables the RB port change interrupt

bit

2:

T0IF: TMR0 Overflow Interrupt Flag bit

1

= TMR0 register has overflowed (must be cleared in software)

0

= TMR0 register did not overflow

bit

1:

INTF: RB0/INT External Interrupt Flag bit

1

= The RB0/INT external interrupt occurred (must be cleared in software)

0

= The RB0/INT external interrupt did not occur

bit

0:

RBIF: RB Port Change Interrupt Flag bit

1

= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0

= None of the RB7:RB4 pins have changed state

1998 Microchip Technology Inc.

DS30605A-page 17

PIC16C63A/65B/73B/74B

2.2.2.4PIE1 REGISTER

This register contains the individual enable bits for the

Note:

Bit PEIE (INTCON<6>) must be set to

peripheral interrupts.

enable any peripheral interrupt.

FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

PSPIE(1)

ADIE(2)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

1

= Enables the PSP read/write interrupt

0

= Disables the PSP read/write interrupt

bit

6:

ADIE(2): A/D Converter Interrupt Enable bit

1

= Enables the A/D interrupt

0

= Disables the A/D interrupt

bit

5:

RCIE: USART Receive Interrupt Enable bit

1

= Enables the USART receive interrupt

0

= Disables the USART receive interrupt

bit

4:

TXIE: USART Transmit Interrupt Enable bit

1

= Enables the USART transmit interrupt

0

= Disables the USART transmit interrupt

bit

3:

SSPIE: Synchronous Serial Port Interrupt Enable bit

1

= Enables the SSP interrupt

0

= Disables the SSP interrupt

bit

2:

CCP1IE: CCP1 Interrupt Enable bit

1

= Enables the CCP1 interrupt

0

= Disables the CCP1 interrupt

bit

1:

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1

= Enables the TMR2 to PR2 match interrupt

0

= Disables the TMR2 to PR2 match interrupt

bit

0:

TMR1IE: TMR1 Overflow Interrupt Enable bit

1

= Enables the TMR1 overflow interrupt

0

= Disables the TMR1 overflow interrupt

Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these devices. Always maintain this bit clear.

2:PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.

DS30605A-page 18

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

2.2.2.5

PIR1 REGISTER

Note:

Interrupt flag bits get set when an interrupt

This register contains the individual flag bits for the

condition occurs regardless of the state of

peripheral interrupts.

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0

R/W-0

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

PSPIF(1)

ADIF(2)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit

1

= A read or a write operation has taken place (must be cleared in software)

0

= No read or write has occurred

bit

6:

ADIF(2): A/D Converter Interrupt Flag bit

1

= An A/D conversion completed (must be cleared in software)

0

= The A/D conversion is not complete

bit

5:

RCIF: USART Receive Interrupt Flag bit

1

= The USART receive buffer is full (cleared by reading RCREG)

0

= The USART receive buffer is empty

bit

4:

TXIF: USART Transmit Interrupt Flag bit

1

= The USART transmit buffer is empty

(cleared by writing to TXREG)

0

= The USART transmit buffer is full

bit

3:

SSPIF: Synchronous Serial Port Interrupt Flag bit

1

= The transmission/reception is complete (must be cleared in software)

0

= Waiting to transmit/receive

bit

2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1

= A TMR1 register capture occurred (must be cleared in software)

0

= No TMR1 register capture occurred

Compare Mode

1

= A TMR1 register compare match occurred (must be cleared in software)

0

= No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit

1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1

= TMR2 to PR2 match occurred (must be cleared in software)

0

= No TMR2 to PR2 match occurred

bit

0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

1

= TMR1 register overflowed (must be cleared in software)

0

= TMR1 register did not overflow

Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these devices. Always maintain this bit clear.

2:PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.

1998 Microchip Technology Inc.

DS30605A-page 19

PIC16C63A/65B/73B/74B

2.2.2.6PIE2 REGISTER

This register contains the individual enable bit for the

CCP2 peripheral interrupt.

FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh)

U-0

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

—

—

—

CCP2IE

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-1:

Unimplemented: Read as '0'

bit 0:

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

DS30605A-page 20

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

2.2.2.7PIR2 REGISTER

This register contains the CCP2 interrupt flag bit.

.

Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh)

U-0

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

—

—

—

CCP2IF

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-1:

Unimplemented: Read as '0'

bit 0:

CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1

= A TMR1 register capture occurred (must be cleared in software)

0

= No TMR1 register capture occurred

Compare Mode

1

= A TMR1 register compare match occurred (must be cleared in software)

0

= No TMR1 register compare match occurred

PWM Mode

Unused

1998 Microchip Technology Inc.

DS30605A-page 21

PIC16C63A/65B/73B/74B

2.2.2.8

PCON REGISTER

Note:

If the BODEN configuration bit is set, BOR

The Power Control (PCON) register contains a flag bit

is ’1’ on Power-on Reset. If the BODEN

configuration bit is clear, BORis unknown

to allow

differentiation

between

a Power-on

Reset

on Power-on Reset.

(POR) to an external MCLR Reset or WDT Reset.

Those devices with brown-out detection circuitry con-

The

BOR

status bit is a "don't care" and is

tain an additional bit to differentiate a Brown-out Reset

not necessarily predictable if the brown-out

condition from a Power-on Reset condition.

circuit is disabled (the BODEN configura-

tion bit is clear).

must then be set by

BOR

the user and checked on subsequent

resets to see if

is clear, indicating a

it

brown-out has occurred.

FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-q

—

—

—

—

—

—

R

= Readable bit

POR

BOR

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-2:

Unimplemented: Read as '0'

bit

1:

: Power-on Reset Status bit

POR

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit

0:

: Brown-out Reset Status bit

BOR

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS30605A-page 22

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

2.3PCL and PCLATH

The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register.

2.3.1STACK

The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution.

Mid-Range devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not modified when the stack is PUSHed or POPed.

After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

2.4Program Memory Paging

The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper bit of the address is provided by PCLATH<3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bit is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack).

1998 Microchip Technology Inc.

DS30605A-page 23

PIC16C63A/65B/73B/74B

2.5Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.

EXAMPLE 2-1: INDIRECT ADDRESSING

•Register file 05 contains the value 10h

•Register file 06 contains the value 0Ah

•Load the value 05 into the FSR register

•A read of the INDF register will return the value of 10h

•Increment the value of the FSR register by one (FSR = 06)

•A read of the INDR register now will return the value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

FIGURE 2-11: DIRECT/INDIRECT ADDRESSING

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING

	movlw	0x20	;initialize pointer
	movwf	FSR	; to RAM
NEXT	clrf	INDF	;clear INDF register
	incf	FSR	;inc pointer
	btfss	FSR,4	;all done?
	goto	NEXT	;NO, clear next
CONTINUE
	:		;YES, continue

An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-11. However, IRP is not used in the PIC16C63A/65B/73B/74B.

			Direct Addressing																Indirect Addressing
RP1:RP0			6	from opcode						0				IRP			7				FSR register					0
(2)														(2)
bank select			location select											bank select									location select
										00	01	10	11
								00h			80h	100h	180h

not used Data (3) (3)

Memory(1)

7Fh	FFh	17Fh	1FFh
Bank 0	Bank 1	Bank 2	Bank 3

Note 1: For register file map detail see Figure 2-2.

2:Maintain RP1 and IRP as clear for upward compatibility with future products.

3:Not implemented.

DS30605A-page 24

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

3.0I/O PORTS

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the PICmicro Mid-Range Reference Manual, (DS33023).

3.1PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin.

Note: On a Power-on Reset, these pins are configured as inputs and read as '0'.

Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read. This value is modified and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.

On PIC16C73B/74B devices, other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 3-1: INITIALIZING PORTA

BCF	STATUS, RP0	;
CLRF	PORTA	; Initialize	PORTA by
		; clearing output
		; data latches
BSF	STATUS, RP0	; Select Bank 1
MOVLW	0xCF	; Value used	to
		; initialize	data
		; direction
MOVWF	TRISA	; Set RA<3:0> as inputs
		; RA<5:4> as	outputs
		; TRISA<7:6>	are always
		; read as '0'.

FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS

Data
bus	Q
D
WR		VDD
Port	Q
CK		P
Data Latch
D	Q	N	I/O pin(1)
WR
TRIS	Q	VSS
CK
		Analog
TRIS Latch		input
		mode
		(73B/74B
		only)
	RD TRIS		TTL
			input
	Q	D	buffer
		EN
RD PORT

To A/D Converter (73B/74B only)

Note 1: I/O pins have protection diodes to VDD and VSS.

FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN

Data
bus	D	Q
WR
PORT	CK	Q		I/O pin(1)
			N
	Data Latch
	D	Q	VSS
WR
TRIS	CK	Q	Schmitt
			Trigger
	TRIS Latch		input
			buffer
	RD TRIS
		Q	D
			ENEN
RD PORT
TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

1998 Microchip Technology Inc.

DS30605A-page 25

PIC16C63A/65B/73B/74B

TABLE 3-1:			PORTA FUNCTIONS
Name				Bit#	Buffer	Function
RA0/AN0				bit0	TTL	Input/output or analog input(1)
RA1/AN1				bit1	TTL	Input/output or analog input(1)
RA2/AN2				bit2	TTL	Input/output or analog input(1)
RA3/AN3/VREF				bit3	TTL	Input/output or analog input(1) or VREF(1)
RA4/T0CKI				bit4	ST	Input/output or external clock input for Timer0
						Output is open drain type
						Input/output or slave select input for synchronous serial port or analog input(1)
RA5/SS/AN4				bit5	TTL

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: On PIC16C73B/74B devices only.

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

05h

PORTA

—

—

RA5

RA4

RA3

RA2

RA1

RA0

--0x

0000

--0u

0000

85h

TRISA

—

—

PORTA Data Direction Register

--11

1111

--11

1111

9Fh

ADCON1(1)

—

—

—

—

—

PCFG2

PCFG1

PCFG0

---- -000

---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: On PIC16C73B/74B devices only.

DS30605A-page 26

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

3.2PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin.

EXAMPLE 3-1: INITIALIZING PORTB

BCF	STATUS, RP0	;
CLRF	PORTB	; Initialize	PORTB by
		; clearing output
		; data latches
BSF	STATUS, RP0	; Select Bank 1
MOVLW	0xCF	; Value used	to
		; initialize	data
		; direction
MOVWF	TRISB	; Set RB<3:0> as inputs
		; RB<5:4> as	outputs
		; RB<7:6> as	inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF RB3:RB0 PINS

VDD

RBPU(2)

Data bus

WR Port

WR TRIS

RB0/INT

			P	weak
				pull-up
	Data Latch
	D	Q
	CK			I/O
				pin(1)
	TRIS Latch
	D	Q	TTL
	CK		Input
			Buffer
	RD TRIS
		Q	D
	RD Port		EN
	Schmitt Trigger		RD Port
	Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2:To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a)Any read or write of PORTB. This will end the mismatch condition.

b)Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared.

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 3-4: BLOCK DIAGRAM OF RB7:RB4 PINS

		VDD
RBPU(2)		P	weak
			pull-up
Data bus	Data Latch
	D	Q
WR Port			I/O
	CK		pin(1)

TRIS Latch

	D	Q
WR TRIS	CK		TTL
			Input
			Buffer	ST
				Buffer
	RD TRIS		Latch
		Q	D
Set RBIF	RD Port		EN	Q1
From other		Q	D
				RD Port
RB7:RB4 pins
			EN	Q3
RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2:To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

1998 Microchip Technology Inc.

DS30605A-page 27

PIC16C63A/65B/73B/74B

TABLE 3-3:	PORTB FUNCTIONS
Name	Bit#	Buffer	Function
RB0/INT	bit0	TTL/ST(1)	Input/output pin or external interrupt input. Internal software
			programmable weak pull-up.
RB1	bit1	TTL	Input/output pin. Internal software programmable weak pull-up.
RB2	bit2	TTL	Input/output pin. Internal software programmable weak pull-up.
RB3	bit3	TTL	Input/output pin. Internal software programmable weak pull-up.
RB4	bit4	TTL	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up.
RB5	bit5	TTL	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up.
RB6	bit6	TTL/ST(2)	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up. Serial programming clock.
RB7	bit7	TTL/ST(2)	Input/output pin (with interrupt on change). Internal software programmable
			weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

86h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

81h

OPTION_

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

RBPU

REG

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

DS30605A-page 28

1998 Microchip Technology Inc.

PIC16C63A/65B/73B/74B

3.3PORTC and the TRISC Register

PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin.

PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify- write instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

EXAMPLE 3-1: INITIALIZING PORTC

BCF	STATUS, RP0	; Select Bank 0
CLRF	PORTC	; Initialize	PORTC by
		; clearing output
		; data latches
BSF	STATUS, RP0	; Select Bank 1
MOVLW	0xCF	; Value used	to
		; initialize	data
		; direction
MOVWF	TRISC	; Set RC<3:0> as inputs
		; RC<5:4> as	outputs
		; RC<7:6> as	inputs

FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

	PORT/PERIPHERAL Select(2)
	Peripheral Data Out		0	VDD
	Data bus
		D	Q	P
	WR
			1
	PORT
		CK	Q
		Data Latch
	WR	D	Q	I/O
				pin(1)
	TRIS	CK	Q	N
		TRIS Latch		VSS
		RD TRIS		Schmitt
				Trigger
	Peripheral
	OE(3)		Q	D
		RD		EN
		PORT
	Peripheral input

Note 1: I/O pins have diode protection to VDD and VSS.

2:Port/Peripheral select signal selects between port data and peripheral output.

3:Peripheral OE (output enable) is only activated if peripheral select is active.

1998 Microchip Technology Inc.

DS30605A-page 29

PIC16C63A/65B/73B/74B

TABLE 3-5:	PORTC FUNCTIONS
Name		Bit#	Buffer Type	Function
RC0/T1OSO/T1CKI		bit0	ST	Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI		bit1	ST	Input/output port pin or Timer1 oscillator input
RC2/CCP1		bit2	ST	Input/output port pin or Capture1 input/Compare1 output/PWM1
				output
RC3/SCK/SCL		bit3	ST	RC3 can also be the synchronous serial clock for both SPI and I2C
				modes.
RC4/SDI/SDA		bit4	ST	RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO		bit5	ST	Input/output port pin or Synchronous Serial Port data output
RC6		bit6	ST	Input/output port pin
RC7		bit7	ST	Input/output port pin

Legend: ST = Schmitt Trigger input

TABLE 3-6:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

BOR

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

uuuu uuuu

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

Legend: x = unknown, u = unchanged.

DS30605A-page 30

1998 Microchip Technology Inc.