Microchip Technology Inc 24C02SC-WF08, 24C02SC-WF, 24C02SC-W08, 24C02SC-W, 24C02SC-S08 Datasheet

24C01SC/02SC

1K/2K 5.0V I2C Serial EEPROMs for Smart Cards

FEATURES

•ISO Standard 7816 pad locations

•Low power CMOS technology

-1 mA active current typical

-10 A standby current typical at 5.5V

•Organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8)

•Two-wire serial interface bus, I2C compatible

•100 kHz and 400 kHz compatibility

•Self-timed write cycle (including auto-erase)

•Page-write buffer for up to 8 bytes

•2 ms typical write cycle time for page-write

•ESD protection > 4 kV

•1,000,000 E/W cycles guaranteed

•Data retention > 200 years

•Available for extended temperature ranges

- Commercial (C):

0°C to +70°C

DESCRIPTION

The Microchip Technology Inc. 24C01SC and 24C02SC are 1K-bit and 2K-bit Electrically Erasable PROMs with bondpad positions optimized for smart card applications. The devices are organized as a single block of 128 x 8-bit or 256 x 8-bit memory with a two-wire serial interface. The 24C01SC and 24C02SC also have page-write capability for up to 8 bytes of data.

DIE LAYOUT

VSS

VCC

SDA

DC

SCL

BLOCK DIAGRAM

					HV GENERATOR
	I/O		MEMORY		EEPROM
	CONTROL		CONTROL
				XDEC	ARRAY
	LOGIC		LOGIC
					PAGE LATCHES
	SDA	SCL
					YDEC
	VCC				SENSE AMP
	VSS				R/W CONTROL

I2C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 1

24C01SC/02SC

1.0ELECTRICAL CHARACTERISTICS

Maximum Ratings*

VCC........................................................................	7.0V
All inputs and outputs w.r.t. VSS......	-0.6V to VCC +1.0V
Storage temperature ...........................	-65˚C to +150˚C
Ambient temp. with power applied.......	-65˚C to +125˚C
ESD protection on all pads.....................................	≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PAD FUNCTION TABLE

Name	Function
VSS	Ground
SDA	Serial Address/Data I/O
SCL	Serial Clock
VCC	+4.5V to 5.5V Power Supply
DC	Don’t connect

TABLE 1-2:	DC CHARACTERISTICS
		VCC = +4.5V to +5.5V		Commercial (C): Tamb = 0˚C to +70˚C
	Parameter	Symbol	Min.	Max.	Units	Conditions
SCL and SDA pads:
High level input voltage		VIH	.7 VCC	—	—
Low level input voltage		VIL	—	.3 V CC	V
Hysteresis of Schmidt trigger inputs		VHYS	.05 VCC	—	V	(Note)
Low level output voltage		VOL	—	.40	V	I OL = 3.0 mA, VCC = 4.5V
Input leakage current (SCL)		ILI	-10	10	A VIN = .1V to 5.5V
Output leakage current (SDA)		ILO	-10	10	A VOUT = .1V to 5.5V
Pin capacitance (all inputs/outputs)		CIN,	—	10	pF	V CC = 5.0V (Note 1)
		COUT				Tamb = 25˚C, FCLK = 1 MHz
Operating current		ICC Write	—	3	mA	V CC = 5.5V
		ICC Read	—	1	mA	Vcc = 5.5V, SCL = 400 KHz
Standby current		ICCS	—	100	A VCC = 5.5V, SDA = SCL = VCC

Note:	This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:		BUS TIMING START/STOP
		VHYS
SCL
		THD:STA
	TSU:STA		TSU:STO
SDA
		START	STOP

DS21170A-page 2

Preliminary

1996 Microchip Technology Inc.

24C01SC/02SC

TABLE 1-3:	AC CHARACTERISTICS
Parameter		Symbol	Min.	Max.	Units	Remarks
Clock frequency		FCLK	—	400	kHz
Clock high time		THIGH	600	—	ns
Clock low time		TLOW	1300	—	ns
SDA and SCL rise time		TR	—	300	ns	(Note 1)
SDA and SCL fall time		TF	—	300	ns	(Note 1)
START condition hold time		THD:STA	600	—	ns	After this period the first clock
						pulse is generated
START condition setup time		TSU:STA	600	—	ns	Only relevant for repeated
						START condition
Data input hold time		THD:DAT	0	—	ns	(Note 2)
Data input setup time		TSU:DAT	100	—	ns
STOP condition setup time		TSU:STO	600	—	ns
Output valid from clock		TAA	—	900	ns	(Note 2)
Bus free time		TBUF	1300	—	ns	Time the bus must be free
						before a new transmission can
						start
Output fall time from VIH		TOF	20 +0.1	250	ns	(Note 1), CB ≤ 100 pF
minimum to VIL maximum			CB
Input filter spike suppression		TSP	—	50	ns	(Note 3)
(SDA and SCL pins)
Write cycle time		TWR	—	10	ms	Byte or Page mode
Endurance		—	106	—	cycles	25 °C, Vcc = 5V, Block Mode
						(Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

		TF		TR
		THIGH
		TLOW
SCL
	TSU:STA	THD:DAT	TSU:DAT	TSU:STO
SDA		THD:STA
	TSP
IN
	TAA	THD:STA		TBUF
		TAA
SDA
OUT

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 3

24C01SC/02SC

2.0FUNCTIONAL DESCRIPTION

The 24C01SC/02SC supports a bi-directional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C01SC/02SC works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.

3.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24C01SC/02SC does not generate any acknowledge bits if an internal programming cycle is in progress.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)	(B)	(D)	(D)	(C)	(A)
SCL
SDA
	START	ADDRESS OR	DATA	STOP
	CONDITION	ACKNOWLEDGE	ALLOWED	CONDITION
		VALID	TO CHANGE

DS21170A-page 4

Preliminary

1996 Microchip Technology Inc.