Microchip Technology Inc 28C64AT-25-SO, 28C64AT-25-L, 28C64AT-20I-SO, 28C64AT-20I-L, 28C64AT-20-SO Datasheet

28C64A

64K (8K x 8) CMOS EEPROM

FEATURES

PACKAGE TYPES

RDY/BSY

• CMOS Technology for Low Power Dissipation

A12

2

27

WE

A7

A12

NU

Vcc

WE

NC

• Fast Read Access Time—150 ns

RDY/BSY

• 1

28

Vcc

-

30 mA Active

A7

3

26

NC

4

3

2

1

32

31

30

A6

4

25

A8

-

100 A Standby

A6

5

29

A8

A5

5

DIP/SOIC

24

A9

A5 6

PLCC

28

A9

•

Fast Byte Write Time—200 s or 1 ms

A4

6

23

A11

A4

7

27

A11

A3

7

22

OE

A3 8

26

NC

•

Data Retention >200 years

A2

8

21

A10

A2 9

25

OE

•

High Endurance - Minimum 100,000 Erase/Write

A1

9

20

CE

A1

10

24

A10

A0 11

23

CE

Cycles

A0

10

19

I/O7

NC 12

22

I/O7

I/O0

11

18

I/O6

•

Automatic Write Operation

I/O0

13

21

I/O6

I/O1

12

17

I/O5

14

15

16

17

18

19

20

-

Internal Control Timer

I/O2

13

16

I/O4

I/O1

I/O2

Vss

NU

I/O3

I/O4

I/O5

- Auto-Clear Before Write Operation

VSS

14

15

I/O3

- On-Chip Address and Data Latches

• Pin 1 indicator on PLCC on top of package

•

Data Polling

OE

1

28

A10

•

Ready/Busy

A11

2

27

CE

A9

3

26

I/07

•

Chip Clear Operation

A8

4

25

I/06

•

Enhanced Data Protection

NC

5

24

I/05

WE

6

TSOP

23

I/04

-

VCC Detector

Vcc

7

22

I/03

-

Pulse Filter

RDY/BSY

8

21

Vss

-

Write Inhibit

A12

9

20

I/02

A7

10

19

I/01

• Electronic Signature for Device Identification

A6

11

18

I/00

•

5-Volt-Only Operation

A5

12

17

A0

A4

13

16

A1

• Organized 8Kx8 JEDEC Standard Pinout

A3

14

15

A2

- 28-pin Dual-In-Line Package

OE

22

21

A10

-

32-pin PLCC Package

A11

23

20

CE

- 28-pin Thin Small Outline Package (TSOP)

A9

24

19

I/O7

A8

25

18

I/O6

8x20mm

NC

26

VSOP

17

I/O5

WE

27

16

I/O4

-

28-pin Very Small Outline Package (VSOP)

VCC

28

15

I/O3

8x13.4mm

RDY/BSY

1

14

VSS

A12

2

13

I/O2

• Available for Extended Temperature Ranges:

A7

3

12

I/O1

-

Commercial: 0˚C to +70˚C

A6

4

11

I/O0

A5

5

10

A0

A4

6

9

A1

DESCRIPTION

A3

7

8

A2

The Microchip Technology Inc. 28C64A is a CMOS 64K non-

BLOCK DIAGRAM

volatile electrically Erasable PROM.

The 28C64A

is

I/O0

I/O7

accessed like a static RAM for the read or write cycles without

the need of external components. During a “byte write”, the

VSS

Data Protection

address and data are latched internally, freeing the micropro-

VCC

Circuitry

cessor address and data bus for other operations. Following

CE

Chip Enable/

the initiation of write cycle, the device will go to a busy state

OE

Output Enable

Control Logic

and automatically clear and write the latched data using an

WE

Auto Erase/Write

Data

Input/Output

internal control timer. To determine when the write cycle is

Rdy/

Timing

Poll

Buffers

Busy

complete, the user has a choice of monitoring the Ready/

Program Voltage

Busy output or using Data polling. The Ready/Busy pin is an

Generation

A0

open drain output, which allows easy configuration in wired-

Y

Y Gating

or systems. Alternatively, Data polling allows the user to read

L

Decoder

the location last written to when the write operation is com-

a

t

plete. CMOS design and processing enables this part to be

c

h

X

16K bit

used in systems where reduced power consumption and reli-

e

s

Decoder

Cell Matrix

ability are required. A complete family of packages is offered

to provide the utmost flexibility in applications

A12

1996 Microchip Technology Inc.

DS11109H-page 1

28C64A

1.0ELECTRICAL CHARACTERISTICS

1.1MAXIMUM RATINGS*

VCC and input voltages w.r.t. VSS .......			-0.6V to + 6.25V
Voltage on		w.r.t. VSS	-0.6V to +13.5V
	OE
Voltage on A9 w.r.t. VSS ......................			-0.6V to +13.5V
Output Voltage w.r.t. VSS ................			-0.6V to VCC+0.6V
Storage temperature ..........................			-65˚C to +125˚C
Ambient temp. with power applied .......			-50˚C to +95˚C

*Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name											Function
A0 - A12									Address Inputs
									Chip Enable
			CE
									Output Enable
		OE
									Write Enable
	WE
I/O0 - I/O7									Data Inputs/Outputs
RDY/Busy									Ready/Busy
VCC									+5V Power Supply
VSS									Ground
		NC							No Connect; No Internal Connection
		NU							Not Used; No External Connection is
									Allowed

TABLE 1-2:	READ/WRITE OPERATION DC CHARACTERISTIC
					VCC = +5V ±10%
					Commercial (C): Tamb = 0˚C to +70˚C
					Industrial	(I): Tamb = -40˚C to +85˚C
Parameter		Status	Symbol	Min	Max	Units					Conditions
Input Voltages		Logic ‘1’	VIH	2.0	Vcc+1	V
		Logic ‘0’	VIL	-0.1	0.8	V
Input Leakage		—	I LI	-10	10	A			VIN = -0.1V to Vcc +1
Input Capacitance		—	C IN	—	10	pF	V IN = 0V; Tamb = 25˚C;
								f = 1 MHz (Note 2)
Output Voltages		Logic ‘1’	VOH	2.4		V		IOH = -400 A
		Logic ‘0’	VOL		0.45	V	IOL = 2.1 mA
Output Leakage		—	I LO	-10	10	A			VOUT = -0.1V to Vcc
								+0.1V
Output Capacitance		—	C OUT	—	12	pF	V IN = 0V; Tamb = 25˚C;
								f = 1 MHz (Note 2)
Power Supply Current, Active		TTL input	ICC	—	30	mA	f = 5 MHz (Note 1)
									VCC = 5.5V
Power Supply Current, Standby		TTL input	ICC(S)TTL	—	2	mA					= VIH (0˚C to +70˚C)
									CE
		TTL input	ICC(S)TTL		3	mA			CE		= VIH (-40˚C to +85˚C)
		CMOS input	ICC(S)CMOS		100	A				= VCC-0.3 to Vcc +1
								CE

Note 1: AC power supply current above 5MHz: 2mA/MHz. 2: Not 100% tested.

DS11109H-page 2

1996 Microchip Technology Inc.

28C64A

TABLE 1-3:

READ OPERATION AC CHARACTERISTICS

AC Testing Waveform:

VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V

Output Load:

1 TTL Load + 100 pF

Input Rise and Fall Times:

20 ns

Ambient Temperature:

Commercial (C):

Tamb

=

0˚C to +70˚C

Industrial

(I):

Tamb

=

-40˚C to +85˚C

Parameter

Symbol

28C64A-15

28C64A-20

28C64A-25

Units

Conditions

Min

Max

Min

Max

Min

Max

Address to Output Delay

tACC

—

150

—

200

—

250

ns

OE

=

= VIL

CE

to Output Delay

tCE

—

150

—

200

—

250

ns

OE

= VIL

CE

to Output Delay

tOE

—

70

—

80

—

100

ns

CE

= VIL

OE

or

High to Output Float

tOFF

0

50

0

55

0

70

ns (Note 1)

CE

OE

Output Hold from Address,

tOH

0

—

0

—

0

—

ns

(Note 1)

CE

or

OE,

whichever occurs first.

Endurance

—

1M

—

1M

—

1M

— cycles

25

°C, Vcc =

5.0V, Block

Mode (Note 2)

Note 1: Not 100% tested.

2:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: READ WAVEFORMS

Address	VIH	Address Valid
	VIL
	VIH
CE	VIL
			tCE(2)
	VIH
OE							tOFF(1,3)
	VIL
					tOE(2)		tOH
	VOH						High Z
Data	High Z
	VOL						Valid Output
		tACC

VIH

WE

VIL

Notes: (1) tOFF is specified for OE or CE, whichever occurs first

(2)OE may be delayed up to tCE - t OE after the falling edge of CE without impact on tCE

(3)This parameter is sampled and is not 100% tested

1996 Microchip Technology Inc.

DS11109H-page 3