Microchip Technology Inc PIC16C620-04-P, PIC16C620-04-SO, PIC16C621-04I-SS, PIC16C621-20-P, PIC16C621-20-SO Datasheet

PIC16C62X

EPROM-Based 8-Bit CMOS Microcontroller

Devices included in this data sheet:

Referred to collectively as PIC16C62X .

•	PIC16C620	•	PIC16C620A
•	PIC16C621	•	PIC16C621A
•	PIC16C622	•	PIC16C622A
•	PIC16CR620A

High Performance RISC CPU:

•Only 35 instructions to learn

•All single-cycle instructions (200 ns), except for program branches which are two-cycle

•Operating speed:

-DC - 20 MHz clock input

-DC - 200 ns instruction cycle

Device	Program	Data
	Memory	Memory
PIC16C620	512	80
PIC16C620A	512	96
PIC16CR620A	512	96
PIC16C621	1K	80
PIC16C621A	1K	96
PIC16C622	2K	128
PIC16C622A	2K	128

•Interrupt capability

•16 special function hardware registers

•8-level deep hardware stack

•Direct, Indirect and Relative addressing modes

Peripheral Features:

•13 I/O pins with individual direction control

•High current sink/source for direct LED drive

•Analog comparator module with:

-Two analog comparators

-Programmable on-chip voltage reference (VREF) module

-Programmable input multiplexing from device inputs and internal voltage reference

-Comparator outputs can be output signals

•Timer0: 8-bit timer/counter with 8-bit programmable prescaler

Special Microcontroller Features:

•Power-on Reset (POR)

•Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

•Brown-out Reset

•Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

RA2/AN2/VREF	•1		18	RA1/AN1
RA3/AN3	2	PIC16C62X	17	RA0/AN0
RA4/T0CKI	3		16	OSC1/CLKIN
MCLR/VPP	4		15	OSC2/CLKOUT
VSS	5		14	VDD
RB0/INT	6		13	RB7
RB1	7		12	RB6
RB2	8		11	RB5
RB3	9		10	RB4

SSOP

RA2/AN2/VREF	•1		20	RA1/AN1
RA3/AN3	2		19	RA0/AN0
RA4/T0CKI	3	PIC16C62X	18	OSC1/CLKIN
MCLR/VPP	4		17	OSC2/CLKOUT
VSS	5		16	VDD
VSS	6		15	VDD
RB0/INT	7		14	RB7
RB1	8		13	RB6
RB2	9		12	RB5
RB3	10		11	RB4

Special Microcontroller Features (cont’d)

•Programmable code protection

•Power saving SLEEP mode

•Selectable oscillator options

•Serial in-circuit programming (via two pins)

•Four user programmable ID locations

CMOS Technology:

•Low-power, high-speed CMOS EPROM technology

•Fully static design

•Wide operating voltage range

-PIC16C62X - 2.5V to 6.0V

-PIC16C62XA - 2.5V to 5.5V

-PIC16CR620A - 2.0V to 5.5V

•Commercial, industrial and extended temperature range

•Low power consumption

-< 2.0 mA @ 5.0V, 4.0 MHz

-15 A typical @ 3.0V, 32 kHz

-< 1.0 A typical standby current @ 3.0V

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 1

PIC16C62X

Device Differences

		Voltage		Process
	Device		Oscillator	Technology
		Range
				(Microns)
	PIC16C620	2.5 - 6.0	See Note 1	0.9
	PIC16C621	2.5 - 6.0	See Note 1	0.9
	PIC16C622	2.5 - 6.0	See Note 1	0.9
	PIC16C620A	2.5 - 5.5	See Note 1	0.7
	PIC16CR620A	2.0 - 5.5	See Note 1	0.7
	PIC16C621A	2.5 - 5.5	See Note 1	0.7
	PIC16C622A	2.5 - 5.5	See Note 1	0.7

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

DS30235G-page 2

Preliminary

1998 Microchip Technology Inc.

			PIC16C62X
Table of Contents
1.0	General Description ......................................................................................................................................................................		5
2.0	PIC16C62X Device Varieties .......................................................................................................................................................		7
3.0	Architectural Overview .................................................................................................................................................................		9
4.0	Memory Organization ................................................................................................................................................................		13
5.0	I/O Ports	....................................................................................................................................................................................	25
6.0	Timer0 Module ..........................................................................................................................................................................		31
7.0	Comparator Module ...................................................................................................................................................................		37
8.0	Voltage Reference Module ........................................................................................................................................................		43
9.0	Special Features of the CPU .....................................................................................................................................................		45
10.0	Instruction Set Summary ...........................................................................................................................................................		61
11.0	Development Support ................................................................................................................................................................		73
12.0	Electrical Specifications .............................................................................................................................................................		79
13.0	Device Characterization Information .........................................................................................................................................		93
14.0	Packaging Information ...............................................................................................................................................................		95
Appendix A:		Enhancements..........................................................................................................................................................	101
Appendix B:		Compatibility .............................................................................................................................................................	101
Appendix C:		What’s New...............................................................................................................................................................	102
Appendix D:		What’s Changed .......................................................................................................................................................	102
Index	..................................................................................................................................................................................................		103
PIC16C62X ........................................................................................................................................Product Identification System			107

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•Microchip’s Worldwide Web site; http://www.microchip.com

•Your local Microchip sales office (see last page)

•The Microchip Corporate Literature Center; U.S. FAX: [phone]

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please:

•Fill out and mail in the reader response form in the back of this data sheet.

•E-mail us at [e-mail].

We appreciate your assistance in making this a better document.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 3

PIC16C62X

NOTES:

DS30235G-page 4

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

1.0GENERAL DESCRIPTION

The PIC16C62X are 18 and 20 Pin ROM/EPROM-based members of the versatile PICmicro™ family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers.

All PICmicro™ m icrocontrollers employ an advanced RISC architecture. The PIC16C62X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.

PIC16C62X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC16C620A, PIC16C621A and PIC16CR620A have 96 bytes of RAM. The PIC16C622(A) has 128 bytes of RAM. Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, the PIC16C62X adds two analog comparators with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc).

PIC16C62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake up the chip from SLEEP through several external and internal interrupts and reset.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.

A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume.

Table 1-1 shows the features of the PIC16C62X mid-range microcontroller families.

A simplified block diagram of the PIC16C62X is shown in Figure 3-1.

The PIC16C62X series fit perfectly in applications ranging from battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O flexibility make the PIC16C62X very versatile.

1.1Family and Upward Compatibility

Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to PIC16C62X family of devices (Appendix B). The PIC16C62X family fills the niche for users wanting to migrate up from the PIC16C5X family and not needing various peripheral features of other members of the PIC16XX mid-range microcontroller family.

1.2Development Support

The PIC16C62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A “C”compiler and fuzzy logic support tools are also available.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 5

PIC16C62X

TABLE 1-1: PIC16C62X FAMILY OF DEVICES

			PIC16C620	PIC16C620A	PIC16CR620A	PIC16C621	PIC16C621A	PIC16C622	PIC16C622A
	Clock	Maximum Frequency	20	20	20	20	20	20	20
		of Operation (MHz)
		EPROM Program	512	512	512	1K	1K	2K	2K
	Memory	Memory
		(x14 words)
		Data Memory (bytes)	80	96	96	80	96	128	128
		Timer Module(s)	TMR0	TMR0	TMRO	TMR0	TMR0	TMR0	TMR0
	Peripherals	Comparators(s)	2	2	2	2	2	2	2
		Internal Reference	Yes	Yes	Yes	Yes	Yes	Yes	Yes
		Voltage
		Interrupt Sources	4	4	4	4	4	4	4
		I/O Pins	13	13	13	13	13	13	13
	Features	Voltage Range (Volts)	2.5-6.0	3.0-5.5	2.5-5.5	2.5-6.0	3.0-5.5	2.5-6.0	3.0-5.5
		Brown-out Reset	Yes	Yes	Yes	Yes	Yes	Yes	Yes
		Packages	18-pin DIP,	18-pin DIP,	18-pin DIP,	18-pin DIP,	18-pin DIP,	18-pin DIP,	18-pin DIP,
			SOIC;	SOIC;	SOIC;	SOIC;	SOIC;	SOIC;	SOIC;
			20-pin SSOP	20-pin SSOP	20-pin SSOP	20-pin SSOP	20-pin SSOP	20-pin SSOP	20-pin SSOP

All PICmicro™ F amily devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.

DS30235G-page 6

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

2.0PIC16C62X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16C62X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.

2.1UV Erasable Devices

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.

Microchip's PICSTART and PRO MATE programmers both support programming of the PIC16C62X.

2.2One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.

2.3Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.

2.4Serialized Quick-Turnaround-Production (SQTPSM) Devices

Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 7

PIC16C62X

NOTES:

DS30235G-page 8

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

3.0ARCHITECTURAL OVERVIEW

The high performance of the PIC16C62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a sin- gle-cycle (200 ns @ 20 MHz) except for program branches.

The PIC16C620A and PIC16CR620A address 512 x 14 on-chip program memory. The PIC16C621(A) addresses 1K x 14 program memory. The PIC16C622(A) addresses 2K x 14 program memory. All program memory is internal.

The PIC16C62X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16C62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C62X simple yet efficient. In addition, the learning curve is reduced significantly.

The PIC16C62X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and SUBWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 9

PIC16C62X

FIGURE 3-1: BLOCK DIAGRAM

	Device	Program Memory	Data Memory
			(RAM)
	PIC16C620	512 x 14	80 x 8
	PIC16C620A	512 x 14	96 x 8
	PIC16CR620A	512 x 14	96 x 8
	PIC16C621	1K x 14	80 x 8
	PIC16C621A	1K x 14	96 x 8
	PIC16C622	2K x 14	128 x 8
	PIC16C622A	2K x 14	128 x 8

	13	Data Bus	8
	Program Counter
EPROM
Program	8 Level Stack	RAM
Memory
	(13-bit)	File
		Registers

Program	14	RAM Addr (1)	9
Bus

Instruction reg				Addr MUX
	Direct Addr	7		8	Indirect
					Addr
				FSR reg
				STATUS reg
			3	MUX
	Power-up
	Timer
Instruction	Oscillator
Decode &				ALU
	Start-up Timer
Control
	Power-on
Timing	Reset			W reg
Generation	Watchdog
OSC1/CLKIN
	Timer
OSC2/CLKOUT	Brown-out
	Reset

Voltage

Reference

Comparator
	RA0/AN0
-	RA1/AN1
+	RA2/AN2/VREF
-	RA3/AN3
+
TMR0
	RA4/T0CKI

I/O Ports

PORTB

MCLR VDD, VSS

Note 1: Higher order bits are from the STATUS register.

DS30235G-page 10

Preliminary

1998 Microchip Technology Inc.

										PIC16C62X
TABLE 3-1:			PIC16C62X PINOUT DESCRIPTION
Name				DIP/	SSOP	I/O/P		Buffer		Description
				SOIC
					Pin #	Type		Type
				Pin #
OSC1/CLKIN				16	18	I		ST/CMOS	Oscillator crystal input/external clock source input.
	OSC2/CLKOUT			15	17	O		—	Oscillator crystal output. Connects to crystal or resonator
									in crystal oscillator mode. In RC mode, OSC2 pin outputs
									CLKOUT which has 1/4 the frequency of OSC1, and
									denotes the instruction cycle rate.
				4	4	I/P		ST	Master clear (reset) input/programming voltage input.
	MCLR/VPP
									This pin is an active low reset to the device.
									PORTA is a bi-directional I/O port.
	RA0/AN0			17	19	I/O		ST		Analog comparator input
	RA1/AN1			18	20	I/O		ST		Analog comparator input
	RA2/AN2/VREF			1	1	I/O		ST		Analog comparator input or VREF output
RA3/AN3				2	2	I/O		ST		Analog comparator input /output
	RA4/T0CKI			3	3	I/O		ST		Can be selected to be the clock input to the Timer0
										timer/counter or a comparator output. Output is open
										drain type.
									PORTB is a bi-directional I/O port. PORTB can be
									software programmed for internal weak pull-up on all
									inputs.
	RB0/INT			6	7	I/O		TTL/ST(1)		RB0/INT can also be selected as an external
										interrupt pin.
RB1				7	8	I/O		TTL
	RB2			8	9	I/O		TTL
	RB3			9	10	I/O		TTL
	RB4			10	11	I/O		TTL		Interrupt on change pin.
	RB5			11	12	I/O		TTL		Interrupt on change pin.
	RB6			12	13	I/O		TTL/ST(2)		Interrupt on change pin. Serial programming clock.
RB7				13	14	I/O		TTL/ST(2)		Interrupt on change pin. Serial programming data.
VSS				5	5,6	P		—	Ground reference for logic and I/O pins.
VDD				14	15,16	P		—	Positive supply for logic and I/O pins.
	Legend:			O = output			I/O = input/output			P = power
				— = Not used			I = Input			ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 11

PIC16C62X

3.1Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

3.2Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q1	Q2	Q3	Q4	Q1	Q2	Q3	Q4	Q1	Q2	Q3	Q4
OSC1
Q1
Q2											Internal
Q3											phase
											clock
Q4
PC		PC			PC+1					PC+2
OSC2/CLKOUT
(RC mode)	Fetch INST (PC)
	Execute INST (PC-1)				Fetch INST (PC+1)
					Execute INST (PC)				Fetch INST (PC+2)
									Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1.	MOVLW	55h	Fetch 1	Execute 1
2.	MOVWF	PORTB		Fetch 2	Execute 2
3.	CALL	SUB_1			Fetch 3	Execute 3
4.	BSF	PORTA, BIT3				Fetch 4	Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS30235G-page 12

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.0MEMORY ORGANIZATION

4.1Program Memory Organization

The PIC16C62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16C620(A) and PIC16CR620, 1K x 14 (0000h - 03FFh) for the PIC16C621(A) and 2K x 14 (0000h - 07FFh) for the PIC16C622(A) are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 space (PIC16C(R)620(A)) or 1K x 14 space (PIC16C621(A)) or 2K x 14 space (PIC16C622(A)). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).

FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C620/PIC16C620A/ PIC16CR620A

	PC<12:0>
CALL, RETURN	13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector		000h
Interrupt Vector		0004
		0005
On-chip Program
	Memory
		01FFh
		0200h
		1FFFh

FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C621/PIC16C621A

	PC<12:0>
CALL, RETURN	13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector		000h
Interrupt Vector		0004
		0005
On-chip Program
	Memory
		03FFh
		0400h
		1FFFh

FIGURE 4-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C622/PIC16C622A

	PC<12:0>
CALL, RETURN	13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector		000h
Interrupt Vector		0004
		0005
On-chip Program
	Memory
		07FFh
		0800h
		1FFFh

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 13

PIC16C62X

4.2Data Memory Organization

The data memory (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7) is partitioned into two Banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-7Fh (Bank0) on the PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16C622 and PIC16C622A are general purpose registers implemented as static RAM. Some special purpose registers are mapped in Bank 1.

Addresses F0h-FFh of bank1 are implemented as common ram and mapped back to addresses 70h-7Fh in bank0 on the PIC16C620A/CR620A/621A/622A.

4.2.1GENERAL PURPOSE REGISTER FILE

The register file is organized as 80 x 8 in the PIC16C620/621, 96 x 8 in the PIC16C620A/621A/CR620A and 128 x 8 in the PIC16C622(A). Each is accessed either directly or indirectly through the File Select Register FSR (Section 4.4).

DS30235G-page 14

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

FIGURE 4-4: DATA MEMORY MAP FOR THE PIC16C620/621

File								File
Address						Address
00h				INDF(1)	INDF(1)			80h
01h				TMR0	OPTION			81h
02h				PCL	PCL			82h
03h				STATUS	STATUS			83h
								84h
04h				FSR	FSR
05h				PORTA	TRISA			85h
06h				PORTB	TRISB			86h
07h								87h
								88h
08h
09h								89h
0Ah				PCLATH	PCLATH			8Ah
0Bh				INTCON	INTCON			8Bh
0Ch				PIR1	PIE1			8Ch
0Dh								8Dh
0Eh					PCON			8Eh
0Fh								8Fh
10h								90h
11h								91h
12h								92h
13h								93h
14h								94h
15h								95h
16h								96h
17h								97h
18h								98h
19h								99h
1Ah								9Ah
1Bh								9Bh
1Ch								9Ch
1Dh								9Dh
1Eh								9Eh
1Fh				CMCON	VRCON			9Fh
20h				General				A0h
				Purpose
6Fh				Register
70h

7Fh			FFh
	Bank 0	Bank 1

Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.

FIGURE 4-5: DATA MEMORY MAP FOR THE PIC16C622

File								File
Address						Address
00h				INDF(1)	INDF(1)			80h
01h				TMR0	OPTION			81h
02h				PCL	PCL			82h
03h				STATUS	STATUS			83h
								84h
04h				FSR	FSR
05h				PORTA	TRISA			85h
06h				PORTB	TRISB			86h
07h								87h
								88h
08h
09h								89h
0Ah				PCLATH	PCLATH			8Ah
0Bh				INTCON	INTCON			8Bh
0Ch				PIR1	PIE1			8Ch
0Dh								8Dh
0Eh					PCON			8Eh
0Fh								8Fh
10h								90h
11h								91h
12h								92h
13h								93h
14h								94h
15h								95h
16h								96h
17h								97h
18h								98h
19h								99h
1Ah								9Ah
1Bh								9Bh
1Ch								9Ch
1Dh								9Dh
1Eh								9Eh
1Fh				CMCON	VRCON			9Fh
20h				General	General			A0h
				Purpose	Purpose
				Register	Register			BFh
								C0h

7Fh			FFh
	Bank 0	Bank 1

Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 15

PIC16C62X

FIGURE 4-6: DATA MEMORY MAP FOR THE PIC16C620A/

CR620A/621A

File				File
Address				Address
00h		INDF(1)	INDF(1)	80h
01h		TMR0	OPTION	81h
02h				82h
		PCL	PCL
03h		STATUS	STATUS	83h
04h		FSR	FSR	84h
05h		PORTA	TRISA	85h
06h		PORTB	TRISB	86h
07h				87h
08h				88h
09h				89h
0Ah		PCLATH	PCLATH	8Ah
0Bh		INTCON	INTCON	8Bh
0Ch		PIR1	PIE1	8Ch
0Dh				8Dh
0Eh			PCON	8Eh
0Fh				8Fh
10h				90h
11h				91h
12h				92h
13h				93h
14h				94h
15h				95h
16h				96h
17h				97h
18h				98h
19h				99h
1Ah				9Ah
1Bh				9Bh
1Ch				9Ch
1Dh				9Dh
1Eh				9Eh
1Fh		CMCON	VRCON	9Fh
20h				A0h
		General
		Purpose
		Register
6Fh
70h				F0h
			Accesses
			70h-7Fh
7Fh				FFh
		Bank 0	Bank 1

Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.

FIGURE 4-7: DATA MEMORY MAP FOR THE PIC16C622A

File					File
Address					Address
00h			INDF(1)	INDF(1)	80h
01h			TMR0	OPTION	81h
02h			PCL	PCL	82h
03h			STATUS	STATUS	83h
04h					84h
			FSR	FSR
05h			PORTA	TRISA	85h
06h			PORTB	TRISB	86h
07h					87h
08h					88h
09h					89h
0Ah			PCLATH	PCLATH	8Ah
0Bh			INTCON	INTCON	8Bh
0Ch			PIR1	PIE1	8Ch
0Dh					8Dh
0Eh				PCON	8Eh
0Fh					8Fh
10h					90h
11h					91h
12h					92h
13h					93h
14h					94h
15h					95h
16h					96h
17h					97h
18h					98h
19h					99h
1Ah					9Ah
1Bh					9Bh
1Ch					9Ch
1Dh					9Dh
1Eh					9Eh
1Fh			CMCON	VRCON	9Fh
20h					A0h
			General	General
			Purpose	Purpose
			Register	Register	BFh
					C0h
6Fh					F0h
70h				Accesses
				70h-7Fh
7Fh					FFh
			Bank 0	Bank 1

Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.

DS30235G-page 16

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.2.2SPECIAL FUNCTION REGISTERS

The special function registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM.

The special registers can be classified into two sets (core and peripheral). The special function registers associated with the “core”functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

TABLE 4-1:

SPECIAL REGISTERS FOR THE PIC16C62X

Value on

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

other

POR Reset

resets(1)

Bank 0

00h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical

xxxx xxxx

xxxx xxxx

register)

01h

TMR0

Timer0 Module’s Register

xxxx xxxx

uuuu uuuu

02h

PCL

Program Counter's (PC) Least Significant Byte

0000

0000

0000

0000

03h

STATUS

IRP(2)

RP1(2)

RP0

TO

PD

Z

DC

C

0001

1xxx

000q

quuu

04h

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

—

—

—

RA4

RA3

RA2

RA1

RA0

---x 0000

---u 0000

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

07h

Unimplemented

—

—

08h

Unimplemented

—

—

09h

Unimplemented

—

—

0Ah

PCLATH

—

—

—

Write buffer for upper 5 bits of program counter

---0 0000

---0 0000

0Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000

000x

0000

000u

0Ch

PIR1

—

CMIF

—

—

—

—

—

—

-0-- ----

-0-- ----

0Dh-1Eh

Unimplemented

—

—

1Fh

CMCON

C2OUT

C1OUT

—

—

CIS

CM2

CM1

CM0

00-- 0000

00-- 0000

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical

xxxx xxxx

xxxx xxxx

register)

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

83h

STATUS

IRP(2)

RP1(2)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

—

—

—

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

---1 1111

---1 1111

86h

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

1111 1111

1111 1111

87h

Unimplemented

—

—

88h

Unimplemented

—

—

89h

Unimplemented

—

—

8Ah

PCLATH

—

—

—

Write buffer for upper 5 bits of program counter

---0 0000

---0 0000

8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

8Ch

PIE1

—

CMIE

—

—

—

—

—

—

-0-- ----

-0-- ----

8Dh

Unimplemented

—

—

8Eh

PCON

—

—

—

—

—

—

POR

BOR

---- --0x

---- --uq

8Fh-9Eh

Unimplemented

—

—

9Fh

VRCON

VREN

VROE

VRR

—

VR3

VR2

VR1

VR0

0000000

0000000

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

Note 2: IRP & RPI bits are reserved, always maintain these bits clear.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 17

PIC16C62X

4.2.2.1STATUS REGISTER

The STATUS register, shown in Figure 4-8, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uu1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the “Instruction Set Summary”.

Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C62X and should be programmed as ’0'.Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products.

Note 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-8: STATUS REGISTER (ADDRESS 03H OR 83H)

Reserved	Reserved	R/W-0	R-1			R-1			R/W-x	R/W-x	R/W-x
IRP	RP1	RP0							Z	DC	C
				TO			PD
bit7											bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved on the PIC16C62X, always maintain this bit clear.

R = Readable bit W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

-x = Unknown at POR reset

bit

6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X, always maintain this bit clear.

bit

4:

: Time-out bit

TO

1

= After power-up, CLRWDT instruction, or SLEEP instruction

0

= A WDT time-out occurred

bit

3:

: Power-down bit

PD

1

= After power-up or by the CLRWDT instruction

0

= By execution of the SLEEP instruction

bit

2:

Z: Zero bit

1

= The result of an arithmetic or logic operation is zero

0

= The result of an arithmetic or logic operation is not zero

bit

1: DC: Digit carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)

1

= A carry-out from the 4th low order bit of the result occurred

0

= No carry-out from the 4th low order bit of the result

bit

0:

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

C: Carry/borrow

1

= A carry-out from the most significant bit of the result occurred

0

= No carry-out from the most significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

DS30235G-page 18

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.2.2.2OPTION REGISTER

The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1).

FIGURE 4-9: OPTION REGISTER (ADDRESS 81H)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

R

= Readable bit

bit7

bit0

W

= Writable bit

- n = Value at POR reset

bit 7:

: PORTB Pull-up Enable bit

RBPU

1

= PORTB pull-ups are disabled

0

= PORTB pull-ups are enabled by individual port latch values

bit

6:

INTEDG: Interrupt Edge Select bit

1

= Interrupt on rising edge of RB0/INT pin

0

= Interrupt on falling edge of RB0/INT pin

bit

5:

T0CS: TMR0 Clock Source Select bit

1

= Transition on RA4/T0CKI pin

0

= Internal instruction cycle clock (CLKOUT)

bit

4:

T0SE: TMR0 Source Edge Select bit

1

= Increment on high-to-low transition on RA4/T0CKI pin

0

= Increment on low-to-high transition on RA4/T0CKI pin

bit

3:

PSA: Prescaler Assignment bit

1

= Prescaler is assigned to the WDT

0

= Prescaler is assigned to the Timer0 module

bit

2-0:

PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

1

: 2

1

: 1

001

1

: 4

1

: 2

010

1

: 8

1

: 4

011

1

: 16

1

: 8

100

1

: 32

1

: 16

101

1

: 64

1

: 32

110

1

: 128

1

: 64

111

1

: 256

1

: 128

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 19

PIC16C62X

4.2.2.3INTCON REGISTER

The

INTCON register

is a

readable

and

writable

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

register which contains the various enable and flag bits

its corresponding enable bit or the global

for all interrupt sources except the comparator module.

enable bit, GIE (INTCON<7>).

See

Section 4.2.2.4

and

Section 4.2.2.5

for

a

description of the comparator enable and flag bits.

FIGURE 4-10: INTCON REGISTER (ADDRESS 0BH OR 8BH)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

-x = Unknown at POR reset

bit 7:

GIE: Global Interrupt Enable bit

1

= Enables all un-masked interrupts

0

= Disables all interrupts

bit

6: PEIE: Peripheral Interrupt Enable bit

1

= Enables all un-masked peripheral interrupts

0

= Disables all peripheral interrupts

bit

5: T0IE: TMR0 Overflow Interrupt Enable bit

1

= Enables the TMR0 interrupt

0

= Disables the TMR0 interrupt

bit

4: INTE: RB0/INT External Interrupt Enable bit

1

= Enables the RB0/INT external interrupt

0

= Disables the RB0/INT external interrupt

bit

3: RBIE: RB Port Change Interrupt Enable bit

1

= Enables the RB port change interrupt

0

= Disables the RB port change interrupt

bit

2: T0IF: TMR0 Overflow Interrupt Flag bit

1

= TMR0 register has overflowed (must be cleared in software)

0

= TMR0 register did not overflow

bit

1: INTF: RB0/INT External Interrupt Flag bit

1

= The RB0/INT external interrupt occurred (must be cleared in software)

0

= The RB0/INT external interrupt did not occur

bit

0: RBIF: RB Port Change Interrupt Flag bit

1

= When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0

= None of the RB7:RB4 pins have changed state

DS30235G-page 20

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.2.2.4PIE1 REGISTER

This register contains the individual enable bit for the comparator interrupt.

FIGURE 4-11: PIE1 REGISTER (ADDRESS 8CH)

U-0

R/W-0

U-0

U-0

U-0

U-0

U-0

U-0

—

CMIE

—

—

—

—

—

—

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n

= Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit

6:

CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

bit

5-0: Unimplemented: Read as '0'

4.2.2.5PIR1 REGISTER

This register contains the individual flag bit for the comparator interrupt.

Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

FIGURE 4-12: PIR1 REGISTER (ADDRESS 0CH)

U-0

R/W-0

U-0

U-0

U-0

U-0

U-0

U-0

—

CMIF

—

—

—

—

—

—

R

= Readable bit

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n

= Value at POR reset

bit 7:

Unimplemented: Read as'0'

bit

6:

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed

0 = Comparator input has not changed

bit

5-0: Unimplemented: Read as '0'

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 21

PIC16C62X

4.2.2.6PCON REGISTER

The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset, WDT reset or a Brown-out Reset.

Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BOREN bit in the Configuration word).

FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh)

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-0

—

—

—

—

—

—

R

= Readable bit

POR

BOR

bit7

bit0

W

= Writable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-2:

Unimplemented: Read as '0'

bit

1:

: Power-on Reset Status bit

POR

1

= No Power-on Reset occurred

0

= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit

0:

: Brown-out Reset Status bit

BOR

1

= No Brown-out Reset occurred

0

= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS30235G-page 22

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.3PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-14: LOADING OF PC IN DIFFERENT SITUATIONS

				PCH										PCL
12							8			7							0		Instruction with
PC																			PCL as
		5					PCLATH<4:0>											8	Destination
																			ALU result
								PCLATH
			PCH											PCL
12		11			10		8			7							0
PC																			GOTO, CALL
2			PCLATH<4:3>														11		Opcode <10:0>
							PCLATH

4.3.1COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note “Implementing aTable Read" (AN556).

4.3.2STACK

The PIC16C62X family has an 8 level deep x 13-bit wide hardware stack (Figure 4-2 and Figure 4-3). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions.

Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the

CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 23

PIC16C62X

4.4Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-15. However, IRP is not used in the PIC16C62X.

A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

	movlw	0x20	;initialize pointer
	movwf	FSR	;to RAM
NEXT	clrf	INDF	;clear INDF register
	incf	FSR	;inc pointer
	btfss	FSR,4	;all done?
	goto	NEXT	;no clear next
			;yes continue
CONTINUE:

FIGURE 4-15: DIRECT/INDIRECT ADDRESSING PIC16C62X

					Direct Addressing																	Indirect Addressing
(1)RP1 RP0					6	from opcode								0				IRP(1)				7		FSR register						0
bank select					location select									00	01	10	11	bank select									location select
										00h									180h

not used

Data Memory

7Fh			1FFh
	Bank 0	Bank 1 Bank 2 Bank 3

For memory map detail see (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7).

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

DS30235G-page 24

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

5.0I/O PORTS

The PIC16C62X have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output.

A '1' in theTRISA register puts the corresponding output driver in a hiimpedance mode. A '0' in theTRISA register puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch.

The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as '0's.

FIGURE 5-1: BLOCK DIAGRAM OF RA1:RA0 PINS

Data

bus D Q

WR			VDD
PortA	CK	Q	P
	Data Latch

	D	Q
WR				N	I/O Pin
TRISA	CK	Q
	TRIS Latch			VSS
			Analog
			Input Mode
			Schmitt Trigger
	RD TRISA		Input Buffer
			Q	D
			EN
RD PORTA

To Comparator

Note: I/O pins have protection diodes to VDD and VSS.

Note: On reset, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.

TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs.

The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high impedance output. The user must configure TRISA<2> bit as an input and use high impedance loads.

In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.

EXAMPLE 5-1: INITIALIZING PORTA

CLRF	PORTA	;Initialize PORTA by setting
		;output data latches
MOVLW	0X07	;Turn comparators off and
MOVWF	CMCON	;enable pins for I/O
		;functions
BSF	STATUS, RP0 ;Select Bank1
MOVLW	0x1F	;Value used to initialize
		;data direction
MOVWF	TRISA	;Set RA<4:0> as inputs
		;TRISA<7:5> are always
		;read as '0'.

FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN

Data
bus	D	Q
WR			VDD
PortA	CK	Q	P
	Data Latch

	D	Q
WR				N	RA2 Pin
TRISA	CK	Q
	TRIS Latch			VSS
			Analog
			Input Mode
			Schmitt Trigger
	RD TRISA		Input Buffer
			Q	D
			EN
RD PORTA
	To Comparator
	VROE
	VREF

Note: I/O pins have protection diodes to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 25

PIC16C62X
FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN
Data			Comparator Mode = 110
bus
	D		Q
WR			Comparator Output	VDD
PortA		CK	Q	P
	Data Latch
	D		Q
WR				N	RA3 Pin
TRISA		CK	Q
	TRIS Latch			VSS
				Analog
				Input Mode
				Schmitt Trigger
		RD TRISA		Input Buffer
			Q	D
				EN
RD PORTA
	To Comparator
Note:		I/O pins have protection diodes to VDD and VSS

FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN
Data			Comparator Mode = 110
bus
		D	Q
WR			Comparator Output
PortA		CK	Q
		Data Latch
		D	Q
WR				N	RA4 Pin
TRISA		CK	Q
		TRIS Latch		VSS
				Schmitt Trigger
		RD TRISA		Input Buffer
			Q	D
				EN
RD PORTA
		TMR0 Clock Input
	Note:		RA4 has protection diodes to VSS only

DS30235G-page 26

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

	TABLE 5-1:	PORTA FUNCTIONS
	Name	Bit #	Buffer	Function
			Type
	RA0/AN0	bit0	ST	Input/output or comparator input
	RA1/AN1	bit1	ST	Input/output or comparator input
	RA2/AN2/VREF	bit2	ST	Input/output or comparator input or VREF output
	RA3/AN3	bit3	ST	Input/output or comparator input/output
	RA4/T0CKI	bit4	ST	Input/output or external clock input for TMR0 or comparator output.
				Output is open drain type.

Legend: ST = Schmitt Trigger input

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

POR

Resets

05h

PORTA

—

—

—

RA4

RA3

RA2

RA1

RA0

---x 0000

---u 0000

85h

TRISA

—

—

—

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

---1 1111

---1 1111

1Fh

CMCON

C2OUT

C1OUT

—

—

CIS

CM2

CM1

CM0

00-- 0000

00-- 0000

9Fh

VRCON

VREN

VROE

VRR

—

VR3

VR2

VR1

VR0

0000000

0000000

Legend:

— = Unimplemented locations , read as ‘0’, u = unchanged, x = unknown

Note: Note: Shaded bits are not used by PORTA.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 27

PIC16C62X

5.2PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in theTRISB register puts the contents of the output latch on the selected pin(s).

Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up (≈200 A typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch”outputs of RB7:RB4 are OR’ed together to generate the RBIF interrupt (flag latched in INTCON<0>).

FIGURE 5-5: BLOCK DIAGRAM OF RB7:RB4 PINS

VDD

RBPU(2)			P	weak
				pull-up
Data bus	Data Latch
	D	Q
WR PortB				I/O
		CK Q		pin(1)
	TRIS Latch
	D	Q
WR TRISB		CK Q	TTL
			Input
			Buffer	ST
				Buffer
	RD TRISB		Latch
		Q	D
Set RBIF	RD PortB		EN
From other		Q	D
RB7:RB4 pins
			EN
			RD Port
RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a)Any read or write of PORTB. This will end the mismatch condition.

b)Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.)

Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 5-6: BLOCK DIAGRAM OF RB3:RB0 PINS

VDD

	RBPU(2)	weak
	P
		pull-up

	Data bus	Data Latch
		D	Q
	WR PortB	CK	Q	I/O
				pin(1)
		D	Q	TTL
	WR TRISB	CK	Q	Input
				Buffer
		RD TRISB
			Q	D
		RD PortB		EN
	RB0/INT
		ST		RD Port
		Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).

DS30235G-page 28

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

TABLE 5-3:

PORTB FUNCTIONS

Name

Bit #

Buffer Type

Function

RB0/INT

bit0

TTL/ST(1)

Input/output or external interrupt input. Internal software programmable

weak pull-up.

RB1

bit1

TTL

Input/output pin. Internal software programmable weak pull-up.

RB2

bit2

TTL

Input/output pin. Internal software programmable weak pull-up.

RB3

bit3

TTL

Input/output pin. Internal software programmable weak pull-up.

RB4

bit4

TTL

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up.

RB5

bit5

TTL

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up.

RB6

bit6

TTL/ST(2)

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming clock pin.

RB7

bit7

TTL/ST(2)

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming data pin.

Legend: ST = Schmitt Trigger, TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

TABLE 5-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

POR

Resets

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

86h

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

1111 1111

1111 1111

81h

OPTION

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

RBPU

Note:

Shaded bits are not used by PORTB.

u = unchanged

x = unknown

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 29

PIC16C62X

5.3I/O Programming Considerations

5.3.1BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-2 shows the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”,“wired-and”). The resulting high output currents may damage the chip.

EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT

; Initial PORT settings: PORTB<7:4> Inputs

;
;	PORTB<3:0> Outputs

;PORTB<7:6> have external pull-up and are not

;connected to other circuitry

;
;	PORT latch	PORT pins
;	----------	----------
BCF PORTB, 7	; 01pp pppp	11pp pppp
BCF PORTB, 6	; 10pp pppp	11pp pppp
BSF STATUS,RP0	;
BCF TRISB, 7	; 10pp pppp	11pp pppp
BCF TRISB, 6	; 10pp pppp	10pp pppp
;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

5.3.2SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-7). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-7: SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

	PC	PC	PC + 1	PC + 2	PC + 3
	Instruction	MOVWF PORTB	MOVF PORTB, W	NOP	NOP
	fetched
		Write to	Read PORTB
		PORTB
	RB7:RB0
	RB <7:0>
				Port pin
			TPD	sampled here
			Execute	Execute	Execute
			MOVWF	MOVF	NOP
			PORTB	PORTB, W

Note:

This example shows write to PORTB followed by a read from PORTB.

Note that:

data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

DS30235G-page 30

Preliminary

1998 Microchip Technology Inc.