Microchip Technology Inc PIC16CR54C-04-P, PIC16CR54C-04-SO, PIC16CR54C-04-SS, PIC16CR54C-04I-P, PIC16CR54C-04I-SO Datasheet

M PIC16CR54C

ROM-Based 8-Bit CMOS Microcontroller Series

Devices Included in this Data Sheet:

• PIC16CR54C

High-Performance RISC CPU:

•Only 33 single word instructions to learn

•All instructions are single cycle (200 ns) except for program branches which are two-cycle

•Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

Device	Pins	I/O	ROM	RAM
PIC16CR54C	18	12	512	25

•12-bit wide instructions

•8-bit wide data path

•Seven or eight special function hardware registers

•Two-level deep hardware stack

•Direct, indirect and relative addressing modes for data and instructions

Peripheral Features:

•8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

•Power-On Reset (POR)

•Device Reset Timer (DRT)

•Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

•Programmable code-protection

•Power saving SLEEP mode

•Selectable oscillator options:

-	RC:	Low-cost RC oscillator
-	XT:	Standard crystal/resonator
-	HS:	High-speed crystal/resonator
-	LP:	Power saving, low-frequency crystal

CMOS Technology:

•Low-power, high-speed CMOS ROM technology

•Fully static design

•Wide-operating voltage and temperature range:

-ROM Commercial/Industrial 3.0V to 5.5V

•Low-power consumption

-< 2 mA typical @ 5V, 4 MHz

-15 A typical @ 3V, 32 kHz

-< 0.6 A typical standby current

(with WDT disabled) @ 3V, 0°C to 70°C

Pin Diagrams

PDIP and SOIC

RA2	•1
RA3	2
T0CKI	3
MCLRVPP	4
VSS	5
RB0	6
RB1	7
RB2	8
RB3	9

SSOP

RA2	•1
RA3	2
T0CKI	3
MCLRVPP	4
VSS	5
VSS	6
RB0	7
RB1	8
RB2	9
RB3	10

		18	RA1
	PIC16CR54C	17	RA0
		16	OSC1/CLKIN
		15	OSC2/CLKOUT
		14	VDD
		13	RB7
		12	RB6
		11	RB5
		10	RB4

		20	RA1
	PIC16CR54C	19	RA0
		18	OSC1/CLKIN
		17	OSC2/CLKOUT
		16	VDD
		15	VDD
		14	RB7
		13	RB6
		12	RB5
		11	RB4

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 1

PIC16CR54C

Device Differences

		Oscillator		Process
	Voltage				ROM		MCLR
Device		Selection	Oscillator	Technology
	Range				Equivalent		Filter
		(Program)		(Microns)
PIC16C52	3.0-6.25	User	See Note 1	0.9	—		No
PIC16C54	2.5-6.25	Factory	See Note 1	1.2	PIC16CR54A		No
PIC16C54A	2.0-6.25	User	See Note 1	0.9	—		No
PIC16C54B	3.0-5.5	User	See Note 1	0.7	PIC16CR54B		Yes
					or
					PIC16CR54C
PIC16C55	2.5-6.25	Factory	See Note 1	1.7	—		No
PIC16C55A	3.0-5.5	User	See Note 1	0.7	—		Yes
PIC16C56	2.5-6.25	Factory	See Note 1	1.7	—		No
PIC16C56A	3.0-5.5	User	See Note 1	0.7	PIC16CR56A		Yes
PIC16C57	2.5-6.25	Factory	See Note 1	1.2	—		No
PIC16C57C	3.0-5.5	User	See Note 1	0.7	PIC16CR57C		Yes
PIC16CR57C	2.5-5.5	Factory	See Note 1	0.7	NA		Yes
PIC16C58A	2.0-6.25	User	See Note 1	0.9	PIC16CR58A		No(2)
PIC16C58B	3.0-5.5	User	See Note 1	0.7	PIC16CR58B		Yes
PIC16CR54A	2.5-6.25	Factory	See Note 1	1.2	NA		Yes
PIC16CR54B	2.5-5.5	Factory	See Note 1	0.7	NA		Yes
PIC16CR54C	3.0-5.5	Factory	See Note 1	0.7	NA		Yes
PIC16CR56A	2.5-5.5	Factory	See Note 1	0.7	NA		Yes
PIC16CR57B	2.5-6.25	Factory	See Note 1	0.9	NA		Yes
PIC16CR58A	2.5-6.25	Factory	See Note 1	0.9	NA		Yes
PIC16CR58B	2.5-5.5	Factory	See Note 1	0.7	NA		Yes

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

Note 2: In PIC16LV58A, MCLR Filter = Yes

DS40191A-page 2

Preliminary

1998 Microchip Technology Inc.

		PIC16CR54C
Table of Contents
1.0	General Description .............................................................................................................................................	5
2.0	PIC16C5X Device Varieties .................................................................................................................................	7
3.0	Architectural Overview .........................................................................................................................................	9
4.0	Memory Organization ........................................................................................................................................	13
5.0	I/O Ports ............................................................................................................................................................	19
6.0	Timer0 Module and TMR0 Register ..................................................................................................................	21
7.0	Special Features of the CPU .............................................................................................................................	25
8.0	Instruction Set Summary ...................................................................................................................................	37
9.0	Development Support ........................................................................................................................................	49
10.0	Electrical Characteristics - PIC16CR54C ..........................................................................................................	53
11.0	DC and AC Characteristics - PIC16CR54C .......................................................................................................	63
12.0	Packaging Information .......................................................................................................................................	73
Appendix A: Compatibility .............................................................................................................................................		77
Index	............................................................................................................................................................................	79
On-Line ............................................................................................................................................................Support		81
Reader .........................................................................................................................................................Response		82
PIC16CR54C .................................................................................................................Product Identification System		83

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Preliminary

DS40191A-page 3

PIC16CR54C

NOTES:

DS40191A-page 4

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

1.0GENERAL DESCRIPTION

The PIC16C5X from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/ ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which take two cycles. The PIC16C5X delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly.

The PIC16C5X products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The UV erasable CERDIP packaged versions are ideal for code development, while the cost-effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers while benefiting from the OTP’s flexibility.

The PIC16C5X products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM PC and compatible machines.

1.1Applications

The PIC16C5X series fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The EPROM technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of “glue”logic in larger systems, coprocessor applications).

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 5

PIC16CR54C

TABLE 1-1:		PIC16C5X FAMILY OF DEVICES
			PIC16C52	PIC16C54s		PIC16CR54s		PIC16C55s		PIC16C56s
	Clock	Maximum Frequency	4	20		20		20		20
		of Operation (MHz)
		EPROM Program Memory	384	512		—		512		1K
		(x12 words)
	Memory
		ROM Program Memory	—	—		512		—		—
		(x12 words)
		RAM Data Memory (bytes)	25	25		25		24		25
	Peripherals	Timer Module(s)	TMR0	TMR0		TMR0		TMR0		TMR0
		I/O Pins	12	12		12		20		12
		Number of Instructions	33	33		33		33		33
	Features
		Packages	18-pin DIP,	18-pin DIP,		18-pin DIP,		28-pin DIP,		18-pin DIP,
			SOIC	SOIC;		SOIC;		SOIC;		SOIC;
				20-pin SSOP		20-pin SSOP		28-pin SSOP		20-pin SSOP

All PICmicro™ F amily devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability.

			PIC16CR56s	PIC16C57s		PIC16CR57s		PIC16C58s		PIC16CR58s
	Clock	Maximum Frequency	20	20		20		20		20
		of Operation (MHz)
		EPROM Program Memory	—	2K		—		2K		—
		(x12 words)
	Memory
		ROM Program Memory	1K	—		2K		—		2K
		(x12 words)
		RAM Data Memory (bytes)	25	72		72		73		73
	Peripherals	Timer Module(s)	TMR0	TMR0		TMR0		TMR0		TMR0
		I/O Pins	12	20		20		12		12
		Number of Instructions	33	33		33		33		33
	Features
		Packages	18-pin DIP,	28-pin DIP,		28-pin DIP,		18-pin DIP,		18-pin DIP,
			SOIC;	SOIC;		SOIC;		SOIC;		SOIC;
			20-pin SSOP	28-pin SSOP		28-pin SSOP		20-pin SSOP		20-pin SSOP

All PICmicro™ F amily devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability.

DS40191A-page 6

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

2.0PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16CR54C Product Identification System at the back of this data sheet to specify the correct part number.

For the PIC16C5X family of devices, there are four device types, as indicated in the device number:

1.C, as in PIC16C54. These devices have EPROM program memory and operate over the standard voltage range.

2.LC, as in PIC16LC54A. These devices have EPROM program memory and operate over an extended voltage range.

3.LV, as in PIC16LV54A. These devices have EPROM program memory and operate over a 2.0V to 3.8V range.

4.CR, as in PIC16CR54A. These devices have ROM program memory and operate over the standard voltage range.

5.LCR, as in PIC16LCR54B. These devices have ROM program memory and operate over an extended voltage range.

2.1UV Erasable Devices (EPROM)

The UV erasable versions, offered in CERDIP packages, are optimal for prototype development and pilot programs

UV erasable devices can be programmed for any of the four oscillator configurations. Microchip's PICSTART and PRO MATE programmers both support programming of the PIC16CR54C. Third party programmers also are available; refer to the Third Party Guide for a list of sources.

2.2One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers expecting frequent code changes and updates.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must be programmed.

2.3Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.

2.4Serialized Quick-Turnaround-Production (SQTP SM) Devices

Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory.

Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number.

2.5Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 7

PIC16CR54C

NOTES:

DS40191A-page 8

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

3.0ARCHITECTURAL OVERVIEW

The high performance of the PIC16CR54C can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CR54C uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MHz) except for program branches.

The PIC16CR54C address 512 x 12 of program memory. All program memory is internal.

The PIC16CR54C can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CR54C has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CR54C simple yet efficient. In addition, the learning curve is reduced significantly.

The PIC16CR54C device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 9

PIC16CR54C
FIGURE 3-1:	PIC16CR54C SERIES BLOCK DIAGRAM
	9-11	9-11		T0CKI	CONFIGURATION WORD				OSC1 OSC2 MCLR
		STACK 1
ROM				PIN
		STACK 2
512 X 12	PC				“DISABLE”			“OSC
								SELECT”
12				WATCHDOG		“CODE		2
				TIMER					OSCILLATOR/
INSTRUCTION						PROTECT”
									TIMING &
REGISTER		WDT TIME				CLKOUT			CONTROL
	9			WDT/TMR0
12			OUT	PRESCALER
		8							“SLEEP”
INSTRUCTION
					6
DECODER
							“OPTION”
				OPTION REG.
DIRECT ADDRESS		DIRECT RAM			FROM W				GENERAL
			ADDRESS
									PURPOSE
						5
									REGISTER
8									FILE
									(SRAM)
LITERALS	STATUS								25 Bytes
			TMR0				FSR
									8
W	ALU			DATA BUS
				8
		FROM W			FROM W
			4		8	8
		4
	“TRIS 5”			“TRIS 6”	TRISB	PORTB
		TRISA	PORTA
			4			8
			RA3:RA0			RB7:RB0

DS40191A-page 10

Preliminary

1998 Microchip Technology Inc.

							PIC16CR54C
TABLE 3-1:			PINOUT DESCRIPTION - PIC16CR54C
	Name		DIP, SOIC	SSOP	I/O/P	Input	Description
			No.	No.	Type	Levels
	RA0		17	19	I/O	TTL	Bi-directional I/O port
	RA1		18	20	I/O	TTL
	RA2		1	1	I/O	TTL
	RA3		2	2	I/O	TTL
	RB0		6	7	I/O	TTL	Bi-directional I/O port
	RB1		7	8	I/O	TTL
	RB2		8	9	I/O	TTL
	RB3		9	10	I/O	TTL
	RB4		10	11	I/O	TTL
	RB5		11	12	I/O	TTL
	RB6		12	13	I/O	TTL
	RB7		13	14	I/O	TTL
	T0CKI		3	3	I	ST	Clock input to Timer0. Must be tied to VSS or VDD, if not in
							use, to reduce current consumption.
		PP	4	4	I	ST	Master clear (reset) input/verify voltage input. This pin is an
	MCLR/V
							active low reset to the device.
OSC1/CLKIN			16	18	I	ST(1)	Oscillator crystal input/external clock source input.
OSC2/CLKOUT			15	17	O	—	Oscillator crystal output. Connects to crystal or resonator in
							crystal oscillator mode. In RC mode, OSC2 pin outputs
							CLKOUT which has 1/4 the frequency of OSC1, and denotes
							the instruction cycle rate.
	VDD		14	15,16	P	—	Positive supply for logic and I/O pins.
	VSS		5	5,6	P	—	Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output,
	P = power, — = Not Used, TTL = TTL input,
	ST = Schmitt Trigger input

Note 1: Schmitt Trigger input only when in RC mode.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 11

PIC16CR54C

3.1Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.

3.2Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q1	Q2	Q3	Q4	Q1	Q2	Q3	Q4	Q1	Q2	Q3	Q4
OSC1
Q1
Q2											Internal
Q3											phase
											clock
Q4
PC		PC			PC+1					PC+2
OSC2/CLKOUT
(RC mode)	Fetch INST (PC)
	Execute INST (PC-1)				Fetch INST (PC+1)
					Execute INST (PC)				Fetch INST (PC+2)
									Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1.	MOVLW	55H	Fetch 1	Execute 1
2.	MOVWF	PORTB		Fetch 2	Execute 2
3.	CALL	SUB_1			Fetch 3	Execute 3
4.	BSF	PORTA, BIT3				Fetch 4	Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS40191A-page 12

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1998 Microchip Technology Inc.

4.0MEMORY ORGANIZATION

PIC16CR54C memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS register bits. For devices with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR).

4.1Program Memory Organization

The PIC16CR54C has a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 4-1). Accessing a location above the physically implemented address will cause a wraparound.

The reset vector for the PIC16CR54C is at 1FFh. A NOP at the reset vector location will cause a restart at location 000h.

FIGURE 4-1: PIC16CR54C PROGRAM MEMORY MAP AND STACK

PC<8:0>

CALL, RETLW

9

Stack Level 1

Stack Level 2

000h

MemoryUser Space

On-chip

0FFh

Program

100h

Memory

Reset Vector

1FFh

4.2Data Memory Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers.

The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options.

The general purpose registers are used for data and control information under command of the instructions.

For the PIC16CR54C, the register file is composed of 7 special function registers and 25 general purpose registers (Figure 4-2).

PIC16CR54C

4.2.1GENERAL PURPOSE REGISTER FILE

The register file is accessed either directly or indirectly through the file select register FSR (Section 4.7).

FIGURE 4-2:	PIC16CR54C REGISTER FILE
	MAP
File Address
	00h		INDF(1)
	01h		TMR0
	02h		PCL
	03h		STATUS
	04h		FSR
	05h		PORTA
	06h		PORTB
	07h
	0Fh		General
	10h		Purpose
			Registers
	1Fh
Note 1:	Not a physical register. See Section 4.7

4.2.2SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1).

The special registers can be classified into two sets. The special function registers associated with the “core”functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 13

PIC16CR54C

TABLE 4-1:

SPECIAL FUNCTION REGISTER SUMMARY

Value on

Value on

Power-On

MCLR

and

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

WDT Reset

N/A

TRIS

I/O control registers (TRISA, TRISB)

1111

1111

1111

1111

N/A

OPTION

Contains control bits to configure Timer0 and Timer0/WDT prescaler

--11 1111

--11 1111

00h

INDF

Uses contents of FSR to address data memory (not a physical register)

xxxx xxxx

uuuu uuuu

01h

TMR0

8-bit real-time clock/counter

xxxx xxxx

uuuu uuuu

02h(1)

PCL

Low order 8 bits of PC

1111

1111

1111

1111

03h

STATUS

PA2

PA1

PA0

TO

PD

Z

DC

C

0001

1xxx

000q

quuu

04h

FSR

Indirect data memory address pointer

1xxx xxxx

1uuu uuuu

05h

PORTA

—

—

—

—

RA3

RA2

RA1

RA0

---- xxxx

---- uuuu

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access these bits.

DS40191A-page 14

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

4.3STATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for program memories larger than 512 words.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Section 8.0, Instruction Set Summary.

FIGURE 4-3: STATUS REGISTER (ADDRESS:03h)

R/W-0

R/W-0

R/W-0

R-1

R-1

R/W-x

R/W-x

R/W-x

PA2

PA1

PA0

TO

PD

Z

DC

C

R = Readable bit

bit7

6

5

4

3

2

1

bit0

W = Writable bit

- n = Value at POR reset

bit 7:

PA2: This bit unused at this time.

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward

compatibility with future products.

bit 6-5:

Not Applicable

bit

4:

: Time-out bit

TO

1

= After power-up, CLRWDT instruction, or SLEEP instruction

0

= A WDT time-out occurred

bit

3:

: Power-down bit

PD

1

= After power-up or by the CLRWDT instruction

0

= By execution of the SLEEP instruction

bit

2:

Z: Zero bit

1

= The result of an arithmetic or logic operation is zero

0

= The result of an arithmetic or logic operation is not zero

bit

1:

bit (for ADDWF and SUBWF instructions)

DC: Digit carry/borrow

ADDWF

1

= A carry from the 4th low order bit of the result occurred

0

= A carry from the 4th low order bit of the result did not occur

SUBWF

1

= A borrow from the 4th low order bit of the result did not occur

0

= A borrow from the 4th low order bit of the result occurred

bit

0:

bit (for ADDWF, SUBWF and RRF, RLF instructions)

C: Carry/borrow

ADDWF

SUBWF

RRF or RLF

1

= A carry occurred

1 = A borrow did not occur

Load bit with LSb or MSb, respectively

0

= A carry did not occur

0 = A borrow occurred

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 15

PIC16CR54C

4.4OPTION Register

The OPTION register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0.

FIGURE 4-4: OPTION REGISTER

By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<5:0> bits.

U-0

U-0

W-1

W-1

W-1

W-1

W-1

W-1

—

—

T0CS

T0SE

PSA

PS2

PS1

PS0

W

= Writable bit

bit7

6

5

4

3

2

1

bit0

U

= Unimplemented bit

- n = Value at POR reset

bit 7-6:

Unimplemented.

bit

5:

T0CS: Timer0 clock source select bit

1

= Transition on T0CKI pin

0

= Internal instruction cycle clock (CLKOUT)

bit

4:

T0SE: Timer0 source edge select bit

1

= Increment on high-to-low transition on T0CKI pin

0

= Increment on low-to-high transition on T0CKI pin

bit

3:

PSA: Prescaler assignment bit

1

= Prescaler assigned to the WDT (not implemented on PIC16C52)

0

= Prescaler assigned to Timer0

bit

2-0:

PS2:PS0: Prescaler rate select bits

Bit Value

Timer0 Rate WDT Rate (not implemented on PIC16C52)

000

1

: 2

1 :

1

001

1

: 4

1 :

2

010

1

: 8

1 :

4

011

1

: 16

1 :

8

100

1

: 32

1 :

16

101

1

: 64

1 :

32

110

1

: 128

1 :

64

111

1

: 256

1 :

128

DS40191A-page 16

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

4.5Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 4-5 and Figure 4-6).

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-10 and Figure 4-11)/

Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC, 5.

.

Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).

FIGURE 4-5: LOADING OF PC

BRANCH INSTRUCTIONS - PIC16CR54C

GOTO Instruction

8		7	0
PC			PCL

Instruction Word

CALL or Modify PCL Instruction

8			7	0
PC				PCL
Reset to '0'				Instruction Word

4.5.1EFFECTS OF RESET

The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the reset vector.

The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre-selected.

Therefore, upon a RESET, a GOTO instruction at the reset vector location will automatically cause the program to jump to page 0.

4.6Stack

PIC16CR54C device has a 9-bit, two-level hardware push/pop stack (Figure 4-1).

A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL’s are executed, only the most recent two return addresses are stored.

A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 17

PIC16CR54C

4.7Indirect Data Addressing; INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING

•Register file 05 contains the value 10h

•Register file 06 contains the value 0Ah

•Load the value 05 into the FSR register

•A read of the INDF register will return the value of 10h

•Increment the value of the FSR register by one (FSR = 06)

•A read of the INDR register now will return the value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING

	movlw	0x10	;initialize pointer
	movwf	FSR	; to RAM
NEXT	clrf	INDF	;clear INDF register
	incf	FSR,F	;inc pointer
	btfsc	FSR,4	;all done?
	goto	NEXT	;NO, clear next
CONTINUE
	:		;YES, continue

The FSR is a 5-bit ( PIC16CR54C) wide register. It is used in conjunction with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

PIC16CR54C: Do not use banking. FSR<6:5> are unimplemented and read as '1's.

FIGURE 4-6: DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(FSR)

6 5 4

(FSR)

0

6 5

4 (opcode) 0

bank

location select

bank select

location select

00

00h

Data 0Fh

Memory(1) 10h

1Fh

Bank 0

Note 1: For register map detail see Section 4.2.

DS40191A-page 18

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

5.0I/O PORTS

As with any other register, the I/O registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB, TRISC) are all set.

5.1PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits are used (RA3:RA0). Bits 7-4 are unimplemented and read as '0's.

5.2PORTB

PORTB is an 8-bit I/O register (PORTB<7:0>).

5.3TRIS Registers

The output driver control registers are loaded with the contents of the W register by executing the TRIS f instruction. A '1' from TRISa register bit puts the corresponding output driver in a hi-impedance mode.

A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer.

Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET.

5.4I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All ports may be used for both input and output operation. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The

outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

Data
Bus	D	Q
WR	Data	VDD
	Latch
Port	CK	Q
		P
W		N	I/O
Reg	D	Q	pin(1)
	TRIS	VSS
	Latch
TRIS ‘f’
	CK	Q
	Reset

RD Port

Note 1: I/O pins have protection diodes to VDD and VSS.

TABLE 5-1: SUMMARY OF PORT REGISTERS

Value on

Value on

Power-On

MCLR

and

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

WDT Reset

N/A

TRIS

I/O control registers (TRISA, TRISB)

1111 1111

1111 1111

05h

PORTA

—

—

—

—

RA3

RA2

RA1

RA0

---- xxxx

---- uuuu

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

Legend: Shaded boxes = unimplemented, read as ‘0’,

– = unimplemented, read as '0',x = unknown, u = unchanged

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 19

PIC16CR54C

5.5I/O Programming Considerations

5.5.1BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”,“wired-and”). The resulting high output currents may damage the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT

;Initial PORT Settings

;PORTB<7:4> Inputs

;PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry

;
;		PORT latch	PORT pins
;		----------	----------
BCF	PORTB, 7	;01pp pppp	11pp pppp
BCF	PORTB, 6	;10pp pppp	11pp pppp
MOVLW	03Fh	;
TRIS	PORTB	;10pp pppp	10pp pppp

;

;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High).

5.5.2SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction	PC		PC + 1			PC + 2		PC + 3
fetched	MOVWF PORTB	MOVF PORTB,W				NOP		NOP
RB7:RB0
		Port pin			Port pin
		written here			sampled here
Instruction
executed		MOVWF PORTB			MOVF PORTB,W			NOP
		(Write to			(Read
		PORTB)			PORTB)

This example shows a write to PORTB followed by a read from PORTB.

DS40191A-page 20

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

6.0TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

•8-bit timer/counter register, TMR0

-Readable and writable

•8-bit software programmable prescaler

•Internal or external clock select

-Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0 module, while Figure 6-2 shows the electrical structure of the Timer0 input.

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-3 and Figure 6-4). The user can work around this by writing an adjusted value to the TMR0 register.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler.

A summary of registers associated with the Timer0 module is found in Table 6-1.

Data bus

FOSC/4

0

1

PSout

8

Sync with

1

TMR0 reg

Internal

Clocks

T0CKI

Programmable

0

PSout

pin

Prescaler(2)

T0SE

(1)

(2 cycle delay) Sync

3

PSA(1)

PS2, PS1, PS0(1)

T0CS(1)

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

		RIN
T0CKI		(1)	Schmitt Trigger
pin	(1)	N	Input Buffer

VSS VSS

Note 1: ESD protection circuits

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 21

PIC16CR54C

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

MOVWF TMR0

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

Fetch

Timer0

T0

T0+1

T0+2

NT0

NT0

NT0

NT0+1

NT0+2

Instruction

Executed

Write TMR0

Read TMR0

Read TMR0

Read TMR0

Read TMR0

Read TMR0

executed

reads NT0

reads NT0

reads NT0

reads NT0 + 1

reads NT0 + 2

FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

MOVWF TMR0

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

Fetch

Timer0

T0

T0+1

NT0

NT0+1

T0

Instruction

Write TMR0

Read TMR0

Read TMR0

Read TMR0

Read TMR0

Read TMR0

Execute

executed

reads NT0

reads NT0

reads NT0

reads NT0

reads NT0 + 1

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Power-On

MCLR

and

Reset

WDT Reset

01h

TMR0

Timer0 - 8-bit real-time clock/counter

xxxx xxxx

uuuu uuuu

N/A

OPTION

—

—

T0CS

T0SE

PSA

PS2

PS1

PS0

--11 1111

--11 1111

Legend: Shaded cells: Unimplemented bits,

- = unimplemented, x = unknown, u = unchanged,

DS40191A-page 22

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

6.1Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.

When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.

6.1.2TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

External Clock Input or Prescaler Output (2)

External Clock/Prescaler

Output After Sampling

Increment Timer0 (Q4)

Timer0

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Small pulse

misses sampling

(3)

(1)

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

2:External clock if no prescaler selected, Prescaler output otherwise.

3:The arrows indicate the points in time where sampling occurs.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 23

PIC16CR54C

6.2Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT) (WDT postscaler not implemented on PIC16C52), respectively (Section 6.1.2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's.

6.2.1SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control (i.e., it can be changed “on the y”fl during program execution). To avoid an unintended device RESET, the

following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

EXAMPLE 6-1: CHANGING PRESCALER (TIMER0→WDT)

1.CLRWDT		;Clear WDT
2.CLRF	TMR0	;Clear TMR0 & Prescaler
3.MOVLW	'00xx1111’b	;These 3 lines (5, 6, 7)
4.OPTION		; are required only if
		; desired
5.CLRWDT		;PS<2:0> are 000 or 001
6.MOVLW	'00xx1xxx’b	;Set Postscaler to
7.OPTION		; desired WDT rate

To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.

EXAMPLE 6-2: CHANGING PRESCALER (WDT→TIMER0)

CLRWDT	;Clear WDT and
	;prescaler
MOVLW 'xxxx0xxx'	;Select TMR0, new
	;prescale value and
	;clock source
OPTION

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

Data Bus

0

8

M

1

T0CKI

U

M

1

X

Sync

pin

U

TMR0 reg

2

0

X

Cycles

T0SE

T0CS

PSA

0

M

8-bit Prescaler

U

Watchdog

1

X

8

Timer

8 - to - 1MUX

PS2:PS0

PSA

0

1

WDT Enable bit

MUX

PSA

WDT

Time-Out

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40191A-page 24

Preliminary

1998 Microchip Technology Inc.

PIC16CR54C

7.0SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16C5X family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are:

•Oscillator selection

•Reset

•Power-On Reset (POR)

•Device Reset Timer (DRT)

•Watchdog Timer (WDT)

•SLEEP

•Code protection

The PIC16CR54C Family has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external reset circuitry.

The SLEEP mode is designed to offer a very low current power-down mode. The user can wake up from SLEEP through external reset or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

7.1Configuration Bits

Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type and one bit is the Watchdog Timer enable bit. Nine bits are code protection bits (Figure 7-1 and Figure 7-2) for the PIC16CR54C devices.

ROM devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "Product Identification System" diagrams in the back of this data sheet).

FIGURE 7-1:

CONFIGURATION WORD FOR PIC16CR54C

CP

CP

CP

CP

CP

CP

CP

CP

CP

WDTE

FOSC1

FOSC0

Register:

CONFIG

Address(1):

0FFFh

bit11

10

9

8

7

6

5

4

3

2

1

bit0

bit 11-3:

CP: Code protection bits

1

= Code protection off

0

= Code protection on

bit 2:

WDTE: Watchdog timer enable bit

1

= WDT enabled

0

= WDT disabled

bit 1-0:

FOSC1:FOSC0: Oscillator selection bits

11

= RC oscillator

10

= HS oscillator

01

= XT oscillator

00

= LP oscillator

Note 1: Refer to the PIC16C5X Programming Specification (Literature number DS30190) to determine how to access the configuration word.

1998 Microchip Technology Inc.

Preliminary

DS40191A-page 25

PIC16CR54C

7.2Oscillator Configurations

7.2.1OSCILLATOR TYPES

PIC16CR54Cs can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes:

•	LP:	Low Power Crystal
•	XT:	Crystal/Resonator
•	HS:	High Speed Crystal/Resonator
•	RC:	Resistor/Capacitor

7.2.2CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 7-2). The PIC16CR54C oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 7-3).

FIGURE 7-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

C1(1)	PIC16CR54C
OSC1
XTAL	SLEEP
	RF(3)
	To internal
RS(2) OSC2	logic
C2(1)

Note 1: See Capacitor Selection tables for recommended values of C1 and C2.

2:A series resistor (RS) may be required for AT strip cut crystals.

3:RF varies with the crystal chosen (approx. value = 10 MΩ).

FIGURE 7-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)

Clock from	OSC1
ext. system	PIC16CR54C
Open	OSC2

TABLE 7-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16CR54C

Osc	Resonator	Cap. Range	Cap. Range
Type	Freq	C1	C2
XT	455 kHz	68-100 pF	68-100 pF
	2.0 MHz	15-33 pF	15-33 pF
	4.0 MHz	10-22 pF	10-22 pF
HS	8.0 MHz	10-22 pF	10-22 pF
	16.0 MHz	10 pF	10 pF

These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

TABLE 7-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC16CR54C

Osc	Resonator	Cap.Range	Cap. Range
Type	Freq	C1	C2
LP	32 kHz(1)	15 pF	15 pF
XT	100 kHz	15-30 pF	200-300 pF
	200 kHz	15-30 pF	100-200 pF
	455 kHz	15-30 pF	15-100 pF
	1 MHz	15-30 pF	15-30 pF
	2 MHz	15 pF	15 pF
	4 MHz	15 pF	15 pF
HS	4 MHz	15 pF	15 pF
	8 MHz	15 pF	15 pF
	20 MHz	15 pF	15 pF

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.

These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Note: If you change from this device to another device, please verify oscillator characteristics in your application.

DS40191A-page 26

Preliminary

1998 Microchip Technology Inc.