Microchip Technology Inc 93AA66XTSN, 93AA66XSN, 93AA66TSN, 93AA66TSM, 93AA66TP Datasheet



1996 Microchip Technology Inc. DS20067G-page 1

FEATURES

• Single supply with programming operation down

to 1.8V

• Low power CMOS technology

- 70

µ

A typical active READ current at 1.8V

-2

µ

A typical standby current at 1.8V

• ORG pin selectable memory configuration

- 128 x 8- or 64 x 16-bit organization (93AA46)

- 256 x 8- or 128 x 16-bit organization

(93AA56)

- 512 x 8 or 256 x 16 bit organization (93AA66)

• Self-timed ERASE and WRITE cycles

(including auto-erase)

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during ERASE/WRITE cycles

• Sequential READ function

• 10,000,000 ERASE/WRITE cycles guaranteed on

93AA56 and 93AA66

• 1,000,000 E/W cycles guaranteed on 93AA46

• Data retention > 200 years

• 8-pin PDIP/SOIC

(SOIC in JEDEC and EIAJ standards)

• Temperature ranges supported

DESCRIPTION

The Microchip Technology Inc. 93AA46/56/66 are 1K,

2K and 4K low voltage serial Electrically Erasable

PROMs. The device memory is configured as x8 or x16

bits depending on the ORG pin setup. Advanced

CMOS technology makes these devices ideal for low

power non-volatile memory applications. The 93AA

Series is available in standard 8-pin DIP and surface

mount SOIC packages. The rotated pin-out 93AA46X/

56X/66X are offered in the “SN” package only.

- Commercial (C): 0

°

C to +70

°

C

PACKA GE TYPES

BLOCK DIAGRAM

1

2

3

4

8

7

6

5

CS

CLK

DI

DO

SS

V

NU

ORG

V

CC

1

2

3

4

8

7

6

5

SS

V

NU

ORG

V

CC

CS

CLK

DI

DO

1

2

3

4

8

7

6

5

ORG

Vss

DO

DI

NU

Vcc

CS

CLK

DIP

SOIC

SOIC

93AA46

93AA56

93AA66

93AA46

93AA56

93AA66

93AA46X

93AA56X

93AA66X

MEMORY

ARRAY



ADDRESS

DECODER

V

CC VSS

DATA REGISTER

DO

MODE

DECODE

 LOGIC

CLOCK

GENERATOR

OUTPUT

BUFFER

DI

CS

ORG

CLK

ADDRESS

COUNTER

93AA46/56/66

1K/2K/4K 1.8V Microwire



Serial EEPROM

Microwire is a registered trademark of National Semiconductor Incorporated.

93AA46/56/66

DS20067G-page 2



1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings

V

CC

............................................................................7.0V

All inputs and outputs w.r.t. V

SS

..........-0.6V to V

CC

+1.0V

Storage temperature................................-65˚C to +150˚C

Ambient temp. with power applied...........-65˚C to +125˚C

Soldering temperature of leads (10 seconds)........+300˚C

ESD protection on all pins ......................................... 4 kV

*Notice:

Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

V

SS

Ground

ORG Memory Configuration

NU Not Utilized

V

CC

Power Supply

TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS

V

CC

= +1.8V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C

Parameter Symbol Min Typ Max Units Conditions

High level input voltage V

IH

1 2.0 — V

CC

+1 V V

CC

≥

2.7V

V

IH

2 0.7 V

CC

—V

CC

+1 V V

CC

< 2.7V

Low level input voltage V

IL

1 -0.3 — 0.8 V V

CC

≥

2.7V

V

IL

2 -0.3 — 0.2 V

CC

VV

CC

< 2.7V

Low level output voltage V

OL

1 — — 0.4 V I

OL

= 2.1 mA; V

CC

= 4.5V

V

OL

2 — — 0.2 V I

OL

= 100

µ

A; V

CC

= 1.8V

High level output voltage V

OH

1 2.4 — — V I

OH

= -400

µ

A; V

CC

= 4.5V

V

OH

2V

CC

-0.2 — — V I

OH

= -100

µ

A; V

CC

= 1.8V

Input leakage current I

LI

-10 — 10

µ

AV

IN

= 0.1V to V

CC

Output leakage current I

LO

-10 — 10

µ

AV

OUT

= 0.1V to V

CC

Pin capacitance

(all inputs/outputs)

C

IN

, C

OUT

—— 7 pFV

IN

/V

OUT

= 0V (Note 1 & 2)

Tamb = +25˚C, F

CLK

= 1 MHz

Operating current I

CC

write — — 3 mA F

CLK

=2 MHz; V

CC

=5.5V (Note 2)

I

CC

read — —

70

1

500

mA

µ

A

µ

A

F

CLK

= 2 MHz; V

CC

= 5.5V

F

CLK

= 1 MHz; V

CC

= 3.0V

F

CLK

= 1 MHz; V

CC

= 1.8V

Standby current I

CCS

2

100

30

µ

A

µ

A

µ

A

CLK = CS = 0V; V

CC

= 5.5V

CLK = CS = 0V; V

CC

= 3.0V

CLK = CS = 0V; V

CC

= 1.8V

Clock frequency F

CLK

2

1

MHz

MHz

V

CC

≥

4.5V

V

CC

< 4.5V

Clock high time T

CKH

250 ns

Clock low time T

CKL

250 ns

Chip select setup time T

CSS

50 ns Relative to CLK

Chip select hold time T

CSH

0 ns Relative to CLK

Chip select low time T

CSL

250 ns

Data input setup time T

DIS

100 ns Relative to CLK

Data input hold time T

DIH

100 ns Relative to CLK

Data output delay time T

PD

400 ns CL = 100 pF

Data output disable time T

CZ

100 ns CL = 100 pF (Note 2)

Status valid time T

SV

500 ns CL = 100 pF

Program cycle time T

WC

4 10 ms ERASE/WRITE mode

T

EC

8 15 ms ERAL mode (Vcc = 5V

±

10%)

T

WL

16 30 ms WRAL mode (Vcc = 5V

±

10%)

Endurance

93AA46

93AA56/66

—

—

1M

10M

—

—

1M

10M

—

—

25

°

C, Vcc = 5.0V, Block Mode

(Note 3)

Note 1: This parameter is tested at Tamb = 25

°

C and F

CLK

= 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.



1996 Microchip Technology Inc. DS20067G-page 3

93AA46/56/66

TABLE 1-3: INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION)

TABLE 1-4: INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION)

TABLE 1-5: INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION)

TABLE 1-6: INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION)

TABLE 1-7: INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION)

TABLE 1-8: INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25

EWEN 1 00 1 1 X X X X — High-Z 9

ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY

)9

ERAL 1 00 1 0 X X X X — (RDY/BSY

)9

WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY

)25

WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY

)25

EWDS 1 00 0 0 X X X X — High-Z 9

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18

EWEN 1 00 1 1 X X X X X — High-Z 10

ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY

)10

ERAL 1 00 1 0 X X X X X — (RDY/BSY

)10

WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY

)18

WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY

)18

EWDS 1 00 0 0 X X X X X — High-Z 10

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27

EWEN 1 00 1 1 X X X X X X — High-Z 11

ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY

)11

ERAL 1 00 1 0 X X X X X X — (RDY/BSY

)11

WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY

)27

WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY

)27

EWDS 1 00 0 0 X X X X X X — High-Z 11

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20

EWEN 1 00 1 1 X X X X X X X — High-Z 12

ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY

)12

ERAL 1 00 1 0 X X X X X X X — (RDY/BSY

)12

WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY

)20

WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY

)20

EWDS 1 00 0 0 X X X X X X X — High-Z 12

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27

EWEN 1 00 1 1 X X X X X X — High-Z 11

ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY

)11

ERAL 1 00 1 0 X X X X X X — (RDY/BSY

)11

WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY

)27

WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY) 27

EWDS 1 00 0 0 X X X X X X — High-Z 11

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20

EWEN 1 00 1 1 X X X X X X X — High-Z 12

ERASE 1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY

)12

ERAL 1 00 1 0 X X X X X X X — (RDY/BSY

)12

WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY

)20

WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY

)20

EWDS 1 00 0 0 X X X X X X X — High-Z 12

93AA46/56/66

DS20067G-page 4



1996 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin is connected to V

CC

, the (x16) orga-

nization is selected. When it is connected to ground,

the (x8) organization is selected. Instructions,

addresses and write data are clocked into the DI pin on

the rising edge of the clock (CLK). The DO pin is nor-

mally held in a high-Z state except when reading data

from the device, or when checking the READY/BUSY

status during a programming operation. The ready/

busy status can be verified during an Erase/Write oper-

ation by polling the DO pin; DO low indicates that pro-

gramming is still in progress, while DO high indicates

the device is ready. The DO will enter the high-Z state

on the falling edge of the CS.

2.1 ST

ART Condition

The START bit is detected by the device if CS and DI

are both HIGH with respect to the positive edge of CLK

for the first time.

Before a STAR T condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

STAR T condition), without resulting in any device oper-

ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,

and WRAL). As soon as CS is HIGH, the device is no

longer in the standby mode.

An instruction following a START condition will only be

executed if the required amount of opcode, address

and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new start condition is

detected.

2.2 DI/DO

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero” that

precedes the READ operation, if A0 is a logic HIGH

level. Under such a condition the voltage level seen at

Data Out is undefined and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin.

2.3 Data Protection

During power-up, all programming modes of operation

are inhibited until V

CC has reached a level greater than

1.4V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

V

CC has fallen below 1.4V at nominal conditions.

The EWEN and EWDS commands give additional pro-

tection against accidentally programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction can

be executed.

2.4 READ

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 16 bit (x16 organization) or 8 bit

(x8 organization) output string. The output data bits will

toggle on the rising edge of the CLK and are stable after

the specified time delay (T

PD). Sequential read is pos-

sible when CS is held high. The memory data will auto-

matically cycle to the next register and output

sequentially.

2.5 Erase/Write Enable and Disable

(EWEN,EWDS)

The 93AA46/56/66 power up in the Erase/Write Disable

(EWDS) state. All programming modes must be pre-

ceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or V

CC is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be

used to disable all Erase/Write functions and should fol-

low all programming operations. Execution of a READ

instruction is independent of both the EWEN and

EWDS instructions.

2.6 ERASE

The ERASE instruction forces all data bits of the spec-

ified address to the logical “1” state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed programming

cycle.

The DO pin indicates the READY/BUSY

status of the

device if CS is brought high after a minimum of 250 ns

low (T

CSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the specified address has been erased

and the device is ready for another instruction.

The ERASE cycle takes 4 ms per word typical.

2.7 WRITE

The WRITE instruction is followed by 16 bits (or by 8

bits) of data which are written into the specified

address. After the last data bit is put on the DI pin, CS

must be brought low before the next rising edge of the

CLK clock. This falling edge of CS initiates the self-

timed auto-erase and programming cycle.

The DO pin indicates the READY/BUSY

status of the

device if CS is brought high after a minimum of 250 ns

low (T

CSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the specified address has been written with the data

specified and the device is ready for another instruc-

tion.

The WRITE cycle takes 4 ms per word typical.