Microchip Technology Inc 25LC160T-I-SN, 25LC160T-I-P, 25LC160T-SN, 25LC160T-P, 25LC160-I-SN Datasheet

25LC080/160

8K/16K 2.5V SPI Bus Serial EEPROM

FEATURES

•SPI modes 0,0 and 1,1

•3 MHz Clock Rate

•Single supply with programming operation down to 2.5V

•Low Power CMOS Technology

-Max Write Current: 5 mA

-Read Current: 1.0 mA

-Standby Current: 1 A typical

•Organization

-1024 x 8 for 25LC080

-2048 x 8 for 25LC160

•16 Byte Page

•Sequential Read

•Self-timed ERASE and WRITE Cycles

•Block Write Protection

-Protect none, 1/4, 1/2, or all of Array

•Built-in Write Protection

-Power On/Off Data Protection Circuitry

-Write Latch

-Write Protect Pin

•High Reliability

-Endurance: 10M cycles (guaranteed)

-Data Retention: >200 years

-ESD protection: >4000 V

•8-pin PDIP/SOIC Packages

•Temperature ranges supported

-	Commercial (C):	0°C	to	+70°C
-	Industrial (I):	-40°C	to	+85°C

DESCRIPTION

The Microchip Technology Inc. 25LC080/160 are 8K and 16K bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus.

There are two other inputs that provide the end user with additional flexibility. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. Also, write operations to the Status Register can be disabled via the write protect pin (WP).

SPI is a trademark of Motorola.

PACKAGE TYPES

PDIP

	CS		1		8	VCC
				25LC080/160
SO			2		7		HOLD
			3		6		SCK
WP
VSS			4		5		SI

SOIC

						1		8				VCC
	CS						25LC080/160
SO						2		7
								6				HOLD
						3						SCK
WP
VSS						4		5				SI

BLOCK DIAGRAM

	Status		HV Generator
	Register
			EEPROM
	I/O Control	Memory	X
		Control	Array
	Logic
		Logic	Dec
			Page Latches
	WP
	SI
	SO		Y Decoder
	CS
	SCK
	HOLD		Sense Amp.
			R/W Control
		Vcc
		Vss

1996 Microchip Technology Inc.

Preliminary

DS21145D-page 1

25LC080/160

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC........................................................................	7.0V
All inputs and outputs w.r.t. VSS......	-0.6V to VCC +1.0V
Storage temperature .............................	-65˚C to 150˚C
Ambient temperature under bias...........	-65˚C to 125˚C

Soldering temperature of leads (10 seconds) ...	+300˚C
ESD protection on all pins......................................	4kV

*Notice: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended period of time may affect device reliability

TABLE 1-1: PIN FUNCTION TABLE

	Name					Function
						Chip Select Input
		CS
		SO				Serial Data Output
		SI				Serial Data Input
	SCK					Serial Clock Input
						Write Protect Pin
		WP
	VSS					Ground
	VCC					Supply Voltage
						Hold Input
	HOLD

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: AC TEST CIRCUIT

Vcc

2.25 K

SO

1.8 K 100 pF

1.2AC Test Conditions

AC Waveform:
VLO = 0.2V
VHI = Vcc - 0.2V	(Note 1)
VHI = 4.0V	(Note 2)
Timing Measurement Reference Level
Input	0.5 VCC
Output	0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V

Applicable over recommended operating ranges shown below unless otherwise noted.

VCC = +2.5V to +5.5V
Commercial (C):	Tamb =	0˚C to +70˚C
Industrial (I):	Tamb = -40˚C to +85˚C
Parameter		Symbol		Min	Max	Units				Test Conditions
High level input voltage		VIH1		2.0	VCC+1	V		VCC ≥ 2.7V
		VIH2		0.7 VCC	VCC+1	V		VCC< 2.7V
Low level input voltage		VIL1		-0.3	0.8	V		VCC ≥ 2.7V
		VIL2		-0.3	0.3 VCC	V		VCC< 2.7V
Low level output voltage		VOL		—	0.4	V	I OL=2.1 mA
High level output voltage		VOH		VCC-0.5	—	V	I OH=-400 A
Input leakage current		ILI		-10	10	A
								CS=VIH, VIN=VSS to VCC
Output leakage current		ILO		-10	10	A
								CS=VIH, VOUT=VSS to VCC
Internal Capacitance		CINT		—	7	pF	Tamb=25˚C, F CLK=3.0 MHz,
(all inputs and outputs)								VCC=5.5V (Note)
Operating Current		ICC WRITE		—	5	mA		VCC=5.5V
				—	3	mA		VCC=2.5V
		ICC READ		—	1	mA	VCC=5.5V; 3 MHz
				—	500	A		VCC=2.5V; 2 MHz
Standby Current		ICCS		—	5	A
								CS=VCC=5.5V; Vin=0V or VCC
				—	2	A
								CS=VCC=2.5V; Vin=0V or VCC

Note: This parameter is periodically sampled and not 100% tested.

DS21145D-page 2

Preliminary

1996 Microchip Technology Inc.

25LC080/160

FIGURE 1-2: SERIAL INPUT TIMING

			tCSD
CS
	tCSS	t	tCLD
		R	tCSH
		tF
SCK
tSU		tHD
SI	MSB in		LSB in
SO		high impedance
FIGURE 1-3: SERIAL OUTPUT TIMING
CS

	tHI		tLO			tCSH
SCK
		tV	tHO			tDIS
SO		MSB out				LSB out
SI			don’t care
FIGURE 1-4: HOLD TIMING
CS
		tHS	tHH	tHS	tHH
SCK
			tHZ		tHV
SO	n+2	n+1	high impedance		n	n-1
			n
			don’t care		tSU
SI	n+2	n+1	n		n	n-1
HOLD

1996 Microchip Technology Inc.

Preliminary

DS21145D-page 3

25LC080/160

TABLE 1-3:		AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted.
VCC = +2.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):		Tamb = -40˚C to +85˚C
Symbol				Parameter	Min	Max	Units		Test Conditions
fSCK		Clock Frequency			—	3	MHz		VCC=4.5V to 5.5V
					—	2	MHz		VCC=2.5V to 4.5V
tCSS			Setup Time		100	—	ns		VCC=4.5V to 5.5V
		CS
					250	—	ns		VCC=2.5V to 4.5V
tCSH			Hold Time		100	—	ns		VCC=4.5V to 5.5V
		CS
					250	—	ns		VCC=2.5V to 4.5V
tCSD			Disable Time		250	—	ns		VCC=4.5V to 5.5V
		CS
					500	—	ns		VCC=2.5V to 4.5V
tSU		Data Setup Time			30	—	ns		VCC=4.5V to 5.5V
					50	—	ns		VCC=2.5V to 4.5V
tHD		Data Hold Time			50	—	ns		VCC=4.5V to 5.5V
					100	—	ns		VCC=2.5V to 4.5V
tR		CLK Rise Time			—	2	s		(Note 1)
tF		CLK Fall Time			—	2	s		(Note 1)
tHI		Clock High Time			150	—	ns		VCC=4.5V to 5.5V
					250	—	ns		VCC=2.5V to 4.5V
tLO		Clock Low Time			150	—	ns		VCC=4.5V to 5.5V
					250	—	ns		VCC=2.5V to 4.5V
tCLD		Clock Delay Time			50	—	ns
tV		Output Valid from			—	150	ns		VCC=4.5V to 5.5V
		Clock Low			—	250	ns		VCC=2.5V to 4.5V
tHO		Output Hold Time			0	—	ns
tDIS		Output Disable Time			—	200	ns		VCC=4.5V to 5.5V (Note 1)
					—	250	ns		VCC=2.5V to 4.5V (Note 1)
tHS				Setup Time	100	—	ns		VCC=4.5V to 5.5V
		HOLD
					100	—	ns		VCC=2.5V to 4.5V
tHH				Hold Time	100	—	ns		VCC=4.5V to 5.5V
		HOLD
					100	—	ns		VCC=2.5V to 4.5V
tHZ				Low to Output High-Z	100	—	ns		VCC=4.5V to 5.5V (Note 1)
		HOLD
					150	—	ns		VCC=2.5V to 4.5V (Note 1)
tHV				High to Output Valid	100	—	ns		VCC=4.5V to 5.5V (Note 1)
		HOLD
					150	—	ns		VCC=2.5V to 4.5V (Note 1)
tWC		Internal Write Cycle Time			—	5	ms		(Note 2)
—	Endurance				10M	—	E/W Cycles	25 °C, Vcc = 5.0V, Block Mode
									(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.

2:tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write cycle is complete.

3:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

DS21145D-page 4

Preliminary

1996 Microchip Technology Inc.