Microchip Technology Inc 24C04AT-I-SN, 24C04AT-I-SM, 24C04AT-SL, 24C04AT-P, 24C04A-I-SN Datasheet

24C01A/02A/04A

1K/2K/4K 5.0V I2C Serial EEPROMs

FEATURES

•Low power CMOS technology

•Hardware write protect

•Two wire serial interface bus, I2C compatible

•5.0V only operation

•Self-timed write cycle (including auto-erase)

•Page-write buffer

•1ms write cycle time for single byte

•1,000,000 Erase/Write cycles guaranteed

•Data retention >200 years

•8-pin DIP/SOIC packages

•Available for extended temperature ranges

-	Commercial (C):	0˚C	to	+70˚C
-	Industrial (I):	-40˚C	to	+85˚C
-	Automotive (E):	-40˚C	to	+125˚C

DESCRIPTION

The Microchip Technology Inc. 24C01A/02A/04A is a 1K/2K/4K bit Electrically Erasable PROM. The device is organized as shown, with a standard two wire serial interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A special feature in the 24C02A and 24C04A provides hardware write protection for the upper half of the block. The 24C01A and 24C02A have a page write capability of two bytes and the 24C04A has a page length of eight bytes. Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the same two wire bus.

This device offers fast (1ms) byte write and extended (-40°C to 125°C) temperature operation. It is recommended that all other applications use Microchip’s 24LCXXB.

	24C01A	24C02A	24C04A
Organization	128 x 8	258 x 8	2 x	256 x 8
Write Protect	None	080-0FF	100-1FF
Page Write	2 Bytes	2 Bytes	8	Bytes
Buffer

I2C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

PACKAGE TYPES

DIP	A0						1						8			VCC
	A1						2			24C04A	24C02A	24C01A	7			WP*
	A2						3						6			SCL
8-lead	VSS						4						5			SDA
SOIC	A0							1		24C04A	24C02A	24C01A	8				VCC
								2					7
	A2																SCL
								3					6
	A1							4					5				WP*
14-lead	VSS																SDA
									1				14				NC
SOIC	NC
									2				13
	A0																VCC
									3	24C04A	24C02A	24C01A	12
	A1																WP
													11
	NC								4								NC
									5				10
	A2																SCL
													9
	VSS																SDA
									6
									7				8
	NC																NC

* “TEST” pin in 24C01A

BLOCK DIAGRAM

	Vcc	Data		Vpp		R/W Amp
		Buffer
	Vss
		(FIFO)
		Data Reg.	A P
			d o			Memory
	SDA		d	i
		Slave Addr.	r	n	A0 to	Array
			e	t	A7
			s e
			s	r
	SCL	Control		Increment		A8
		Logic
		A0 A1 A2 WP
					DS11183D-page 1

24C01A/02A/04A

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. VSS ...............	-0.6V to VCC +1.0V
Storage temperature .....................................		-65˚C to +150˚C
Ambient temp. with power applied ................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins................................................		4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1:	PIN FUNCTION TABLE
Name	Function
A0	No Function for 24C04A only, Must
	be connected to VCC or VSS
A0, A1, A2	Chip Address Inputs
VSS	Ground
SDA	Serial Address/Data I/O
SCL	Serial Clock
TEST	(24C01A only) VCC or VSS
WP	Write Protect Input
VCC	+5V Power Supply

TABLE 1-2:	DC CHARACTERISTICS
VCC = +5V (±10%)			Commercial (C): Tamb =				0°C to +70°C
			Industrial (I):		Tamb =		-40°C to +85°C
			Automotive (E):		Tamb =		-40°C to +125°C
Parameter		Symbol	Min.	Max.		Units		Conditions
VCC detector threshold		VTH	2.8	4.5			V
SCL and SDA pins:
High level input voltage		VIH	VCC x 0.7	VCC + 1			V
Low level input voltage		VIL	-0.3	VCC x 0.3			V
Low level output voltage		VOL		0.4			V	IOL = 3.2 mA (SDA only)
A1 & A2 pins:
High level input voltage		VIH	VCC - 0.5	VCC + 0.5			V
Low level input voltage		VIL	-0.3	0.5			V
Input leakage current		ILI	—	10			A	VIN = 0V to VCC
Output leakage current		ILO	—	10			A	VOUT = 0V to VCC
Pin capacitance		CIN,	—	7.0		pF		V IN/VOUT = 0V (Note)
(all inputs/outputs)		COUT						Tamb = +25˚C, f = 1 MHz
Operating current		ICC Write	—	3.5		mA		F CLK = 100 kHz, program cycle time = 1 ms,
								Vcc = 5V, Tamb = 0˚C to +70˚C
		ICC Write	—	4.25		mA		F CLK = 100 kHz, program cycle time = 1 ms,
								Vcc = 5V, Tamb = (I) and (E)
		ICC	—	750			A	VCC = 5V, Tamb= (C), (I) and (E)
		Read
Standby current		ICCS	—	100			A	SDA=SCL=VCC=5V (no PROGRAM active)

Note: This parameter is periodically sampled and not 100% tested

FIGURE 1-1:	BUS TIMING START/STOP
		VHYS
SCL
	THD:STA
TSU:STA		TSU:STO
SDA
	START	STOP

DS11183D-page 2

1996 Microchip Technology Inc.

24C01A/02A/04A

TABLE 1-3:	AC CHARACTERISTICS
Parameter		Symbol		Min.	Typ	Max.	Units	Remarks
Clock frequency		FCLK		—	—	100	kHz
Clock high time		THIGH		4000	—	—	ns
Clock low time		TLOW		4700	—	—	ns
SDA and SCL rise time		TR		—	—	1000	ns
SDA and SCL fall time		TF		—	—	300	ns
START condition hold time		THD:STA		4000	—	—	ns	After this period the first
								clock pulse is generated
START condition setup time		TSU:STA		4700	—	—	ns	Only relevant for repeated
								START condition
Data input hold time		THD:DAT		0	—	—	ns
Data input setup time		TSU:DAT		250	—	—	ns
Data output delay time		TAA		300	—	3500		(Note 1)
STOP condition setup time		TSU:STO		4700	—	—	ns
Bus free time		TBUF		4700	—	—	ns	Time the bus must be free
								before a new transmission
								can start
Input filter time constant		TI		—	—	100	ns
(SDA and SCL pins)
Program cycle time		TWC		—	.4	1	ms	Byte mode
					.4N	N	ms	Page mode, N=# of bytes
Endurance		—		1M	—	—	cycles	25 °C, Vcc = 5.0V, Block
								Mode (Note 2)

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

		TF			TR
			THIGH
		TLOW
SCL
	TSU:STA		THD:DAT	TSU:DAT	TSU:STO
		THD:STA
SDA	TSP
IN
	TAA	THD:STA	TAA		TBUF
SDA
OUT

1996 Microchip Technology Inc.

DS11183D-page 3

24C01A/02A/04A

2.0FUNCTIONAL DESCRIPTION

The 24C01A/02A/04A supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C01A/02A/04A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.

Up to eight 24C01/24c02s can be connected to the bus, selected by the A0, A1 and A2 chip address inputs. Up to four 24C04As can be connected to the bus, selected by A1 and A2 chip address inputs. A0 must be tied to VCC or VSS for the 24C04A. Other devices can be connected to the bus but require different device codes than the 24C01A/02A/04A (refer to section Slave Address).

3.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24C01A/02A/04A does not generate any acknowledge bits if an internal programming cycle is in progress.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)	(B)	(D)	(D)	(C)	(A)
SCL
SDA
	START	ADDRESS OR	DATA	STOP
CONDITION		ACKNOWLEDGE	ALLOWED	CONDITION
		VALID	TO CHANGE

DS11183D-page 4

1996 Microchip Technology Inc.